RapidIO高速互连接口PCS层的设计与验证
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摘要
嵌入式处理技术的快速发展,给高性能嵌入式系统的高速互联方面带来了严峻的挑战。为了应对这类挑战,同时适应嵌入式系统的发展需要,业界领先的半导体和系统制造商联合制订了一种可实现任意拓扑和点对点操作、高效且具有很高可靠性和有效拥塞控制的高速互联协议--RapidIO。作为目前世界上第一个、也是唯一的嵌入式系统互连国际标准,RapidIO互连架构通过定义一种高性能包交换互连技术有效地消除了系统互连瓶颈。
文中从多个方面对新一代高速互连技术—RapidIO串行物理层中的物理编码子层(PCS层)进行了研究,具体如下:
1.首先对串行RapidIO协议结构进行了深入研究。串行RapidIO协议分为三层,逻辑层、传输层、物理层。这种三层体系结构的最大优点是,在任意层对事务类型进行修改都不会影响到其它层的规范,具有很强的灵活可变性。
2.通过对协议结构的研究分析,本文设计了串行RapidIO物理层中的物理编码子层。实现了对包的物理层字段的封装、端口的初始化、包的发送和接收、流量控制、错误管理等操作。分析了循环冗余校验码的原理并予以实现。研究了8B/10B编解码的原理并予以实现。
3.设计了物理编码子层中的缓存模块,该模块解决了物理层和逻辑层之间的数据传输问题,并且实现了协议所必须的接收端流量控制功能。
4.完成了串行RapidIO物理编码子层以及缓存模块的RTL级代码设计与功能验证。验证结果表明发送通路、接收通路以及错误管理功能正确,实现了协议所要求的接收端流量控制功能,符合串行RapidIO1.3协议标准,为开发和研制新一代用于嵌入式数字信号处理芯片的高速串口打下了良好基础。
The fast development of embedded processing technology is posed a serious challenge to high-performance embedded system high-speed interconnection. In order to cope with such challenges and meet the needs of embedded system development, the industry's leading semiconductor and system manufacturers work together to set up a high-speed Internet Protocol--RapidIO. The RapidIO interconnect architecture, the first and only international standard at the system interconnect level, eliminates this bottleneck by defining a high-performance, packet-switched interconnect technology.
This paper analyzes the new generation high-speed interconnect technology--RapidIO physical coding sublayer of serial physical layer.from various aspects, the main results are as follows:
1. First of all, this dissertation carries out study on the structure of Serial RapidIO protocol. Serial RapidIO protocol is divided into three layers: logical layer, transport layer, physical layer. Such a three layers structure characterized by a layer of affairs in any type of change will not affect other layers of the norms is highly flexible and variable.
2. Based on results of the RapidIO protocol analysis, this dissertation does logic implementation of the serial physical layer’s physical coding sublayer. These logics achieve,i.e,complete the physical layer packet field encapsulation、in charge of port initialization、sending and receiving packets and control symbols、flow control、error management and other operations. This dissertation analyzes theory of cyclic redundancy check and does logic implementation of it. This dissertation analyzes theory of cyclic redundancy check and does logic implementation of it. This dissertation analyzes theory of 8B/10B codec and does logic implementation of it.
3. This dissertation does logic implementation of the buffer module in physical coding sublayer. This module resolves problem of data transfer between logical layer and physical layer, and carries out the function of receiver-controlled flow control which protocol requires.
4. After the accomplishment of the serial RapidIO physical coding sublayer and buffer module design and logic implementation, this dissertation does RTL simulation immediately for the implementation of the logic code. Throughout the physical coding sublayer simulation of the sending channel, receiving channel, error management function and flow control function, it verifies that the functions are correct inaccordanced with the RapidIO 1.3 protocol version. Lay a good foundation for developing new generation high-speed serial port of embedded digital signal processing chips.
文中从多个方面对新一代高速互连技术—RapidIO串行物理层中的物理编码子层(PCS层)进行了研究,具体如下:
1.首先对串行RapidIO协议结构进行了深入研究。串行RapidIO协议分为三层,逻辑层、传输层、物理层。这种三层体系结构的最大优点是,在任意层对事务类型进行修改都不会影响到其它层的规范,具有很强的灵活可变性。
2.通过对协议结构的研究分析,本文设计了串行RapidIO物理层中的物理编码子层。实现了对包的物理层字段的封装、端口的初始化、包的发送和接收、流量控制、错误管理等操作。分析了循环冗余校验码的原理并予以实现。研究了8B/10B编解码的原理并予以实现。
3.设计了物理编码子层中的缓存模块,该模块解决了物理层和逻辑层之间的数据传输问题,并且实现了协议所必须的接收端流量控制功能。
4.完成了串行RapidIO物理编码子层以及缓存模块的RTL级代码设计与功能验证。验证结果表明发送通路、接收通路以及错误管理功能正确,实现了协议所要求的接收端流量控制功能,符合串行RapidIO1.3协议标准,为开发和研制新一代用于嵌入式数字信号处理芯片的高速串口打下了良好基础。
The fast development of embedded processing technology is posed a serious challenge to high-performance embedded system high-speed interconnection. In order to cope with such challenges and meet the needs of embedded system development, the industry's leading semiconductor and system manufacturers work together to set up a high-speed Internet Protocol--RapidIO. The RapidIO interconnect architecture, the first and only international standard at the system interconnect level, eliminates this bottleneck by defining a high-performance, packet-switched interconnect technology.
This paper analyzes the new generation high-speed interconnect technology--RapidIO physical coding sublayer of serial physical layer.from various aspects, the main results are as follows:
1. First of all, this dissertation carries out study on the structure of Serial RapidIO protocol. Serial RapidIO protocol is divided into three layers: logical layer, transport layer, physical layer. Such a three layers structure characterized by a layer of affairs in any type of change will not affect other layers of the norms is highly flexible and variable.
2. Based on results of the RapidIO protocol analysis, this dissertation does logic implementation of the serial physical layer’s physical coding sublayer. These logics achieve,i.e,complete the physical layer packet field encapsulation、in charge of port initialization、sending and receiving packets and control symbols、flow control、error management and other operations. This dissertation analyzes theory of cyclic redundancy check and does logic implementation of it. This dissertation analyzes theory of cyclic redundancy check and does logic implementation of it. This dissertation analyzes theory of 8B/10B codec and does logic implementation of it.
3. This dissertation does logic implementation of the buffer module in physical coding sublayer. This module resolves problem of data transfer between logical layer and physical layer, and carries out the function of receiver-controlled flow control which protocol requires.
4. After the accomplishment of the serial RapidIO physical coding sublayer and buffer module design and logic implementation, this dissertation does RTL simulation immediately for the implementation of the logic code. Throughout the physical coding sublayer simulation of the sending channel, receiving channel, error management function and flow control function, it verifies that the functions are correct inaccordanced with the RapidIO 1.3 protocol version. Lay a good foundation for developing new generation high-speed serial port of embedded digital signal processing chips.
引文
[1] RapidIO嵌入式系统互连总线概述[EB/OL].www.resys.cn.
[2] Sam Fuller等著,王勇等译.RapidIO嵌入式系统互连[M].北京,电子工业出版社,2006.
[3] Dan Bouvier. An Embedded System Component Network Architecture. RapidIO Technical Working Group, 2001.
[4] RapidIO适用于关键性嵌入式系统[EB/OL].www.hqew.com/ 20071.html.
[5] Virtex-4 RocketIO Multi-Gigabit Transceiver Guide[EB/OL]. www.xilinx.com.
[6]潘国振.系统传输标准协议的研究与电路设计.硕士学位论文,浙江大学,2004.
[7] Choosing the right Arch for Real-time Singnal Processing Design White Paper[Z]. www.ti.com.com.
[8]崔维嘉.新一代的总线结构-RapidIO.通信技术,2001,31(1).
[9] Tsi574 Serial RapidIO Switch User Manual[EB/OL]. www.tundra.com.
[10]林琌.RapidIO在多处理器系统互联中的应用.计算机工程,2006,32(4).
[11] Chris Spear. SystemVerilog for Verification. 2008, Springer Science+Business Media, LLC.
[12]以太网与RapidIO的对比[EB/OL].www.zcom.com/mag2.html.
[13]冯华亮.串行RapidIO:高性能嵌入式互连技术[J].今日电子,2007,28(7).
[14] RapidIOTM Interconnect Specification, Part 8: Error Management Extentions Specification. Trade Association. 2005.
[15]王欣,杨涛,傅丰林.RapidIO互连技术研究[J].电子科技,2008,39(4).
[16] Xiongkui Zhang, Meiguo Gao, Guoman Liu, A Scalable Heterogeneous Multi-Processor Signal Processing System Based on the RapidIO Interconnect. IEEE Computer Society. 2008.
[17] Jan M. Ravery. Digital Integrated circuits: a design perspective. Prentice-Hall Inc, 1999.
[18] RapidIO Interconnect Specification, Part 1: Input/Output Logical Specification. Trade Association. 2005.
[19]刘洁,何宾,韩月秋.基于FPGA的RapidIO核接口芯片的设计和实现[J].微计算机应用. 2004,25(9).
[20] RapidIO Interconnect Specification, Part 2: Message Passing Logical Specification. Trade Association.2005.
[21]梁基,金亨科,徐炜民,郑衍衡,沈文枫.基于RapidIO的高性能通信接口的设计与实现.计算机应用与软件[J], 2009, 26(7).
[22] RapidIO Interconnect Specification, Part 3: Common Transport Specification. Trade Association.2005.
[23] LogiCORE IP Serial RapidIO v5.1 User Guide. www.xilinx.com
[24] RapidIO Interconnect Specification, Part 6: 1x/4x LP-Serial Physical Layer Specification. Trade Association. 2005.
[25]张平安.16位循环冗余校验码(CRC)的原理和性能分析[J].山西科技,2005,22(5).
[26]廖海红.通信系统中的CRC算法的研究和工程实现.硕士学位论文,北京邮电大学,2006.
[27] Tom Shanley, Don Anderson.PCI system architecture.北京,电子工业出版社,2000.
[28]杜旭.基于FPGA的高速串行传输接口的设计与实现[J].计算机工程与应用,2007, 43(12).
[29] Dan Bouvier. An embedded system component network architecture. RapidIO technica group. 2001.
[30] David Bueno, Adam Leko, Chris Conger, Ian Troxel, Alan D. George. Simulative Analysis of the RapidIO Embedded Interconnect Architecture. IEEE Computer Society Press and Wiley. the 29th Annual IEEE International Conference.
[31] RapidIO Interconnect Specification Rev1.3 Part 7: System and Device Inter-operability Specification. RapidIO Trade Association. 2005.
[32] Mindshare.Inc. Tom Shanley. PCI-X系统的体系结构[M].北京,清华大学出版社,2002.
[33]贺传峰,戴居丰,毛陆虹.一种新的8B/10B编解码硬件设计方法[J].高技术通讯,2005, 5(3).
[34]刘智,宁红英,王普昌.一种新的8B/10B编码电路设计[J].通信技术,2009,18(7).
[35] Xiaojun Yang, Tao Liu, Fei Chen, Hailiang Cheng, MemoryIO: an Extended I/O Technology in Embedded Systems. IEEE Computer Society. 2008.
[36] PCI Express TM Base Specification Revision 1.1. PCI-SIG. 2005.
[37] LogiCORE IP Serial RapidIO Physical Layer v4.3 User Guide. www.xilinx.com
[38]黄先春,黄登山,骆艳卜.RapidIO链的设计方案和应用[J].计算机工程与应用,2009, 12(32).
[39] H.Jin, T.Cortes, R.Buyya. Storage and Parallel I/O: Technologies and Applications. IEEE Computer Society Press and Wiley. 2001.
[40] Martin MCKWZ, Transporting multiple classes of traffic over a generic routing device–Aninvestigation into the performance of the RapidIO interconnect architecture. IEEE. 2003.
[41]谢智勇,罗明,蒋俊.串行RapidIO验证模型.计算机工程[J],2008,34(8).
[42]赵博龙,赵云忠,孔德岐.RapidIO互连技术研究及其模型验证[J].航空计算技术,2009, 39(4).
[43] Janick Bergeron, Eduard Cerny, Alan Hunter, Andrew Nightingale. Verification Methodology Manual for SystemVerilog. 2006, Springer Science+Business Media, inc.
[2] Sam Fuller等著,王勇等译.RapidIO嵌入式系统互连[M].北京,电子工业出版社,2006.
[3] Dan Bouvier. An Embedded System Component Network Architecture. RapidIO Technical Working Group, 2001.
[4] RapidIO适用于关键性嵌入式系统[EB/OL].www.hqew.com/ 20071.html.
[5] Virtex-4 RocketIO Multi-Gigabit Transceiver Guide[EB/OL]. www.xilinx.com.
[6]潘国振.系统传输标准协议的研究与电路设计.硕士学位论文,浙江大学,2004.
[7] Choosing the right Arch for Real-time Singnal Processing Design White Paper[Z]. www.ti.com.com.
[8]崔维嘉.新一代的总线结构-RapidIO.通信技术,2001,31(1).
[9] Tsi574 Serial RapidIO Switch User Manual[EB/OL]. www.tundra.com.
[10]林琌.RapidIO在多处理器系统互联中的应用.计算机工程,2006,32(4).
[11] Chris Spear. SystemVerilog for Verification. 2008, Springer Science+Business Media, LLC.
[12]以太网与RapidIO的对比[EB/OL].www.zcom.com/mag2.html.
[13]冯华亮.串行RapidIO:高性能嵌入式互连技术[J].今日电子,2007,28(7).
[14] RapidIOTM Interconnect Specification, Part 8: Error Management Extentions Specification. Trade Association. 2005.
[15]王欣,杨涛,傅丰林.RapidIO互连技术研究[J].电子科技,2008,39(4).
[16] Xiongkui Zhang, Meiguo Gao, Guoman Liu, A Scalable Heterogeneous Multi-Processor Signal Processing System Based on the RapidIO Interconnect. IEEE Computer Society. 2008.
[17] Jan M. Ravery. Digital Integrated circuits: a design perspective. Prentice-Hall Inc, 1999.
[18] RapidIO Interconnect Specification, Part 1: Input/Output Logical Specification. Trade Association. 2005.
[19]刘洁,何宾,韩月秋.基于FPGA的RapidIO核接口芯片的设计和实现[J].微计算机应用. 2004,25(9).
[20] RapidIO Interconnect Specification, Part 2: Message Passing Logical Specification. Trade Association.2005.
[21]梁基,金亨科,徐炜民,郑衍衡,沈文枫.基于RapidIO的高性能通信接口的设计与实现.计算机应用与软件[J], 2009, 26(7).
[22] RapidIO Interconnect Specification, Part 3: Common Transport Specification. Trade Association.2005.
[23] LogiCORE IP Serial RapidIO v5.1 User Guide. www.xilinx.com
[24] RapidIO Interconnect Specification, Part 6: 1x/4x LP-Serial Physical Layer Specification. Trade Association. 2005.
[25]张平安.16位循环冗余校验码(CRC)的原理和性能分析[J].山西科技,2005,22(5).
[26]廖海红.通信系统中的CRC算法的研究和工程实现.硕士学位论文,北京邮电大学,2006.
[27] Tom Shanley, Don Anderson.PCI system architecture.北京,电子工业出版社,2000.
[28]杜旭.基于FPGA的高速串行传输接口的设计与实现[J].计算机工程与应用,2007, 43(12).
[29] Dan Bouvier. An embedded system component network architecture. RapidIO technica group. 2001.
[30] David Bueno, Adam Leko, Chris Conger, Ian Troxel, Alan D. George. Simulative Analysis of the RapidIO Embedded Interconnect Architecture. IEEE Computer Society Press and Wiley. the 29th Annual IEEE International Conference.
[31] RapidIO Interconnect Specification Rev1.3 Part 7: System and Device Inter-operability Specification. RapidIO Trade Association. 2005.
[32] Mindshare.Inc. Tom Shanley. PCI-X系统的体系结构[M].北京,清华大学出版社,2002.
[33]贺传峰,戴居丰,毛陆虹.一种新的8B/10B编解码硬件设计方法[J].高技术通讯,2005, 5(3).
[34]刘智,宁红英,王普昌.一种新的8B/10B编码电路设计[J].通信技术,2009,18(7).
[35] Xiaojun Yang, Tao Liu, Fei Chen, Hailiang Cheng, MemoryIO: an Extended I/O Technology in Embedded Systems. IEEE Computer Society. 2008.
[36] PCI Express TM Base Specification Revision 1.1. PCI-SIG. 2005.
[37] LogiCORE IP Serial RapidIO Physical Layer v4.3 User Guide. www.xilinx.com
[38]黄先春,黄登山,骆艳卜.RapidIO链的设计方案和应用[J].计算机工程与应用,2009, 12(32).
[39] H.Jin, T.Cortes, R.Buyya. Storage and Parallel I/O: Technologies and Applications. IEEE Computer Society Press and Wiley. 2001.
[40] Martin MCKWZ, Transporting multiple classes of traffic over a generic routing device–Aninvestigation into the performance of the RapidIO interconnect architecture. IEEE. 2003.
[41]谢智勇,罗明,蒋俊.串行RapidIO验证模型.计算机工程[J],2008,34(8).
[42]赵博龙,赵云忠,孔德岐.RapidIO互连技术研究及其模型验证[J].航空计算技术,2009, 39(4).
[43] Janick Bergeron, Eduard Cerny, Alan Hunter, Andrew Nightingale. Verification Methodology Manual for SystemVerilog. 2006, Springer Science+Business Media, inc.