可重配置的时钟精确嵌入式处理器仿真平台的研究
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摘要
在过去的几十年内,指令集仿真器成为了嵌入式处理器设计过程中必不可少的一部分。它在已有的计算机系统上为开发中的处理器构造一个模拟平台,验证处理器的正确性和有效性,支持目标程序的运行和调试。硬件设计者用仿真器来评估目标处理器的性能,修改体系结构中的瓶颈。系统开发者用仿真器来开发编译器和操作系统,开发和测试他们的应用程序,实现软硬件协同开发
本文研究了软件仿真器的设计方法和软硬件协同仿真的实现方法,针对自主研发的嵌入式处理器CK510,用C/C++开发了一套可配置的时钟精确的软件仿真平台,这个平台里包括时钟精确的软件仿真器,AMBA AHB总线功能模型,以及实现协同仿真的PLI接口。仿真器采用的是基于解释的仿真策略,执行驱动的实现方式,完整的建模了CPU的流水线结构、中断处理器机制。
本文所设计的软件仿真平台最大的特点在于有很强的可配置性,不仅软件仿真器的模型可以配置,而且仿真的环境也可以根据需要配置。仿真平台可以运行在C++的模型下,根据仿真的目的选择是否需要总线功能模型;也可以运行在Verilog的环境下,通过PLI接口实现协同仿真。灵活的仿真环境可满足不同用户的需求。
In the last decades, instruction set simulator has became an essential development tool for the design of embedded processor. It is a simulation platform that builds on the existing computer system for an under developing processor. Designers can execute programs on these models to validate the performance and correctness of a proposed hardware design. Programmers can use this software models to develop and test software before the real hardware becomes available.This thesis studied the design methods of instruction set simulator, and the implementation of hardware-software co-simulation. We develop a software simulation platform with C/C++. This platform contains a reconfigurable cycle accurate instruction set simulator, whose target processor is CK510, an embedded processor developed by Zhejiang University. It also contains a bus function model of AMBA AHB, and a Procedure Language Interface (PLI) developed with VPI library. Our instruction set simulator is an interpretive simulator, which implements with execution driven approach. In order to get accurate simulation result, it models the pipeline architecture and exception handle of CK510 completely.The cycle-accurate simulation flat is reconfigurable. Foremost, the instrunction set simulator is reconfigurable, users can modify the cache size, associative way number, the size of branch history table, the big endian or little endian. Secondly, the environment of simulation is reconfigurable. It has a stand-alone mode with an external environment simulatied in C++. It also can simulate in Verilog mode, the C++ external environment is disabled and simulated with Verilog.
本文研究了软件仿真器的设计方法和软硬件协同仿真的实现方法,针对自主研发的嵌入式处理器CK510,用C/C++开发了一套可配置的时钟精确的软件仿真平台,这个平台里包括时钟精确的软件仿真器,AMBA AHB总线功能模型,以及实现协同仿真的PLI接口。仿真器采用的是基于解释的仿真策略,执行驱动的实现方式,完整的建模了CPU的流水线结构、中断处理器机制。
本文所设计的软件仿真平台最大的特点在于有很强的可配置性,不仅软件仿真器的模型可以配置,而且仿真的环境也可以根据需要配置。仿真平台可以运行在C++的模型下,根据仿真的目的选择是否需要总线功能模型;也可以运行在Verilog的环境下,通过PLI接口实现协同仿真。灵活的仿真环境可满足不同用户的需求。
In the last decades, instruction set simulator has became an essential development tool for the design of embedded processor. It is a simulation platform that builds on the existing computer system for an under developing processor. Designers can execute programs on these models to validate the performance and correctness of a proposed hardware design. Programmers can use this software models to develop and test software before the real hardware becomes available.This thesis studied the design methods of instruction set simulator, and the implementation of hardware-software co-simulation. We develop a software simulation platform with C/C++. This platform contains a reconfigurable cycle accurate instruction set simulator, whose target processor is CK510, an embedded processor developed by Zhejiang University. It also contains a bus function model of AMBA AHB, and a Procedure Language Interface (PLI) developed with VPI library. Our instruction set simulator is an interpretive simulator, which implements with execution driven approach. In order to get accurate simulation result, it models the pipeline architecture and exception handle of CK510 completely.The cycle-accurate simulation flat is reconfigurable. Foremost, the instrunction set simulator is reconfigurable, users can modify the cache size, associative way number, the size of branch history table, the big endian or little endian. Secondly, the environment of simulation is reconfigurable. It has a stand-alone mode with an external environment simulatied in C++. It also can simulate in Verilog mode, the C++ external environment is disabled and simulated with Verilog.
引文
[1] J. Hennessy and D. Patterson. Computer Organization and Design: The Hardware——Software Interface(AppendixA, by James R. Lanls)[M]. San mateo, CA: Morgan Kaufman, 1993
[2] A. Nohl, G. Braun, O. Schliebusch, R. Leupers, H Meyr. A Universal Technique for Fast and Flexible Instruction Set Architecture Simulation. DAC. 2002.
[3] M. Reshadi, P. Mishra, N. Dutt. Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation. DAC. 2003.
[4] C. Mills, S. Ahalt, and J. Fowler. Compiled instruction set simulation. Software-Practice and Experience, 21 (8): 877-889, 1991.
[5] L. Guerra, J. Fitzner, D. Talukdar, C.Schlager, B.Tabbara, V. Zivojnovic, Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification, DAC 1999, pp. 964-969
[6] R Leupers, J Elste, B Landwehr. Generation of interpretive and compiled instruction set simulators[C]. In: Proceedings of the Asia and South Pacific Design Automation Conference(ASP—DAC), 1999
[7] J. Hennessy and D. Patterson. Computer Architecture: A Quantitative Approach, 3rd. edition. Morgan Kaufmann Publishers, Inc., San Francisco, May 2002.
[8] R. Voith, "The PowerPC 603 C++ Verilog Interface Model," Digest of papers-Spring CompCon 94. IEEE Computer Society Press, March 1994, pp. 337-340.
[9] G. Maturana, J. L. Ball, J. Gee, A. Iyer, and J. O'Connor, Incas: A Cycle Accurate Model of UltraSPARC. VLSI in computers & Processor (ICCD '95) 1995 IEEE, pp. 130-135
[10] ARM7TDMI DesignStart Kit User Guide, http://www.arm.com
[11] Design Simulation Model User Guide, http://www.arm.com
[12] T. Austin, E. Larson, D. Ernst, SimpleScalar: an infrastructure for computer system modeling, Computer, Volume 35, Issue 2, Feb. 2002 Page:59-67
[13] E. Keet, A personal recollection of sofgware's early days(1960-1979): part 1, Annals of the History of Computing, IEEE, Volume 17, Issue 4, Winter 1995 Page:24-45
[14] M. Reshadi, N. Bansal, P. Mishra, N. Dutt, An Efficient Retargetable Framework for Instruction-Set Simulation, Hardware/Software Codesign and System Synthesis, 2003 pp. 13-18
[15] R. F. Cmelik et al. Shade: A fast instruction set simulator for execution profiling. ACM SIGMETTRICS Conference on Measurment and Modeling of computer systems, Philadelphia, 1996.
[16] Pekka Jaaskelainen, Instrction Set Simulator for Transport Triggered Architectures. Master of Science Thesis: 59 pages, 2 appendix pages, September 2005
[17] R. Domer, A. Gerstlauer, D. Shin, Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components, Technical Report CECS-04-19, CECS, UC Irvine, July 22 2004.
[18] D. Shin, A. Gerstlauer, R. Doemer, D. Gajski. C-based Interactive RTL Design Methodology. Center for Embedded Computer Systems, Technical Report 03-42, Dec. 2003.
[19] S. Pees et al. LISA-machine description language for cycleaccurate models of programmable DSP architectures. DAC, 1999.
[20] IEEE. Hardware Description Language Based on the Verilog Hardware Description Language. IEEE Std. 1364-1995, IEEE, 1995.
[21] D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface. San Francisco, US: Morgan Kaufmann, 1998.
[22] "GCC, the GNU Compiler Collection," Website, 2005, http://gcc.gnu.org.
[23] Synopsys Online Documentation, Synopsys, 2002.
[24] V. Zivojnovic, S. Tjiang, H. Meyr: Compiled Simulation of Programmable DSP Architectures, IEEE Workshop on VLSI Signal Processing, 1995
[25] E. Witchel and M. Rosenblum. Embra: Fast and Flexible Machine Simulation. In Proc. of the Conf. on Measurement and Modeling of Computer Systems, 1996.
[26] Rowson, J. "Hardware/software co-simulation", in Proceedings of the Desing Automation Conference (1994), pp.439-440
[27] A. Silburt et. al. Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation. In Proc. ofthe Design Auromution Conference (DAC), Jun. 1995.
[28] J. Daveau, G. Marchioro, T. Ben-Ismail, and A. Jerraya. H[ird+vure/Sqfhvcire Co-Design and Co-Verificufion, volume 8, chapter COSMOS: An SDL Based Hardwadsoftware Codesign Environment,. Kluwer Academic Publishers, 1997. pages 59-87
[39] M. Reshadi, N. Dutt, Genetic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation, Design, Automation and Test in Europe Conference and Exhibition (DATE'05), IEEE Computer Society, 2005, pp.786-791
[30] B. Cmelik, D. Keppel, Shade: A Fast Instruction-Set Simulator for Execution Profiling. A CMSIGMETRIC S Performance Evaluation Review, Volume 22(1), Pages 128-137, May
[31] Felix Sheng-Ho Chang and Alan J. Hu, Fast Specification of Cycle-Accurate Processor Models. VLSI in computers & Processor (ICCD '01) 2001 IEEE
[32] M.. Marinescu, M. Rinard. High-level specification and efficient implementation of pipelined circuits. In Asia and South Pacific Design Automation Conference, 2001.
[33] T. Jeremiassen. Sleipnir, an instruction-level simulator generator. In International Conference on Computer Design, IEEE, 2000. pages 23-31.
[34] S. Pees et al. Retargeting of Compiled Simulators for Digital Signal Processors using a Machine Description Language. DATE, 2000.
[35] G. Braun et al. Using Static Scheduling Techniques for the Retargeting of High Speed, Compiled Simulators for Embedded Processors from an Abstract Machine Description. ISSS, 2001.
[36] E. Schnarr, M. Hill, and J. Larus. Facile: A language and compiler for high-performance processor simulators. In Proceedings of ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Utah,USA, Jun. 2001.
[37] 杭州中天微系统有限公司,CK510用户手册,http://www.c-sky.com
[38] 潘国振,王界兵,严晓浪,“高性能嵌入式CPU特殊指令单元的设计与实现”,浙江大学学报:工学版,2005年39卷2期,211-215
[39] 梁中书,陈必龙,严晓浪,王界兵,“CPU中可伸缩低开销的硬件调试器设计”,微电子学与计算机,2004年21卷8期,141—144
[40] 张宇弘,王界兵,严晓浪,王乐宇,“标志预访问和组选择历史相结合的低功耗指令cache”,电子学报,2004年32卷8期,1286-1289
[41] 严晓浪,余龙理,王界兵,“A fornt-end automation tool supporting design,verification and reuse ofSOC”,浙江大学学报:自然科学英文版,2004年5卷9期,1102-1105
[42] 陶峰峰,付宇卓,“DSP指令集仿真器的设计与实现”,计算机仿真,2005年22卷9 期,225-228
[43] 萧鹏,季红彬,“M~*CORE和SOC设计平台及其应用”,2002年集成电路行业协会年会,中国,成都,2002年10月
[44] 季红彬,萧鹏,“SOC设计平台和方法”,2002年嵌入式系统及其应用研讨会,中国,上海,2002年11月
[45] AMBA Specification, http://www.arm.com
[46] 刑文峰,“RISC/DSP系统仿真器的研究”,浙江大学硕士论文,2004年
[47] 彭志航,“可调试的基于指令集CPU仿真器的设计与实现”,北京航空航天大学,2001
[48] 陆岚,王克祥,“系统级结构仿真器的研究与实现”。小型微型计算机系统,2002年
[49] 王旭,“计算机指令集仿真器的时间仿真技术研究”,计算机应用与软件,2005年22卷8期,62-63
[50] 钱斌,付宇卓,“一种基于虚指令集技术构建快速的可重用的指令集仿真器的方法”,计算机工程与应用,2005年41卷12期,95-97
[51] 王颖,邵作之,王赛宇,“于快速ISS建模技术的研究”计算机与网络,2005年21期,60-61
[2] A. Nohl, G. Braun, O. Schliebusch, R. Leupers, H Meyr. A Universal Technique for Fast and Flexible Instruction Set Architecture Simulation. DAC. 2002.
[3] M. Reshadi, P. Mishra, N. Dutt. Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation. DAC. 2003.
[4] C. Mills, S. Ahalt, and J. Fowler. Compiled instruction set simulation. Software-Practice and Experience, 21 (8): 877-889, 1991.
[5] L. Guerra, J. Fitzner, D. Talukdar, C.Schlager, B.Tabbara, V. Zivojnovic, Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification, DAC 1999, pp. 964-969
[6] R Leupers, J Elste, B Landwehr. Generation of interpretive and compiled instruction set simulators[C]. In: Proceedings of the Asia and South Pacific Design Automation Conference(ASP—DAC), 1999
[7] J. Hennessy and D. Patterson. Computer Architecture: A Quantitative Approach, 3rd. edition. Morgan Kaufmann Publishers, Inc., San Francisco, May 2002.
[8] R. Voith, "The PowerPC 603 C++ Verilog Interface Model," Digest of papers-Spring CompCon 94. IEEE Computer Society Press, March 1994, pp. 337-340.
[9] G. Maturana, J. L. Ball, J. Gee, A. Iyer, and J. O'Connor, Incas: A Cycle Accurate Model of UltraSPARC. VLSI in computers & Processor (ICCD '95) 1995 IEEE, pp. 130-135
[10] ARM7TDMI DesignStart Kit User Guide, http://www.arm.com
[11] Design Simulation Model User Guide, http://www.arm.com
[12] T. Austin, E. Larson, D. Ernst, SimpleScalar: an infrastructure for computer system modeling, Computer, Volume 35, Issue 2, Feb. 2002 Page:59-67
[13] E. Keet, A personal recollection of sofgware's early days(1960-1979): part 1, Annals of the History of Computing, IEEE, Volume 17, Issue 4, Winter 1995 Page:24-45
[14] M. Reshadi, N. Bansal, P. Mishra, N. Dutt, An Efficient Retargetable Framework for Instruction-Set Simulation, Hardware/Software Codesign and System Synthesis, 2003 pp. 13-18
[15] R. F. Cmelik et al. Shade: A fast instruction set simulator for execution profiling. ACM SIGMETTRICS Conference on Measurment and Modeling of computer systems, Philadelphia, 1996.
[16] Pekka Jaaskelainen, Instrction Set Simulator for Transport Triggered Architectures. Master of Science Thesis: 59 pages, 2 appendix pages, September 2005
[17] R. Domer, A. Gerstlauer, D. Shin, Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components, Technical Report CECS-04-19, CECS, UC Irvine, July 22 2004.
[18] D. Shin, A. Gerstlauer, R. Doemer, D. Gajski. C-based Interactive RTL Design Methodology. Center for Embedded Computer Systems, Technical Report 03-42, Dec. 2003.
[19] S. Pees et al. LISA-machine description language for cycleaccurate models of programmable DSP architectures. DAC, 1999.
[20] IEEE. Hardware Description Language Based on the Verilog Hardware Description Language. IEEE Std. 1364-1995, IEEE, 1995.
[21] D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface. San Francisco, US: Morgan Kaufmann, 1998.
[22] "GCC, the GNU Compiler Collection," Website, 2005, http://gcc.gnu.org.
[23] Synopsys Online Documentation, Synopsys, 2002.
[24] V. Zivojnovic, S. Tjiang, H. Meyr: Compiled Simulation of Programmable DSP Architectures, IEEE Workshop on VLSI Signal Processing, 1995
[25] E. Witchel and M. Rosenblum. Embra: Fast and Flexible Machine Simulation. In Proc. of the Conf. on Measurement and Modeling of Computer Systems, 1996.
[26] Rowson, J. "Hardware/software co-simulation", in Proceedings of the Desing Automation Conference (1994), pp.439-440
[27] A. Silburt et. al. Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation. In Proc. ofthe Design Auromution Conference (DAC), Jun. 1995.
[28] J. Daveau, G. Marchioro, T. Ben-Ismail, and A. Jerraya. H[ird+vure/Sqfhvcire Co-Design and Co-Verificufion, volume 8, chapter COSMOS: An SDL Based Hardwadsoftware Codesign Environment,. Kluwer Academic Publishers, 1997. pages 59-87
[39] M. Reshadi, N. Dutt, Genetic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation, Design, Automation and Test in Europe Conference and Exhibition (DATE'05), IEEE Computer Society, 2005, pp.786-791
[30] B. Cmelik, D. Keppel, Shade: A Fast Instruction-Set Simulator for Execution Profiling. A CMSIGMETRIC S Performance Evaluation Review, Volume 22(1), Pages 128-137, May
[31] Felix Sheng-Ho Chang and Alan J. Hu, Fast Specification of Cycle-Accurate Processor Models. VLSI in computers & Processor (ICCD '01) 2001 IEEE
[32] M.. Marinescu, M. Rinard. High-level specification and efficient implementation of pipelined circuits. In Asia and South Pacific Design Automation Conference, 2001.
[33] T. Jeremiassen. Sleipnir, an instruction-level simulator generator. In International Conference on Computer Design, IEEE, 2000. pages 23-31.
[34] S. Pees et al. Retargeting of Compiled Simulators for Digital Signal Processors using a Machine Description Language. DATE, 2000.
[35] G. Braun et al. Using Static Scheduling Techniques for the Retargeting of High Speed, Compiled Simulators for Embedded Processors from an Abstract Machine Description. ISSS, 2001.
[36] E. Schnarr, M. Hill, and J. Larus. Facile: A language and compiler for high-performance processor simulators. In Proceedings of ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Utah,USA, Jun. 2001.
[37] 杭州中天微系统有限公司,CK510用户手册,http://www.c-sky.com
[38] 潘国振,王界兵,严晓浪,“高性能嵌入式CPU特殊指令单元的设计与实现”,浙江大学学报:工学版,2005年39卷2期,211-215
[39] 梁中书,陈必龙,严晓浪,王界兵,“CPU中可伸缩低开销的硬件调试器设计”,微电子学与计算机,2004年21卷8期,141—144
[40] 张宇弘,王界兵,严晓浪,王乐宇,“标志预访问和组选择历史相结合的低功耗指令cache”,电子学报,2004年32卷8期,1286-1289
[41] 严晓浪,余龙理,王界兵,“A fornt-end automation tool supporting design,verification and reuse ofSOC”,浙江大学学报:自然科学英文版,2004年5卷9期,1102-1105
[42] 陶峰峰,付宇卓,“DSP指令集仿真器的设计与实现”,计算机仿真,2005年22卷9 期,225-228
[43] 萧鹏,季红彬,“M~*CORE和SOC设计平台及其应用”,2002年集成电路行业协会年会,中国,成都,2002年10月
[44] 季红彬,萧鹏,“SOC设计平台和方法”,2002年嵌入式系统及其应用研讨会,中国,上海,2002年11月
[45] AMBA Specification, http://www.arm.com
[46] 刑文峰,“RISC/DSP系统仿真器的研究”,浙江大学硕士论文,2004年
[47] 彭志航,“可调试的基于指令集CPU仿真器的设计与实现”,北京航空航天大学,2001
[48] 陆岚,王克祥,“系统级结构仿真器的研究与实现”。小型微型计算机系统,2002年
[49] 王旭,“计算机指令集仿真器的时间仿真技术研究”,计算机应用与软件,2005年22卷8期,62-63
[50] 钱斌,付宇卓,“一种基于虚指令集技术构建快速的可重用的指令集仿真器的方法”,计算机工程与应用,2005年41卷12期,95-97
[51] 王颖,邵作之,王赛宇,“于快速ISS建模技术的研究”计算机与网络,2005年21期,60-61