面向媒体应用的多核SoC平台的设计与实现
|
摘要
近年来媒体处理尤其是H.264/AVC、Ogg/Vorbis等音视频压缩技术的集成电路产品成为消费类电子的主要部分,为了提高设计效率,降低芯片成本,SoC设计方法学已逐步取代了传统的定制设计、ASIC设计等流程,成为消费类媒体处理电子产品的主流芯片设计方案。但随着设计复杂度要求的进一步提高,单核作为控制和计算的核心已不能完成如H.264/AVC等编解码标准的计算,对于特定任务添加硬件加速指令集的计算核心或加速器的多核SoC体系结构,在嵌入式领域满足了这样的高性能计算要求,MPSoC(Multi Processor SoC),尤其是异构MPSoC体系结构,与其相应应用目标有较强的耦合性,可从核心指令集、IP、总线、多核通信协议及软件等方面进行定制和优化。
本文基于中天微系统有限公司与浙江大学合作开发的CK510高性能嵌入式CPU、Spock媒体处理DSP核,设计硬件计算加速单元、通信辅助单元等以配合工作,搭建合理的SoC架构以满足媒体应用的需求。媒体用例则选用典型音视频编解码标准为媒体应用的主要研究对象,其中视频编解码标准H.264/AVC在编码效率、容错性和网络适应性方面较之H.263、MPEG4等具有显著优势,代表着当前最先进的视频压缩技术;音频编解码标准Ogg/Vorbis作为开源音频标准,在相同码率下较MP3标准有更高的压缩效率。
针对Ogg/Vorbis编解码设计并实现了Gemini片上双核系统,不仅可在FPGA50M的情况下进行实时Ogg/Vorbis解码及播放,更可继续扩展加速器以完成视频任务。双核片上系统具有丰富的多核通信机制支持,也通过定制软硬件以提高系统核心的计算并行性,简化其在通信中的延迟。为多核H.264/AVC解码片上系统做了充分的研究和铺垫。
In the last decade, VLSI production for media field, especially video/audiao codec such as H.264/AVC, Ogg/Vorbis, has been the main module of consuming electronics. The SoC design methodology began to be instead of typical ASIC design flow, for the efficiency improvement, VLSI cost decreasing, to be the one of most significant design flow. However even the SoC cannot solve the high performance codec standard's extremely complex computing problem, more core or accelerator need to be assemblied in the platform, which is called multi-Processor SoC Architecture. For the reason of application's especial computing task, heterogenous multi-core with the customed instruction set, IP core, bus, multicore communication mechanism has the optimized performance of application and general tasks.
This thesis studied the typical highend audio/video codec standards as the main VLSI application, H.264/AVC as the leader of video codec techonology nowadays, has the more efficient compression, robust ability and network availability than H.263; Ogg/Vorbis as the open source audio codec, has the more efficient compression than MP3. We design and implement a reasonable SoC based on the Csky Co.&ZJU self-IP CK510 CPU core, Spock DSP and related computing, interface IP, VLSI accelerator, communication assistant module, which is named Gemini heterogenous DualCore SoC platform for Ogg/Vorbis codec. With the emulation and test under the result chip, we complete the fluent audio decoder and play task in 50M frequency system.
The platform also has fine expansibility and scalability, so we can repot it into video design. Dual core system has affluent multicore communication mechanism support, we can improve the parallelism and decreasing its commucation latency based on the experiment, so that we prepare for the H.264 MPSoC implemention.
本文基于中天微系统有限公司与浙江大学合作开发的CK510高性能嵌入式CPU、Spock媒体处理DSP核,设计硬件计算加速单元、通信辅助单元等以配合工作,搭建合理的SoC架构以满足媒体应用的需求。媒体用例则选用典型音视频编解码标准为媒体应用的主要研究对象,其中视频编解码标准H.264/AVC在编码效率、容错性和网络适应性方面较之H.263、MPEG4等具有显著优势,代表着当前最先进的视频压缩技术;音频编解码标准Ogg/Vorbis作为开源音频标准,在相同码率下较MP3标准有更高的压缩效率。
针对Ogg/Vorbis编解码设计并实现了Gemini片上双核系统,不仅可在FPGA50M的情况下进行实时Ogg/Vorbis解码及播放,更可继续扩展加速器以完成视频任务。双核片上系统具有丰富的多核通信机制支持,也通过定制软硬件以提高系统核心的计算并行性,简化其在通信中的延迟。为多核H.264/AVC解码片上系统做了充分的研究和铺垫。
In the last decade, VLSI production for media field, especially video/audiao codec such as H.264/AVC, Ogg/Vorbis, has been the main module of consuming electronics. The SoC design methodology began to be instead of typical ASIC design flow, for the efficiency improvement, VLSI cost decreasing, to be the one of most significant design flow. However even the SoC cannot solve the high performance codec standard's extremely complex computing problem, more core or accelerator need to be assemblied in the platform, which is called multi-Processor SoC Architecture. For the reason of application's especial computing task, heterogenous multi-core with the customed instruction set, IP core, bus, multicore communication mechanism has the optimized performance of application and general tasks.
This thesis studied the typical highend audio/video codec standards as the main VLSI application, H.264/AVC as the leader of video codec techonology nowadays, has the more efficient compression, robust ability and network availability than H.263; Ogg/Vorbis as the open source audio codec, has the more efficient compression than MP3. We design and implement a reasonable SoC based on the Csky Co.&ZJU self-IP CK510 CPU core, Spock DSP and related computing, interface IP, VLSI accelerator, communication assistant module, which is named Gemini heterogenous DualCore SoC platform for Ogg/Vorbis codec. With the emulation and test under the result chip, we complete the fluent audio decoder and play task in 50M frequency system.
The platform also has fine expansibility and scalability, so we can repot it into video design. Dual core system has affluent multicore communication mechanism support, we can improve the parallelism and decreasing its commucation latency based on the experiment, so that we prepare for the H.264 MPSoC implemention.
引文
[1]"http://public.itrs.net/Files/1999 SIA Roadmap/Design.pdf," International Technology Roadmap for Semicnductors(ITRS),1999.
[2]B.Pierre K.Michael,"Reuse methodology manual for system-on-a-chip design," Kluwer academic publishers,2000.
[3]J.Bergeron,"Writing Testbenches:Functional Verification of Hdl Models," Springer Publisher:,2003.
[4]F.Kordon,"An Introduction to Rapid System Prototyping," IEEE Transactions on Software Engineering vol.28,pp.817-821 2002.
[5]J.K.Adams D.E.Thomas,H.Schmit,"A model and methodology for hardware-software codesign,"IEEE Transactions Design and Test of Computers,vol.10,pp.6-15,1993.
[6]A.Gupta P.Garg,J.W.Rozenblit,"Performance analysis of embedded systems in the virtual component co-design environment," Proceedings of 11th IEEE International Conference and Workshop on the Engineering of Computer-Based Systems,pp.61- 68,2004.
[7]B.Denis K.Tim,"SystemC Based Design of an IP Forwarding Chip with CoCentric System Studio," SNUG Europe 2002 2002.
[8]F.Fiedler A.Hoffinann,A.Nohl and et al,"A methodology and tooling enabling application specific processor design," Proceeding of 18th International Conference on VLSI Design,2005,pp.399-404,2005.
[9]W.Paul S.Wilson,GDuane,"Verilator Verilog HDL simulator,"http://www.veripool.com/verilator.html.
[10]MARK DEVOSS。NAND增长重塑NOR市场[J]。市场分析与趋势,2005,2:5-6.
[11]肖建。一种在片上系统中实现Nand Flash控制器的方法[J]。南京邮电学院学报,2005,25(2):81-85。
[12]SUMSUNG。K9F1208U0M Datasheet[EB/OL]。(2001-04)[2006-03-03]。http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html。
[13]沈浩,付宇卓。NAND Flash存储控制器的软硬件划分设计[J].计算机工程,2004,30(24):169-185
[14]SUMSUNG。APPLICATION NOTE for NAND Flash Memory Revision2.0[EB/OL]。(1999-12-19)[2006-03-05]。http://www.samsung.com/Products/Semiconductor/Memory/appnote/app_nand.pdf.
[15]Micron.ECC Module for NAND Flash via Xilinx Spartan-3 FPGA[EB/OL]。(2005-06-24)[2006-03-02]。http://download.micron.com/pdf/technotes/nand/tn2905.pdf
[16]TOSHIBA。NAND Flash Applications Design Guide[EB/OL]。(2003-04-19)[2006-3-06]。http://www.dataio.com/pdf/NAND/Toshiba/NandDesignGuide.pdf
[17]Michael Keating,Pierre Bricaud.REUSE METHODOLOGY MANNUAL[M]。北京:电子工业出版社。2004:52-58。
[18]"ARM AMBA 3 AXI Specification,"http://www.arm.com/products/solutions/axi spec.html.
[19]N.Manjikian J.Reed,"A dual round-robin arbiter for split-transaction buses in system-on-chip implementations,"Proceeding of 2004 Canadian Conference on Electrical and Computer Engineering,vol.2,pp.835-840,2004.
[20]K.S.Jhang S.Y.Hwang,"An improved implementalion method of AHB BusMatrix,"Proceedings of2005 IEEE Intemational SOC Conference,pp.211-214,2005.
[21]J.M.Lu,"High Performance and Low-Power Dual-Core SoC Platform for Portable Multimedia Applications,"SoC Technology Jurnal,vol.2,pp.36-40,2005.
[22] D.R.Gonzales, "Micro-RISC Architecture for the Wireless Market," IEEE Micro, vol. 1999, pp. 30-37, 1999.
[23] B.M.Kulaczewski D.Andreas, L.Friebe and et al, "A multi-core SoC design for advanced image and video compression," Proceeding of of 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing(ICASSP'05), 2005.
[24] K.A.Jeong H.Y.Kang, J.Y.Ba and et al, "MPEG4 AVC/H.264 Decoder with Scalable Bus Architecture and Dual Memory Controller," Proceeding of 2004 IEEE International Symposium on Circuits and Systems(ISCAS'04), 2004.
[25] W.Zhan R.Wang, Gs.Jiang and et al, "Reuse issues in SoC verification platform," Proceedings of The 8th International Conference on Computer Supported Cooperative Work in Design, 2004, vol. 2, pp. 685- 688 2004.
[26] S.Yamaguchi A.Kosaka, H.Okuhata and et al, "VLSI implementation of Ogg Vorbis decoder for embedded applications," Proceedings of 15th Annual IEEE International: ASIC/SOC Conference, pp. 20- 24, 2002.
[27] H.Okuhata A.Kosaka, T.Onoye and et al, "Design of Ogg Vorbis Decoder System for Embedded Platform " the 19th VLSI Design Technology and CAD Symposium on Signal Processing, pp. 2124-2130,2005.
[28] K.Brandenburg T.Sporer, B.Edler, "The use of multirate filter banks for coding of high quality digital audio," Proceedings of 6th European Signal Processing Conference (EUSIPCO), p. 211～ 214,1992.
[29] W.C.Lee C.M.Liu, "The design of a hybrid filter bank for the psychoacoustic model inISO/MPEG phases 1, 2 audio encoder," IEEE Transactions on Consumer Electronics, vol. 43, pp. 586-592, 1997.
[30] xiph.org, "tremor vorbis decoder," http://www.xiph.org/vorbis/, 2002.
[31] GFettweis V.Nikolajevic, "New recursive algorithms for the forward and inverse MDCT," Proceedings of 2001 IEEE Workshop on Signal Process Systems, pp. 51-57, 2001.
[32] T.L.Yu H.Chen, "Comparison of Psychoacoustic Principles and Genetic Algorithms in Audio Compression," Proceedings of ICSENG, pp. 16-18,2005.
[33] Thomas Wiegand, Gary J. Sullivan, Gisle Bjontegaard, and Ajay Luthra Overview of the H.264/AVC Video Coding Standard [J] IEEE Trans Circuits Syst.Video Technol, vol 13,pp.560- 576, July. 2003
[34] Iain E.GRichardson H.264 and MPEG-4 Video Compression—Video Coding for Next-generation Multimedia[M] John Wiley & Sons Ltd, England December 2003
[35] S.Zhu, K.-K.Ma. A new diamond search algorithm for fast block-matching motion estimation [J]. IEEE Trans Image Processing. Feb.2000, vol.9, 287-290.
[36] CZhu.X.Lin, L.-P. Chau, Hexagon-based search pattern for fast block motion estimation [J]. IEEE Trans Circuits Syst.Video Technol. May 2002, vol.12, 349-355.
[37] A.Tourapis, O.C.Au, M.L.Liou, Highly efficient predictive zonal algorithm for fast block-matching motion estimation [J]. IEEE Trans. Circuits Syst. Video Technol, Oct.2002, vol.12. 934-947.
[38] YK.Tu, J.F.Yang, Y.N.Shen, M.T.Sun, Fast variable-size block motion estimation using merging procedure with an adaptive threshold [C]. 2003 IEEE International Conference on Multimedia and Expo, vol. 2, 789-792, Jul. 2003.
[39] Zhi Zhou, Ming-Ting Sun, Yuh-Feng Hsu Fast variable bock-size motion estimation algorithms based on merge and split procedures for H.264/MPEG-4 AVC [C] 2004 IEEE International Symposium on Circuits and Systems ISCAS 2004.725-728, May 2004
[40] Ye Wen Huang, Tu Chih Wang, Bing Yu Hsieh, Liang Gee Chen. Hardware architecture design for variable block size motion estimation in MPEG-4/AVC/JVT/ITU-T H.264 [C] Proceedings of the 2003 International Symposium on Circuits and Systems,2003. ISCAS '03., Volume: 2 , 25-28 May 2003
[41] Shih-Chang Hsia VLSI implementation for low-complexity full-search motion estimation [J] IEEE Transactions on Circuits and Systems for Video Technology vol. 12, Issue: 7, July 2002
[42] Detlev Marpe, Heiko Schwarz,Thomas Wiegand. Context-based adaptive binary arithmetic codingin the H.264/AVC video compression standard [J]. IEEE Trans. Circuits Syst Video Technol, July 2003, vol.13, 620, No.7.
[2]B.Pierre K.Michael,"Reuse methodology manual for system-on-a-chip design," Kluwer academic publishers,2000.
[3]J.Bergeron,"Writing Testbenches:Functional Verification of Hdl Models," Springer Publisher:,2003.
[4]F.Kordon,"An Introduction to Rapid System Prototyping," IEEE Transactions on Software Engineering vol.28,pp.817-821 2002.
[5]J.K.Adams D.E.Thomas,H.Schmit,"A model and methodology for hardware-software codesign,"IEEE Transactions Design and Test of Computers,vol.10,pp.6-15,1993.
[6]A.Gupta P.Garg,J.W.Rozenblit,"Performance analysis of embedded systems in the virtual component co-design environment," Proceedings of 11th IEEE International Conference and Workshop on the Engineering of Computer-Based Systems,pp.61- 68,2004.
[7]B.Denis K.Tim,"SystemC Based Design of an IP Forwarding Chip with CoCentric System Studio," SNUG Europe 2002 2002.
[8]F.Fiedler A.Hoffinann,A.Nohl and et al,"A methodology and tooling enabling application specific processor design," Proceeding of 18th International Conference on VLSI Design,2005,pp.399-404,2005.
[9]W.Paul S.Wilson,GDuane,"Verilator Verilog HDL simulator,"http://www.veripool.com/verilator.html.
[10]MARK DEVOSS。NAND增长重塑NOR市场[J]。市场分析与趋势,2005,2:5-6.
[11]肖建。一种在片上系统中实现Nand Flash控制器的方法[J]。南京邮电学院学报,2005,25(2):81-85。
[12]SUMSUNG。K9F1208U0M Datasheet[EB/OL]。(2001-04)[2006-03-03]。http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html。
[13]沈浩,付宇卓。NAND Flash存储控制器的软硬件划分设计[J].计算机工程,2004,30(24):169-185
[14]SUMSUNG。APPLICATION NOTE for NAND Flash Memory Revision2.0[EB/OL]。(1999-12-19)[2006-03-05]。http://www.samsung.com/Products/Semiconductor/Memory/appnote/app_nand.pdf.
[15]Micron.ECC Module for NAND Flash via Xilinx Spartan-3 FPGA[EB/OL]。(2005-06-24)[2006-03-02]。http://download.micron.com/pdf/technotes/nand/tn2905.pdf
[16]TOSHIBA。NAND Flash Applications Design Guide[EB/OL]。(2003-04-19)[2006-3-06]。http://www.dataio.com/pdf/NAND/Toshiba/NandDesignGuide.pdf
[17]Michael Keating,Pierre Bricaud.REUSE METHODOLOGY MANNUAL[M]。北京:电子工业出版社。2004:52-58。
[18]"ARM AMBA 3 AXI Specification,"http://www.arm.com/products/solutions/axi spec.html.
[19]N.Manjikian J.Reed,"A dual round-robin arbiter for split-transaction buses in system-on-chip implementations,"Proceeding of 2004 Canadian Conference on Electrical and Computer Engineering,vol.2,pp.835-840,2004.
[20]K.S.Jhang S.Y.Hwang,"An improved implementalion method of AHB BusMatrix,"Proceedings of2005 IEEE Intemational SOC Conference,pp.211-214,2005.
[21]J.M.Lu,"High Performance and Low-Power Dual-Core SoC Platform for Portable Multimedia Applications,"SoC Technology Jurnal,vol.2,pp.36-40,2005.
[22] D.R.Gonzales, "Micro-RISC Architecture for the Wireless Market," IEEE Micro, vol. 1999, pp. 30-37, 1999.
[23] B.M.Kulaczewski D.Andreas, L.Friebe and et al, "A multi-core SoC design for advanced image and video compression," Proceeding of of 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing(ICASSP'05), 2005.
[24] K.A.Jeong H.Y.Kang, J.Y.Ba and et al, "MPEG4 AVC/H.264 Decoder with Scalable Bus Architecture and Dual Memory Controller," Proceeding of 2004 IEEE International Symposium on Circuits and Systems(ISCAS'04), 2004.
[25] W.Zhan R.Wang, Gs.Jiang and et al, "Reuse issues in SoC verification platform," Proceedings of The 8th International Conference on Computer Supported Cooperative Work in Design, 2004, vol. 2, pp. 685- 688 2004.
[26] S.Yamaguchi A.Kosaka, H.Okuhata and et al, "VLSI implementation of Ogg Vorbis decoder for embedded applications," Proceedings of 15th Annual IEEE International: ASIC/SOC Conference, pp. 20- 24, 2002.
[27] H.Okuhata A.Kosaka, T.Onoye and et al, "Design of Ogg Vorbis Decoder System for Embedded Platform " the 19th VLSI Design Technology and CAD Symposium on Signal Processing, pp. 2124-2130,2005.
[28] K.Brandenburg T.Sporer, B.Edler, "The use of multirate filter banks for coding of high quality digital audio," Proceedings of 6th European Signal Processing Conference (EUSIPCO), p. 211～ 214,1992.
[29] W.C.Lee C.M.Liu, "The design of a hybrid filter bank for the psychoacoustic model inISO/MPEG phases 1, 2 audio encoder," IEEE Transactions on Consumer Electronics, vol. 43, pp. 586-592, 1997.
[30] xiph.org, "tremor vorbis decoder," http://www.xiph.org/vorbis/, 2002.
[31] GFettweis V.Nikolajevic, "New recursive algorithms for the forward and inverse MDCT," Proceedings of 2001 IEEE Workshop on Signal Process Systems, pp. 51-57, 2001.
[32] T.L.Yu H.Chen, "Comparison of Psychoacoustic Principles and Genetic Algorithms in Audio Compression," Proceedings of ICSENG, pp. 16-18,2005.
[33] Thomas Wiegand, Gary J. Sullivan, Gisle Bjontegaard, and Ajay Luthra Overview of the H.264/AVC Video Coding Standard [J] IEEE Trans Circuits Syst.Video Technol, vol 13,pp.560- 576, July. 2003
[34] Iain E.GRichardson H.264 and MPEG-4 Video Compression—Video Coding for Next-generation Multimedia[M] John Wiley & Sons Ltd, England December 2003
[35] S.Zhu, K.-K.Ma. A new diamond search algorithm for fast block-matching motion estimation [J]. IEEE Trans Image Processing. Feb.2000, vol.9, 287-290.
[36] CZhu.X.Lin, L.-P. Chau, Hexagon-based search pattern for fast block motion estimation [J]. IEEE Trans Circuits Syst.Video Technol. May 2002, vol.12, 349-355.
[37] A.Tourapis, O.C.Au, M.L.Liou, Highly efficient predictive zonal algorithm for fast block-matching motion estimation [J]. IEEE Trans. Circuits Syst. Video Technol, Oct.2002, vol.12. 934-947.
[38] YK.Tu, J.F.Yang, Y.N.Shen, M.T.Sun, Fast variable-size block motion estimation using merging procedure with an adaptive threshold [C]. 2003 IEEE International Conference on Multimedia and Expo, vol. 2, 789-792, Jul. 2003.
[39] Zhi Zhou, Ming-Ting Sun, Yuh-Feng Hsu Fast variable bock-size motion estimation algorithms based on merge and split procedures for H.264/MPEG-4 AVC [C] 2004 IEEE International Symposium on Circuits and Systems ISCAS 2004.725-728, May 2004
[40] Ye Wen Huang, Tu Chih Wang, Bing Yu Hsieh, Liang Gee Chen. Hardware architecture design for variable block size motion estimation in MPEG-4/AVC/JVT/ITU-T H.264 [C] Proceedings of the 2003 International Symposium on Circuits and Systems,2003. ISCAS '03., Volume: 2 , 25-28 May 2003
[41] Shih-Chang Hsia VLSI implementation for low-complexity full-search motion estimation [J] IEEE Transactions on Circuits and Systems for Video Technology vol. 12, Issue: 7, July 2002
[42] Detlev Marpe, Heiko Schwarz,Thomas Wiegand. Context-based adaptive binary arithmetic codingin the H.264/AVC video compression standard [J]. IEEE Trans. Circuits Syst Video Technol, July 2003, vol.13, 620, No.7.