考虑自热效应互连性能优化及硅通孔结构热传输分析
|
摘要
随着集成电路进入纳米时代，芯片的特征尺寸不断减小而集成度持续上升，片上晶体管数目的增加大大提高了芯片的复杂度，连接芯片内部功能块的互连线结构也变的复杂，集成电路的设计重心由原来器件为主逐步向互连线上转移。集成电路的互连结构目前已经达到13层，加上低k低热导率介质材料的引入，导致互连线的热耗散路径变长、难度增大。互连线自身产生的焦耳热无疑升高了互连温度，而受温度影响的互连电阻的改变使得现有的互连线性能估算方法不再准确，这势必阻碍集成电路的发展。本文从自热效应的影响、互连线性能优化以及3D IC热管理角度开展研究，并取得了以下成果：
(1)针对单根互连线，本文引进了可以减小互连线延时的非均匀互连线结构，验证了其在减小功耗方面也做出了一定的贡献。基于二端口电路的电流电压理论，推导出非均匀互连线输入、输出电流和电压，建立了包含前端驱动和后端负载在内的非均匀互连电路各部分能耗分布。在65nm工艺下，非均匀互连线的输出电压仿真结果同Hspice仿真结果比较非常吻合。针对互连线不同长度和不同负载电容值进行讨论，结果表明非均匀互连线的能耗分布模型比较适合长互连线和负载电容较大的互连电路。与均匀互连线相比较，非均匀互连线在功耗优化方面也起到了积极的作用。
(2)基于分布式功耗模型，考虑自热效应，采用非均匀互连线结构建立了一种基于延时、带宽、面积、最小线宽和最小线间距约束的互连线动态优化模型。分别在90nm和65nm CMOS工艺节点下验证本文功耗优化模型的有效性,与同等条件的均匀互连线相比，在工艺约束下同时不牺牲延时、带宽、和面积所提模型能够降低高达35%的互连线功耗；分析结果表明该模型更适合负载电容小和驱动电阻大的互连电路；通过定性分析再次证明该模型互连线功耗优化的合理之处。该模型适用于片上网络构架中大型互连路由结构和时钟网络优化设计。
(3)缓冲器插入的互连线一般都是较长的全局互连线，其位于离热沉较远的互连线结构顶层，散热较差，因此互连线自热效应严重影响到了全局互连线性能和电磁可靠性。传统缓冲器插入优化方法的建立都是基于互连线恒温状态，本文针对这一不足，利用互连线单位电阻与温度的线性关系，考虑互连线自热效应修正了电阻表达式。并通过作图的方式分析出自热效应对互连线延时、带宽、功耗和面积的影响。采用互连线各性能折中优化方法，引入性能品质因子这一概念，合理的建立了考虑自热效应后的插入缓冲器优化模型。针对90nm、65nm和40nm工艺节点进行仿真，仿真结果与不考虑自热效应情况相比，互连线线宽wopt、线间距sopt、缓冲器大小kopt和插入缓冲器的间距hopt的值都明显增大，并且考虑自热效应后互连线的延时、功耗和带宽能够获得更好的优化值。结果表明在实际生产中，由于不考虑自热效应，互连线性能优化所需结构尺寸明显偏小，导致互连工艺技术要求苛刻。
(4)三维集成电路与二维集成电路相比，降低了全局互连和整个互连线长度，提高了互连延时、功耗方面的性能。特别是三维集成电路系统包含多个功能模块（数字模块、模拟模块、RF模块）和不同工艺技术(SOI, SiGe, GaAs等)，为集成电路的设计拓展了空间。在影响3D集成电路发展的诸多问题中，热管理无疑是最为重要的因素之一。基于Ankur Jain的三维集成电路一维热管理模型，本文提出了考虑横向热扩散效应的含硅通孔结构的三维热传输模型。仿真结果与ANSYS软件仿真结果比较具有很高的吻合度，针对变化的通孔密度、通孔直径、后端互连线层厚度和硅通孔填充材料，仿真比较了考虑通孔结构和不考虑通孔结构的叠层芯片各层温升，结果显示考虑通孔结构后的三维集成电路热扩散能力显著提高，证明了硅通孔结构在三维集成电路热扩散中的重要地位；对含有硅通孔结构的三维集成电路，同样比较了上述参数变化下考虑横向热扩散和不考虑横向热扩散的各层温升，结果表明，横向热扩散对于含硅通孔结构的三维集成电路热分析而言是不可忽视的。
As the feature sizes of integrate circuits decrease to nanometer，the chip featuresize continues to decrease while integration level is improved continuously. Theincrease of the number of transistors enhances the complexity of chip. Theinterconnection, which connects function modules on chip, is becoming more complexas well. The centre of the design integrated circuit (IC) has shifted from electronicdevice to the interconnection. Variation of interconnect wire resistance, which resultsfrom the influence of temperature, and the adopting of new materials with low thermalconductivity lead to the deterioration of performance and reliability of the circuit. Thethermal problems of chip always restrict the development of IC. Consequently, theresearch of interconnection performance with consideration of the self-heating effect ofinterconnect is necessary.
At present the number of metal layer has reached13in nanometer integratedcircuit, which result in a longer path between the interconnect wire and the substrateattached to heat sink for the heat dissipation of interconnection. In addition, adoption oflow dielectric constant materials in IC manufacture makes the interconnection heatmore difficult to dissipate. Interconnection Joule's heat increases the interconnectiontemperature while seriously affects the accuracy of interconnection performanceestimation. The research centered on the effect of self-heating, interconnectionperformance optimization and thermal management of3D ICs. The main studies andconclusive results are as follows:
(1) For single interconnect wire, a non-uniform interconnection structure whichcan low the interconnection delay effectively is introduced. Then the non-uniforminterconnection contribution on power reduction is proved. Based on the two-portnetwork current and voltage theory, the input and output current and voltage are derived.Last the energy consumptions distribution model of the interconnect circuit whichincludes front-end driver and back-end load. The proposed model is simulated at65nmCMOS technology. The concluded output voltage accords well with the simulationresult of HSPICE. Simulation results of the energy consumption are analyzed withdifferent interconnect wire length and different load capacitor. The energy consumptionsdistribution model is more applicable to long wire and large load capacitor forinterconnection. Compared with uniform interconnection, the adoption of non-uniforminterconnection structure works well on power optimization.
(2) Based on the distributed interconnect power model, a novel dynamic power model is presented in this paper, which adopts a non-uniform interconnection structure.This model takes into account the self-heating effect and is constrained by delay,bandwidth, area, minimum interconnect width and minimum interconnect space. Thevalidity of the proposed model is verified at90nm and65nm CMOS technology. Theresults indicated that the proposed model can generate a power consumption reductionas high as35%, and yet the delay, area, bandwidth are not deteriorated, compared withthe conventional power model. The simulation results indicates that the proposed modelis more applicable to the interconnect circuit which has low load capacitance and largedriver resistance. The proposed optimal model can be used for design of large scaleinterconnect router and clock network in network-on-chip structure.
(3) The interconnection which needed buffer insertion is a long global line. As it islocated far away from heat sink, the global interconnect has poor heat dissipationcapacity. Therefore, the self-heating effect greatly affects interconnect performance andelectromigration reliability. For traditional optimal buffer insertion, the model is basedon a constant temperature assumption. In order to resolve the shortage, the interconnectresistance per unit length is modification with the consideration of the sealf-heatingeffect since the interconnect resistance has a linear dependence on the temperature. Byusing the graphical mythologies, the relationships between sealf-heating effect and delay,bandwidth, power and area are analyzed. For the purpose of having a small delay, powerdissipation and area while having a large bandwidth, a general metric for the tradeoff onall of above performance is developed. The proposed optimal model is verified andcompared based on90nm,65nm and40nm CMOS technologies. It is found that thevalues of wopt, sopt, koptand hoptare larger than that of no considering the self-heatingeffect. More optimum results can be easily obtained by the proposed model. Thisoptimization model is more accurate and realistic than the conventional optimizationmodels, and can be integrated into the global interconnection design of nano-scaleintegrated circuits.
(4) One of the most important benefits of three-dimensional (3D) architecture overa traditional two-dimensional (2-D) design is the reduction in global interconnects andtotal wire-length, thereby providing higher timing performance and lower powerconsumption. Further, a3-D integrated system can include multiple design disciplines(Digital, analog, RF) and disparate process technologies (SOI, SiGe, GaAs, etc.), thatextend the capabilities of the3D system, expanding the boundaries of the IC designspace. Of all the development-hampering factors for3D ICs, thermal management is undoubtedly the most important factors. Based on the one-dimensional heat transfermodel proposed by Ankur Jain, a3D analytical heat transfer model for3D ICs withthrough silicon via (TSV) is developed in this paper. The simulation results areconsistent with the result based on ANSYS. The results of analysis indicate thatincreasing insertion density of TSV, and radius of TSV, decreasing the thickness of backend of line and adopting TSV insertion of higher thermal conductivity can effectivelyimprove the heat dissipation of3D ICs circuits. It is proved that the importance of TSVin thermal diffusion for3D ICs. Meanwhile, The effects of the horizontal heat transferon the thermal management of3D ICs is analyzed when the number of strata, the TSVdensity, the TSV diameter and the thickness of the BEOL layer vary under the specificprocess and thermal parameters. The results indicated that the temperature rise,simulated by the model presented in this paper, is lower compared with the conditionwithout considering the horizontal heat transfer effect. The difference of the temperaturecan be above10%. And the effect of the horizontal heat transfer on the thermalmanagement of3D ICs is more obvious with the increase of integrated level. Since themodel presented in this paper conforms to the actual situation, it can be more accurate inanalyzing the temperatures of stacked chips in3D ICs.
(1)针对单根互连线，本文引进了可以减小互连线延时的非均匀互连线结构，验证了其在减小功耗方面也做出了一定的贡献。基于二端口电路的电流电压理论，推导出非均匀互连线输入、输出电流和电压，建立了包含前端驱动和后端负载在内的非均匀互连电路各部分能耗分布。在65nm工艺下，非均匀互连线的输出电压仿真结果同Hspice仿真结果比较非常吻合。针对互连线不同长度和不同负载电容值进行讨论，结果表明非均匀互连线的能耗分布模型比较适合长互连线和负载电容较大的互连电路。与均匀互连线相比较，非均匀互连线在功耗优化方面也起到了积极的作用。
(2)基于分布式功耗模型，考虑自热效应，采用非均匀互连线结构建立了一种基于延时、带宽、面积、最小线宽和最小线间距约束的互连线动态优化模型。分别在90nm和65nm CMOS工艺节点下验证本文功耗优化模型的有效性,与同等条件的均匀互连线相比，在工艺约束下同时不牺牲延时、带宽、和面积所提模型能够降低高达35%的互连线功耗；分析结果表明该模型更适合负载电容小和驱动电阻大的互连电路；通过定性分析再次证明该模型互连线功耗优化的合理之处。该模型适用于片上网络构架中大型互连路由结构和时钟网络优化设计。
(3)缓冲器插入的互连线一般都是较长的全局互连线，其位于离热沉较远的互连线结构顶层，散热较差，因此互连线自热效应严重影响到了全局互连线性能和电磁可靠性。传统缓冲器插入优化方法的建立都是基于互连线恒温状态，本文针对这一不足，利用互连线单位电阻与温度的线性关系，考虑互连线自热效应修正了电阻表达式。并通过作图的方式分析出自热效应对互连线延时、带宽、功耗和面积的影响。采用互连线各性能折中优化方法，引入性能品质因子这一概念，合理的建立了考虑自热效应后的插入缓冲器优化模型。针对90nm、65nm和40nm工艺节点进行仿真，仿真结果与不考虑自热效应情况相比，互连线线宽wopt、线间距sopt、缓冲器大小kopt和插入缓冲器的间距hopt的值都明显增大，并且考虑自热效应后互连线的延时、功耗和带宽能够获得更好的优化值。结果表明在实际生产中，由于不考虑自热效应，互连线性能优化所需结构尺寸明显偏小，导致互连工艺技术要求苛刻。
(4)三维集成电路与二维集成电路相比，降低了全局互连和整个互连线长度，提高了互连延时、功耗方面的性能。特别是三维集成电路系统包含多个功能模块（数字模块、模拟模块、RF模块）和不同工艺技术(SOI, SiGe, GaAs等)，为集成电路的设计拓展了空间。在影响3D集成电路发展的诸多问题中，热管理无疑是最为重要的因素之一。基于Ankur Jain的三维集成电路一维热管理模型，本文提出了考虑横向热扩散效应的含硅通孔结构的三维热传输模型。仿真结果与ANSYS软件仿真结果比较具有很高的吻合度，针对变化的通孔密度、通孔直径、后端互连线层厚度和硅通孔填充材料，仿真比较了考虑通孔结构和不考虑通孔结构的叠层芯片各层温升，结果显示考虑通孔结构后的三维集成电路热扩散能力显著提高，证明了硅通孔结构在三维集成电路热扩散中的重要地位；对含有硅通孔结构的三维集成电路，同样比较了上述参数变化下考虑横向热扩散和不考虑横向热扩散的各层温升，结果表明，横向热扩散对于含硅通孔结构的三维集成电路热分析而言是不可忽视的。
As the feature sizes of integrate circuits decrease to nanometer，the chip featuresize continues to decrease while integration level is improved continuously. Theincrease of the number of transistors enhances the complexity of chip. Theinterconnection, which connects function modules on chip, is becoming more complexas well. The centre of the design integrated circuit (IC) has shifted from electronicdevice to the interconnection. Variation of interconnect wire resistance, which resultsfrom the influence of temperature, and the adopting of new materials with low thermalconductivity lead to the deterioration of performance and reliability of the circuit. Thethermal problems of chip always restrict the development of IC. Consequently, theresearch of interconnection performance with consideration of the self-heating effect ofinterconnect is necessary.
At present the number of metal layer has reached13in nanometer integratedcircuit, which result in a longer path between the interconnect wire and the substrateattached to heat sink for the heat dissipation of interconnection. In addition, adoption oflow dielectric constant materials in IC manufacture makes the interconnection heatmore difficult to dissipate. Interconnection Joule's heat increases the interconnectiontemperature while seriously affects the accuracy of interconnection performanceestimation. The research centered on the effect of self-heating, interconnectionperformance optimization and thermal management of3D ICs. The main studies andconclusive results are as follows:
(1) For single interconnect wire, a non-uniform interconnection structure whichcan low the interconnection delay effectively is introduced. Then the non-uniforminterconnection contribution on power reduction is proved. Based on the two-portnetwork current and voltage theory, the input and output current and voltage are derived.Last the energy consumptions distribution model of the interconnect circuit whichincludes front-end driver and back-end load. The proposed model is simulated at65nmCMOS technology. The concluded output voltage accords well with the simulationresult of HSPICE. Simulation results of the energy consumption are analyzed withdifferent interconnect wire length and different load capacitor. The energy consumptionsdistribution model is more applicable to long wire and large load capacitor forinterconnection. Compared with uniform interconnection, the adoption of non-uniforminterconnection structure works well on power optimization.
(2) Based on the distributed interconnect power model, a novel dynamic power model is presented in this paper, which adopts a non-uniform interconnection structure.This model takes into account the self-heating effect and is constrained by delay,bandwidth, area, minimum interconnect width and minimum interconnect space. Thevalidity of the proposed model is verified at90nm and65nm CMOS technology. Theresults indicated that the proposed model can generate a power consumption reductionas high as35%, and yet the delay, area, bandwidth are not deteriorated, compared withthe conventional power model. The simulation results indicates that the proposed modelis more applicable to the interconnect circuit which has low load capacitance and largedriver resistance. The proposed optimal model can be used for design of large scaleinterconnect router and clock network in network-on-chip structure.
(3) The interconnection which needed buffer insertion is a long global line. As it islocated far away from heat sink, the global interconnect has poor heat dissipationcapacity. Therefore, the self-heating effect greatly affects interconnect performance andelectromigration reliability. For traditional optimal buffer insertion, the model is basedon a constant temperature assumption. In order to resolve the shortage, the interconnectresistance per unit length is modification with the consideration of the sealf-heatingeffect since the interconnect resistance has a linear dependence on the temperature. Byusing the graphical mythologies, the relationships between sealf-heating effect and delay,bandwidth, power and area are analyzed. For the purpose of having a small delay, powerdissipation and area while having a large bandwidth, a general metric for the tradeoff onall of above performance is developed. The proposed optimal model is verified andcompared based on90nm,65nm and40nm CMOS technologies. It is found that thevalues of wopt, sopt, koptand hoptare larger than that of no considering the self-heatingeffect. More optimum results can be easily obtained by the proposed model. Thisoptimization model is more accurate and realistic than the conventional optimizationmodels, and can be integrated into the global interconnection design of nano-scaleintegrated circuits.
(4) One of the most important benefits of three-dimensional (3D) architecture overa traditional two-dimensional (2-D) design is the reduction in global interconnects andtotal wire-length, thereby providing higher timing performance and lower powerconsumption. Further, a3-D integrated system can include multiple design disciplines(Digital, analog, RF) and disparate process technologies (SOI, SiGe, GaAs, etc.), thatextend the capabilities of the3D system, expanding the boundaries of the IC designspace. Of all the development-hampering factors for3D ICs, thermal management is undoubtedly the most important factors. Based on the one-dimensional heat transfermodel proposed by Ankur Jain, a3D analytical heat transfer model for3D ICs withthrough silicon via (TSV) is developed in this paper. The simulation results areconsistent with the result based on ANSYS. The results of analysis indicate thatincreasing insertion density of TSV, and radius of TSV, decreasing the thickness of backend of line and adopting TSV insertion of higher thermal conductivity can effectivelyimprove the heat dissipation of3D ICs circuits. It is proved that the importance of TSVin thermal diffusion for3D ICs. Meanwhile, The effects of the horizontal heat transferon the thermal management of3D ICs is analyzed when the number of strata, the TSVdensity, the TSV diameter and the thickness of the BEOL layer vary under the specificprocess and thermal parameters. The results indicated that the temperature rise,simulated by the model presented in this paper, is lower compared with the conditionwithout considering the horizontal heat transfer effect. The difference of the temperaturecan be above10%. And the effect of the horizontal heat transfer on the thermalmanagement of3D ICs is more obvious with the increase of integrated level. Since themodel presented in this paper conforms to the actual situation, it can be more accurate inanalyzing the temperatures of stacked chips in3D ICs.
引文
[1.1]赵保经.大规模和超大规模集成电路.科学技术文献出版社,1984.
[1.2] Claasen T．System on Chip：Changing IC Design Today and in the Future.IEEE Micro.,2004，23(3)：20-26.
[1.3]史密斯，虞慧华.专用集成电路.电子工业出版社，2007.
[1.4] Business Technology, Mastering the art of electronics evolution[EB/OL].201l.URLhttp://biztechreport.co.uk/201l/lO/mastering-the-art-of-electronics-evoIution/
[1.5] Khan A., Recent developments in high-performance system-on-chip IC design[A]. In; IEEE International Conference on Integrated Circuit Design andTechnology[C].2004:151-158.
[1.6]钟波，考虑温度的纳米级CMOS互连线延时和功耗研究.西安电子科技大学硕士论文,2010
[1.7] www.intel.com.
[1.8] http://www.samsung.com/
[1.9] http://www.tsmc.com/english/default.htm
[1.10] http://www.smics.com/chn/
[1.11] Semiconductor Industry Association2011International Technology Roadmapfor Semiconductors2011(ITRS2011).
[1.12] Tu K N. Recent advances on electromigration in very-large-scale-integrationof interconnects. Journal of applied physics,2003,94(9):5451-5473.
[1.13] Semiconductor Industry Association2007International Technology Roadmapfor Semiconductors2007(ITRS2007)
[1.14] Ismail Y I, Friedman E G, Neves J L. Equivalent Elmore Delay for RLC Trees.Computer-aided Design of Integrated Circuits and Systems.2000,19(1):83-97.
[1.15] Cheng C K, et al (著),喻文健等(译).超大规模集成电路互连线分析与综合.清华大学出版社,2008.
[1.16]董刚，杨银堂，柴常春等.多芯片组件互连的功耗分析.计算机辅助设计与图形学学报,2005,17(8):1809-1812.
[1.17] Zhang Y, Li H W, Min YH, Li X W, Selected Transition Time Adjustment forTolerating Crosstalk Effects on Network-on-Chip Interconnects. IEEETransaction On Very Large Scale Integration (VLSI) Systems.2001,19(10):1787-1800.
[1.18] Ho C C, C B S, S-Parameters-Based High Speed Sign al Characterization ofAl and Cu Interconnect on Low-k Hydrogen Silsesquioxane-Si Substrate。2007International Microsystems, Packaging, Assembly and CircuitsTechnology Conference, Piscataway, NJ, USA,2007,262-265.
[1.19] Alam S M, Wei F L, Gan C L,et al. Electromigration Reliability Comparisonof Cu and Al Interconnects,. Proceedings.6th International Symposium onQuality Electronic Design, San Jose, CA, USA,2005:303-308.
[1.20] Ling J, Xu T, Chen R, et al. Cu and Al-Cu Composite-Material Interconnectsfor Power Devices.2012IEEE62nd Electronic Components and TechnologyConference, San Diego, CA, USA,2012:1905-1911
[1.21] Semiconductor Industry Association2009International Technology Roadmapfor Semiconductors2009(ITRS2009).
[1.22]钱立波，基于65nmCMOS工艺的互连串扰及延时优化技术，西安电子科技大学硕士论文,2010..
[1.23] Lannon J, Gregory C, Lueck M, et al. High density Cu-Cu interconnectsbonding for3-D integration.2009IEEE59th Electronic Components andTechnology Conference, San Diego, CA, USA,2009:355-359.
[1.24] Rabaey J M, Chandrakasan A, Nikolie B, Digital Integrated Ciucuits:ADesignPerspective Second Editio. Pearson Education1stEdition2010
[1.25] Wang Y Y, Kang J F.Development of VLSI Interconnect IntegrationTechnology-Copper Interconnect with Low K Dielectrics. Chinese Journal ofSemiconductors,2002,23(11):1121-1134.
[1.26] A Y J, Sato S, Nihei M. Carbon Nanotubes for VLSI: Interconnect andTransistor Applications. Proceedings of the IEEE. December2010,98(12):2015-2.31
[1.27] Pavlidis V F. Interconnect-Based Design Methodolodies forThree-Dimendional Integrated Circuits. University of Rochester,2008
[1.28]王颀，单智阳，朱云涛等.串扰约束下超深亚微米项层互连线性能的优化.电子学报，2006，34(2)：214-219.
[1.29] John P. Shaping A VLSI Wire to Minimize Elmore Delay. ProceedingsEuropean Design and Test Conference. ED&TC97, Los Alamitos, CA, USA,1997:224-250
[1.30] Gao Y X, Wong D F. Optimal Shape Function for a Bidirectional Wire UnderElmore Delay Model IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems.1999,18(7):994-999
[1.31] El-moursy M A, Friedman E G. Wire shaping of RLC interconnects.Integration, the VLSI journal.2006,40:461-472
[1.32] Ni M, Memik S O. Self-Heating-Aware Optimal Wire Sizing under ElmoreDelay Model.200710th Design, Automation and Test in Europe Conferenceand Exhibition, Nice, France,2007:1373-1378.
[1.33] Kar R, Maheshwari V, Agarwal V, Mal A K, Bhattacharjee A. Modeling ofRLC Interconnect Delay for Ramp Input Using Diffusion Model Approach.IEEE Symposium on Industrial Electronics and Applications, Penang,Malaysia,2010:436-440
[1.34] Zhang H B, Wong M D F, Chao K Y, Deng L. A Practical Low-PowerNonregular Interconnect Design With Manufacturing for Design Approach.IEEE Journal On Emerging And Selected Topics In Circuits And Systems,2012,2(2):322-332.
[1.35] Li X C, Mao J F, Huang,H F, Liu Y Global Interconnect Width and SpacingOptimization for Latency, Bandwidth and Power Dissipation.IEEETransaction on electron device.2005,52(10):2272-2279
[1.36]任杰.深亚微米工艺下SOC互连线时延缓冲器插入与优化研究.上海交通大学硕士,2005
[1.37] Banerjee K, Mehrotra A.Power-Optimal Repeater Insertion Methodology forGlobal Interconnects in Nanometer Designs. IEEE Transactions on ElectronDevices.2002,49(11):2001-2007
[1.38] Chen G Q, Friredman E G. Low-Power Repeaters Driving RC and RLCInterconnects With Delay and Bandwidth Constraints. IEEE Transactions onVery Large Scale Integration Systems.2006,14(2):161-172
[1.39] Ku C J, Ismail Y.Thermal-Aware Methodology for Repeater InsertioninLow-Power VLSI Circuits． IEEE Transactions on Very Large ScaleIntegration Systems．2007,15(8):963-970
[1.40] Wwwraseketra R, Pamunuwa D, Zheng L R, Tenhunen. Minimal-Power,Delay-Balanced Smart Repeaters for Global Interconnects in the NanometerRegime. IEEE Transactions on Very Large Scale Integration (VLSI) systems,2008,16(5)
[1.41]朱樟明,万达经,杨银堂.一种基于多目标约束的互连线宽和线间距优化模型.物理学报.2010,59(7):4837-4842
[1.42] Jiang LL, Cheng Y H, Mao J F. Analysis and Optimization of Thermal-DrivenGlobal Interconnects in Nanometer Design. IEEE Components, Packaging,and Manufacturing Technology.2011,1(10):1564-1572
[1.43] Farjad Z, Masoumi N. Accurate Extraction of Inductively-Affected DelayUsing an Optimized Tapered Partitioning Scheme for Global Interconnects.2011IEEE9th International New Circuits and Systems Conference,Piscataway, NJ, USA,2011:138-140.
[1.44] Kim D H, Lim K S Through-Silicon-Via-aware Delay and Power PredictionModel for Buffered Interconnects in3D.Ics.12th ACM/IEEE InternationalWorkshop on System Level Interconnect Prediction, SLIP'10, Anaheim, CA,United states,2010:25-31.
[1.45] Lee Y J, Lim S K. Fast Delay Estimation with Buffer Insertion forThrough-Silicon-Via-Based3D Interconnects.201213th InternationalSymposium on Quality Electronic Design, Santa Clara, CA, USA,2012:228-235.
[2.1] Ni M, Memik S O M. Self-Heating Aware Optimal Wire Sizing under ElmoreDelay Model. Proc. Des.Autom. Test Eur. DATE NiceAcropolis,2007:1373
[2.2] Ajami A H, Banerjee K, Pedram M. Modeling and Analysis of NonuniformSubstrate Temperature Effects on Global ULSI Interconnects. IEEE Trans.Comput.-Aided Des. Integr. Circuits Syst,2005,24(6):849-861.
[2.3] Shang Q, Li X C, Mao L. Transient Thermal Analysis of Global InterconnectsBased on Transmission Lines.2012Asia-Pacific Symposium onElectromagnetic Compatibility, Singapore, Singapore,2012:245-248
[2.4]王增,董刚,杨银堂等.考虑温度分布效应的非对称RLC树时钟偏差研究.物理学报.2010,59(8):5646-5651
[2.5] Hsie M C. Packaging Effects of Cu/Low-k Interconnect Structure.2007International Conference on Thermal, Mechanical and Multi-PhysicsSimulation Experiments in Microelectronics and Micro-Systems. EuroSime,London, UK,2007:398-402
[2.6] Morusupalli R, Rao R, Lee T K, Shen Y L, et al. Critical temperature shift forStress Induced Voiding in Advanced Cu Interconnects for32nm and beyond.2012IEEE International Reliability Physics Symposium, Anaheim, CA, USA,2012:8.1-8.3
[2.7]张金松,吴懿平,王永国等.集成电路微互连结构中的热迁移.物理学报,2010,59(6):4395-4402
[2.8] http://ptm.asu.edu/
[2.9] Roy A and Chowdhury M H. Global Interconnect Optimization in thePresence of On-chip Inductance.2007IEEE International Symposium onCircuits and Systems, New Orleans, LA, USA,2007:885-888
[2.10] Savidis I, Friedman E G. Closed-Form Expressions of3-D Via Resistance,Inductance, and Capacitance. IEEE Transactions On Electron Devices,2009,56(9):1873-1881
[2.11] Kar R, Maheshwari V, Choudhary A. A Novel Bandwidth Estimation Methodfor Distributed On-Chip RLCG Interconnects.2010International Conferenceon Signal and Image Processing, Chennai, India,2010:372-376
[2.12]陈仲先,喻文健.超大规模集成电路分析与综合.清华大学出版社.2008.
[2.13]钟波,考虑温度的纳米级互连线延迟和功耗研究.硕士论文,西电电子科技大学,2010
[2.14] Katoch A, Seevinck E, H Veendrick. Fast Signal Propagation for Point toPoint On-Chip Long Interconnects using current Sensing. ESSCIRC2002.Proceedings of the28th European Solid-State Circuit Conference. Bologna,Italy,2002:195-198.
[2.15]鲁晟,高速低功耗片上互连接收电路研究与设计,硕士论文,上海交通大学,2013
[2.16] Palitl A K, Meyer V, Anheier W. Modeling and analysis of crosstalk couplingeffect on the victim interconnect using the ABCD network model. IEEE Int.Symp. Defect Fault Tolerance VLSI Syst. Cannes, France,2004:174-182.
[2.17] Sahoo S, Da任英磊,毛军发,李晓春.斜阶跃信号激励下的RLC互连线时延模型.微电子学,2005,35(3):290-292.
[2.18] Sahoo S, Datta M, Kar R. An Efficient Dynamic Power Estimation Methodfor On-Chip VLSI Interconnects. Proceedings of the Second InternationalConference on Emerging Applications of Information Technology, Kolkata,India,2011:379-382.
[2.19] Sengupta D, Maheshwari V, Kar R. Unified Delay Analysis for On-ChipRLCG Interconnects for Ramp Input using Fourth Order Transfer Function.2010International Conference on Signal and Image Processing, Chennai,India,2010:357-361
[2.20] Tuuna S, Nigussie E, Isoaho J. Modeling of Energy Dissipation in RLCCurrent-Mode Signaling. IEEE Trans. Very Large Scale Integr.(VLSI) Syst.,2012,20(6):1146-1151.
[2.21] Sahoo S, Datta M, Kar R. An Efficient Dynamic Power Estimation Method forOn-Chip VLSI Interconnects. Second International Conference on EmergingApplications of Information Technology, Kolkata, India,2011:379-382
[2.22] Chen G Q. Friedman E G.. Effective Capacitance of Inductive Interconnectsfor Short-Circuit Power Analysis. IEEE Transactions On Circuits AndSystems,2008,55(1):26-30.
[2.23] Karnik T, Borkar S, De V. Sub90-nm Technologies-Challenges andOpportunities for CAD. in Proc. Int. Conf. Comput.-Aided Des.2002:203-206.
[2.24] Pedram M, Nazarian S. Thermal modeling, analysis and manage-ment inVLSI circuits: principles and methods. Proc. of IEEE, SpecialIssue onThermalAnalysis of ULSI,2006,94(8):487–1501,
[2.25] Lee Y M, Chen C C P, Wong D F2002IEEE Trans. Circuits Syst. I, Fundam.Theory Appl.491671
[2.26] Chen C P, Chen, Y P, Wong D F. Optimal Wire-Sizing Formula Under theElmore Delay Model. Proceedings-Design Automation Conference,1996:487-490
[2.27] Ni M, Memik S O. Slef-Heating-Aware Optimal Wire Sizing under ElmoreDelay Model. Automation and Test in Europe Conference and Exhibition.2007:
[2.28] Palitl AK, Meyer V, Anheier W. Modeling and Analysis of Crosstalk CouplingEffect on the Victim Interconnect Using the ABCD Network Model. IEEEInternational Symposium on Defect and Fault Tolerance, Los Alamitos, CA,USA,2004:174-182
[2.29] Ajami A H. Banerjee K, Pedram M. Modeling and Analysis of NonuniformSubstrate Temperature Effects on Global ULSI Interconnects. IEEE Trans.Comput.-Aided Des. Integr. Circuits Syst,2005,24(6):849-861.
[2.30] Chen P Y. Wu C W. Kwai D M. On-Chip TSV Testing for3D IC beforeBonding Using Sense Amplification.200918th Asian Test Symposium,Piscataway, NJ, USA,2009:450-455
[2.31] Savidis I, Friedman E G. Closed-Form Expressions of3-D Via Reststance,Inductance, and Capacitance. IEEE Transactions on Electron Devices,2009,56(9):1873-1881
[2.32] Kim D H, Mukhopadhyay S, Lim S K. Fast and Accurate Analytical Modelingof Through-Silicon-Via Capacitive Coupling. IEEE Transactions OnComponents, Packaging,And Manufacturing Technology,2011,1(2):168-180
[2.33] Katti G, Stucchi M, Meyer K D, et al. Electrical Modeling andCharacterizaiton of Through Silicon via for Three-Dimensional ICs. IEEETrans. Electron Devi.,2010,57(1):256-262
[2.34] Todri A, Kundu S, et al. A Study of Taperd3-D TSVs for Power and ThermalIntegrity.IEEE Tansactions On Very large Scale Integration (VLSI) Sysstems,2013,21(2):306-319
[3.1] Fishburn J P, Schevon C A. Shaping A Distributed-RC Line to MinimizeElmore Delay. Proceedings. European Design and Test Conference. ED&TC97, USA,1995:1020-1022.
[3.2] Gao Y X, Wong D F. Shaping a VLSI Wire to Minimize Delay UsingTransmission Line Model. IEEE/ACM International Conference onComputer-Aided Design. Digest of Technical Papers, USA,1998:611-616.
[3.3] Lee Y M, Chen C C P, Wong D F. Optimal Wire-Sizing Function Under theElmore Delay Model With Bounded Wire Sizes. IEEE Trans Circuits Syst. I,Fundam. Theor Appl,2002,49(7):1671-1677.
[3.4] El-moursy M A, Friedman E G. Wire shaping of RLC interconnects.Integration, the VLSI journal.2006,40:461-472
[3.5] Kar R, Maheshwari V, Agarwal V, Mal A K, Bhattacharjee A. Modeling ofRLC Interconnect Delay for Ramp Input Using Diffusion Model Approach [R].IEEE Symposium on Industrial Electronics and Applications, Penang,Malaysia,2010:436-440
[3.6] Zhang H B, Wong M D F, Chao K Y, Deng L. A Practical Low-PowerNonregular Interconnect Design With Manufacturing for Design Approach [J].IEEE Journal On Emerging And Selected Topics In Circuits And Systems,2012,2(2):322-332.
[3.7] Fishburn J P, Schevon C A. Shaping A Distributed-RC Line to MinimizeElmore Delay. Proceedings. European Design and Test Conference. ED&TC97, USA,1995:1020-1022.
[3.8] Gao Y X, Wong D F. Shaping a VLSI Wire to Minimize Delay UsingTransmission Line Model. IEEE/ACM International Conference onComputer-Aided Design. Digest of Technical Papers, USA,1998:611-616.
[3.9] Lee Y M, Chen C C P, Wong D F. Optimal Wire-Sizing Function Under theElmore Delay Model With Bounded Wire Sizes. IEEE Trans Circuits Syst. I,Fundam. Theor Appl,2002,49(7):1671-1677.
[3.10] El-moursy M A, Friedman E G. Wire shaping of RLC interconnects.Integration, the VLSI journal.2006,40:461-472
[3.11] Kar R, Maheshwari V, Agarwal V, Mal A K, Bhattacharjee A. Modeling ofRLC Interconnect Delay for Ramp Input Using Diffusion Model Approach [R].IEEE Symposium on Industrial Electronics and Applications, Penang,Malaysia,2010:436-440
[3.12] Zhang H B, Wong M D F, Chao K Y, Deng L. A Practical Low-PowerNonregular Interconnect Design With Manufacturing for Design Approach [J].IEEE Journal On Emerging And Selected Topics In Circuits And Systems,2012,2(2):322-332.
[3.13] El-moursy M A, Fridman E G. Wire shaping of RLC interconnects. Integr.VLSI J,2006:40461-472
[3.14] Alpert Charles J. Devgan A, et al. Interconnect Synthesis Without WireTapering. IEEE Transactions on Computer-Aided Design of IntegratedCircuitsAnd Systems.2001,20(1):90-104
[3.15] Li R, Zhou D, Liu J, et al. Power-Optimal Simultaneous BufferInsertion/Sizing and Wire Sizing for Two-Pin Nets. IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems.2005,24(12):1915-1924
[3.16] Wang X S, Han L, Liu X C, et al. Wire Sizing Regulation Algorithm for VLSIInterconnect Timing Optimization.2012IEEE11th International Conferenceon Solid-State and Integrated Circuit Technology. Xi'an, China,2012: pp3.
[3.17] Tuuna S, Nigussie E, Isoaho J. Modeling of Energy Dissipation in RLCCurrent-Mode Signaling. IEEE Trans. Very Large Scale Integr.(VLSI) Syst.,2012,20(6):1146-1151.
[3.18] Sahoo S, Datta M, Kar R. An Efficient Dynamic Power Estimation Methodfor On-Chip VLSI Interconnects. Second International Conference onEmerging Applications of Information Technology, Los Alamitos, CA,USA.2011:397-382
[3.19] Li X C, Mao J F, et al. Dynamic Power Model of CMOS Gates DrivingTransmission Lines Based on Fourier Analysis. IEEE Transactions on ElectronDevices,2008,55(2):594-600.
[3.20] Quasi-Resonant Interconnects: A Low Power, Low Latency DesignMethodology. IEEE Transactions On Very Large Scale Integrations ON(VLSI),2009,17(2):181-193.
[3.21] Chao A K A, Kapur P, Morifuji E. Electro-Thermally Coupled PowerOptimization for Future Transistors and Its Applications. IEEE TransactionsOn Electron Devices,200754(7):1696-1704Kar R. Maheshwari V., Mondal S, et al. A Novel Power Estimation Method forOn-Chip VLSI Distributed RLCG Global Interconnects Using Model OrderReduction Technique. Advances in Computer Engineering (ACE),2010International Conference on, Bangalore, Karnataka, India,2012:105-109
[3.22] Li F, LinY, He L. Vdd Programmability to Reduce FPGA InterconnectPower," ICCAD2004. International Conference on Computer Aided Design,San Jose, CA, USA,2004:760-765
[3.23] http://www. eas. asu. edu/~ptm/
[4.1] Uchino T, Cong J. An Interconnect Energy Model ConsideringCouplingEffects. IEEE Trans. Comput.-Aided Des. of Integr. Circuits Syst,2002,21(7)763-776
[4.2]朱樟明,钟波,杨银堂.基于RLC型等效模型的互连网络精确焦耳热功耗计算.物理学报.2010,59(7):4895-4900.
[4.3] Sahoo S, Data M, Kar R. An Efficient Dynamic Power Estimation Method forOn-Chip VLSI Interconnects.2011Proceedings of the Second InternationalConference on Emerging Applications of Information Technology Kolkata,India,2011:379-382.
[4.4] Zhou Q M, Elmore K M. Elmore Model for Energy Estimationin RC Trees.ACM∕IEEE Design Automation Conf. San-Francisco, CA, USA,2006:965-970
[4.5]朱樟明,钟波,赫报田,杨银堂,一种考虑温度的分布式互连线功耗模型.物理学报,2009,58(10):7124-7129
[4.6] Li F, LinY, He L. Vdd Programmability to Reduce FPGA InterconnectPower," ICCAD2004. International Conference on Computer Aided Design,San Jose, CA, USA,2004:760-765
[4.7] Choi S M*, Baek D C, Jeong T Y. A Practical Modeling for TransientThermal Characteristics of Multilevel Interconnects.2011IEEE InternationalReliability Physics Symposium,2011:734-739
[4.8] Rzepka S, Banerjee K, MeuselE, et al. Characterization of self-heating inadvanced VLSI interconnect lines based on thermal finite element simulation.IEEE Trans. Compon., Packag., Manufact. Technol.-A,1998,21(3):406–411
[4.9] Ajami A H, Banerjee K, Pedram M. Modeling and Analysis of NonuniformSubstrate Temperature Effects on Global ULSI Interconnects. IEEE Trans.Comput.-Aided Des. Integr. Circuits Syst,2005,24(6):849-861.
[4.10] Ni M, Memik S O M. Self-Heating Aware Optimal Wire Sizing under ElmoreDelay Model. Proc. Des. Autom. Test Eur. Nice Acropolis, France,,2007:1373-1378
[4.11] Pedram M, Nazarian S. Thermal Modeling, Analysis, and Management inVLSICircuits: Principles and Methods. Proceedings of the IEEE,2006,94(8):1487-501.
[4.12] A Thermal Simulation Process Based on Electrical Modeling for ComplexInterconnect, Packaging, and3DI Structures. IEEE Transactions On AdvicedPackaging,2010,33(4):777-786
[4.13] http://www. eas. asu. edu/~ptm/
[4.14] Semiconductor Industry Association2009International Technology Roadmapfor Semiconductors2009(ITRS2009).
[4.15] Chandrakasan A P, Sheng S, Brodersen R W. Low-Power CMOS DigitalDesign. IEEE Journal of Solid-State Circuits,1992,27(4):473-484.
[4.16] Liu D, Svenson C. Power consum estimation in CMOS VLSI chips. IEEEJournal of Solid—State Circuits,1994,29(6):663-670
[4.17] Chandrakasan A P, Brodersen R W. Sources of power consumption. LowPower Digital CMOS Design, Norwell，MA：Kluwer,1995．
[4.18] Balasubramanian P, Narayanan H C, Anantha K. Low Power Design of DigitalCombinatorial Circuits with Complementary CMOS Logic. InternationalJournal of Electrical and Computer Engineering,2007,2(9):580-588
[5.1] Vinita V D, Jeffrey AD, et al. Optimal Voltage Scaling, Repeater Insertion, andWire Sizing for Wave-Pipelined Global Interconnects. IEEE Transactions onCircuits and Systems-I: Fundamental Theory and Applications,2008,55(4):1023-1030.
[5.2] Chen G Q, Friedman E G. Low-Power Repeaters Driving RC and RLCInterconnects With Delay and Bandwidth Constraints. IEEE Trans. Very LargeScale Integr.(VLSI) Syst.,2006,14(2):161-172.
[5.3] Abinash R, Chowdhury M H. Global Interconnect Optimization in thePresence of On-chip Inductance. IEEE International Symposium on Circuitsand Systems, Piscataway, NJ, USA,2007:885-889
[5.4] Faiz-ul-Hassan, Fernando R, Vanderbauwhede W A. Optimization of On-ChipLink Performance under Area, Power and Variability Constraints.22ndInternational Conference on Microelectronics, Cairo, Egypt,2010:48-51
[5.5] Zhu Z M, Wan D J, Yang Y T. An interconnect width and spacing optimizationmodel considering scattering effect. Chin. Phys B,2010,19(9):097803(1-5)
[5.6] Wwwraseketra R, Pamunuwa D, Zheng L R, Tenhunen. Minimal-Power,Delay-Balanced Smart Repeaters for Global Interconnects in the NanometerRegime. IEEE Transactions on Very Large Scale Integration (VLSI) systems,2008,16(5)
[5.7] Tang M, Mao J F. Wire Sizing Optimization for Buffered Global Interconnects.International Conference On Microwave and Millimeter Wave Technology,Piscataway, NJ, USA2008:431-434
[5.8] Zhu Z M, Zhong B, He B T. A novel nanometer CMOS interconnect optimalmodel with target delay and bandwidth constraint. Acta Phys. Sin.,2010,59(3):1997-2203
[5.9] Ashok N, Ramalingam S. Variability Aware Low-Power Delay Optimal BufferInsertion for Global Interconnects. IEEE Trans. Circuits Syst. I, Reg. Pap.,2010,57(12):3055-3063
[5.10] Sharma T. Sharma K G, SINGH B P. A. Efficient Interconnect Design withNovel Repeater Insertion for Low Power Applications. WSEAS Transactionson Circuits and Systems,2010,9(3):153-162.
[5.11] Fargol H, Nasser M. Interconnect Sizing and Spacing with Consideration ofBuffer Insertion for Simultaneous Crosstalk-Delay Optimization. IEEEInternational Conference on Design and Test of Integrated Systems inNanoscale Era, Piscataway, NJ, USA,2008:12008(1-6)
[5.12] Jakushokas R, Friedman E G. Resource Based Optimization for SimultaneousShield and Repeater Insertion. IEEE Trans. Very Large Scale Integr. VLSISyst.,2010,18(5):742-749.
[5.13] Mahmoud Z, Nasser M. Throughput Optimization for InterleavedRepeater-Inserted Interconnects in VLSI Design. IEEE3rd InternationalNanoelectronics Conference Jan., Hongkong, China2010:1443-1444
[5.14] Houman Z, Asim A, Yvon S. Repeater Insertion in Power-Managed VLSISystems. Proc.ACM Great Lakes Symp. VLSI GLSVLSI,2011:395-398.
[5.15] Massimo A, Stephane B, Yusuf L. Optimization of the wire grid size fordifferential routing: Analysis and impact on the power-delay-area tradeoff.Microelectron. J.,2010,41:669-679
[5.16] Sandeep S, A Mahesh K, Sreehari V. An Alternative approach to BufferInsertion for Delay and Power Reduction in VLSI Interconnects.201023rdInternational Conference on VLSI Design,2010:411-416
[5.17] Zhu Z M, Wan D J, Yang Y T. An optimization model of wire size formulti-objective constrain.Acta Phys. Sin.,200959(7):4837-4842
[5.18] Dong G, Liu J, Xue M, Yang Y T. Performance optimization of globalinterconnect based on dual supply and dual threshold voltages. Acta Phys. Sin.,2012,60(4):046602(1-8).
[5.19] Zhu Z M, Qian L B, Yang Y T, Chai C C. A novel interconnect-optimalrepeater insertion model with a target delay constraint. Journal ofSemiconductors,2008,20(4):1847-1850.
[5.20] Ni M, Memik S O M. Self-Heating Aware Optimal Wire Sizing under ElmoreDelay Model. Proc. Des.Autom. Test Eur. DATE NiceAcropolis,2007:1373
[5.21] Chiang T Y, Banerjee K, Saraswat K, Analytical thermal model for multilevelVLSI interconnects incorporating via effect. IEEE Elec-tron Device Lett.,2002,23(1):31–33
[5.22] Ajami A H, Banerjee K, Pedram M. Modeling and Analysis of NonuniformSubstrate Temperature Effects on Global ULSI Interconnects. IEEE Trans.Comput.-Aided Des. Integr. Circuits Syst,2005,24(6):849-861.
[5.23] Shang Q, Li X C, Mao L. Transient Thermal Analysis of Global InterconnectsBased on Transmission Lines.2012Asia-Pacific Symposium onElectromagnetic Compatibility, Singapore, Singapore,2012:245-248
[5.24] Semiconductor Industry Association2012International Technology Roadmapfor Semiconductors2012(ITRS2012).
[5.25]朱樟明,万达经,杨银堂.一种基于多目标约束的互连线宽和线间距优化模型.物理学报,2010,59(7):4837-4842.
[5.26]刘佳,董刚,杨银堂.基于双电源电压和双阈值电压的全局互连性能优化.物理学报2011,6(4):046602(1)-046602(8)
[5.27] Zhu Z M, Wan D J, Y Y T. An Interconnect-Line-Size Optimization ModelConsidering Scattering Effect. IEEE Electron Device Letters,2010,31(7):641-643
[5.28] Zhu Z M, Wan D J, Y Y T. An interconnect width and spacing optimizationmodel considering scattering effect. Chin. Phys. B,19(9):097803(1)-097803(5)
[5.29]贾文兴,基于解析模型的纳米级互连功耗建模及仿真.硕士论文,西电电子科技大学,2012
[5.30] Paul J M. Smit H, Gerard J M.Design techniques for low-power systems.Journal of SystemsArchitecture,2000,46(1):1-21
[5.31]刘恩科,朱秉升,罗晋生.半导体物理（第一版）,电子工业出版社2011
[5.32] Neamen D H. Semiconductor Physics and Devices Basic Principles ThirdEdition. McCraw Hill.2010
[5.33] Hodges D A, Jackson H G, Saleh R A. Analysis and design of digitalintegrated circuits: In Deep Submicron Technology(3rdEdition). McGrawHill.2003.
[5.34] Jiang L L, ChengY H. Analysis and Optimization of Thermal-Driven GlobalInterconnects in Nanometer Design. IEEE Transactions On Components,PackagingAnd Manufacturing Technology,20111(10):1564-1572.
[5.35]朱樟明,郝报田,李儒,杨银堂.一种基于延时和带宽约束的纳米级互连线优化模型,物理学报,201059(3):1997-2003.
[5.36] Zhu Z M, Hao B T, Yang Y T, et al. A novel low-swing interconnectoptimization model with delay and bandwidth constraintsChin. Phys. B,2010,19(12):127805(1)-127805(7)
[5.37] Zhu Z M, Qian L B, Yang Y T, Anovel interconnect-optimal repeater insertionmodel with target delay constraint in65nm CMOS. Chinese Physics B,200918(3):1188-1193
[5.38]朱樟明,钱利波,杨银堂,柴常春,一种基于目标延迟约束缓冲器插入的互连优化模型.半导体学报.2008,29(9):1847-1850
[5.39] http://www. eas. asu. edu/~ptm/
[6.1] Dae H K, Saibal M, Sung K L. TSV-aware Interconnect Length and PowerPrediction for3D Stacked ICs. IEEE International Interconnect TechnologyConference–IITC Sapporo,2009.26-28.
[6.2] Qian L B, Zhu Z M, Yang Y T. Through-silicon-via-aware interconnectprediction model for3D integrated circuirt. Acta Phys. Sin,201261(6)068001(1)-068001(7).
[6.3] Reitz S, Heinig A, Martin R, et al. Thermal Modeling of3D Stacks forFloorplanning.201117thInternational Workshop on Thermal Investigations ofICs and Systems, Paris, France2011.27-29.
[6.4] Bandyopadhyay T. Han K J. Chung D. Rigorous Electrical Modeling ofThrough Silicon Vias (TSVs) with MOS Capacitance Effects,2011,1(6):893-903
[6.5] Kim D H Mukhopadhyay S. Lim S K. TSV-aware Interconnect Length andPower Prediction for3D Stacked ICs.2009IEEE International InterconnectTechnology Conference–IITC. Sapporo, Hokkaido, Japan,2009:26-28.
[6.6] Mahajan R. Thermal management of CPUs: A perspective on trends, needsand opportunities. In International Workshop on Thermal Investigations of ICsand Systems,2002.
[6.7] Cheng E J, Shen Y L. Thermal expansion behavior of through-silicon-viastructures in three-dimensional microelectronic packaging. MicroelectronicsReliability,2012,52(3):534–540
[6.8] John H L, Tang G Y. b Effects of TSVs (through-silicon vias) on thermalperformances of3D IC integration system-in-package (SiP). MicroelectronicsReliability,2012,52(11):2660–2669
[6.9] Reitz S. Heinig A. Martin R. Thermal Modeling of3D Stacks forFloorplanning.201117th International Workshop on Thermal Investigationsof ICs and Systems, Paris, France,2011:pp6.
[6.10] Yan H X, Zhou Q, Hong X L. Thermal aware placement in3D ICs usingquadratic uniformity modeling approach. Integation, The VLSI J,2009,42:175-180.
[6.11] Huang P Y, Lee Y M. Full-Chip Thermal Analysis for the Early Design Stagevia Generalized Integral Transforms. IEEE Transactions On Very Large ScaleIntegration (VLSI) Systems,2009,17(5):613-626
[6.12] Zhang Y, King C R, Zaveri J, et al. Coupled Electrical and Thermal3D ICCentric Microfluidic Heat Sink Design and Technology.2011IEEE61stElectronic Components and Technology Conference (ECTC), Lake BuenaVista, FL, USA,2011:2037-2044
[6.13] Chuan X, Jiang L J, Kolluri S K, et al. Fast3-D Thermal Analysis of ComplexInterconnect Structures Using Electrical Modeling and SimulationMethodologies.2009IEEE/ACM International Conference onComputer-Aided Design (ICCAD2009), San Jose, CA, USA,2009:658-665
[6.14] Kiran P, Gabriel H L. Thermal Analysis of a3D Die-StackedHigh-Performance Microprocessor. GLSVLSI'06-2006ACM Great LakesSymposium on VLSI, Philadelphia, PA, United states,2006:19-24
[6.15] Cong J, Luo G J, Shi Y Y. Thermal-Aware Cell and Through-Silicon-ViaCo-Placement for3D ICs.201148th ACM/EDAC/IEEE Design AutomationConference (DAC2011), New York, NY, USA,2011:670-675.
[6.16] Ding H, Wang W, Qian Z L, et al. Thermal Modeling of Three-DimensionalIntegrated Circuits Considering the Thermal Removal Capability of DifferentTSVs.20113rd Asia Symposium on Quality Electronic Design, Piscataway,NJ, USA,2011:1-7.
[6.17] Wang X P, Zhao W S, Yin W Y. Electrothermal Modelling of Through SiliconVia (TSV) Interconnects.2010IEEE Electrical Design of AdvancedPackaging and Systems Symposium, Singapore, Singapore,2010: pp4
[6.18] Hossain M S, Masood K I, Barua A, Subrina S. Thermal management of3-DIC using Carbon Nanotube Thermal Via.20127th International Conference onElectrical&Computer Engineering (ICECE), Piscataway, NJ, USA,2012:205-208
[6.19] Du X Y, Tang Z A. Thermal Analysis of Four-Layer3D IC with TSVs Basedon Face-to-Back Bonding. IEEE Components, Packaging Manuf. Technol.Soc., Piscataway, NJ, USA,2011:4pp
[6.20] Lau J H, Yue T G. Effects of TSVs (through-silicon vias) on thermalperformances of3D IC integrationsystem-in-package (SiP). MicroelectronicsReliability,2012,52:2660-2669
[6.21] Chen P Y. Wu C W. Kwai D M. On-Chip TSV Testing for3D IC beforeBonding Using Sense Amplification.200918th Asian Test Symposium (ATS2009), Taichung, Taiwan,2009:450-455
[6.22] Savidis I. Friedman E G. Closed-Form Expressions of3-D Via Reststance,Inductance, and Capacitance. IEEE Transactions on Electron Devices,2009,56(9):1873-1881.
[6.23] Katti G, Stucchi M, Meyer K D,et al. Electrical modeling and characterizationof through silicon via for three-dimensional ICs. IEEE Trans. Electron Devi.,2010,57(1):256-262
[6.24] Jain A, Jones R E., Chatterjee R, et al. Analytical and Numerical Modeling ofthe Thermal Performance of Three-Dimensional Integrated Circuits.: IEEETransactions on Components and Packaging Technologies2010,33(1):56-63
[6.25] Todri A, Kundu S, et al. A Study of Taperd3-D TSVs for Power and ThermalIntegrity.IEEE Tansactions On Very large Scale Integration (VLSI) Sysstems,2013,21(2):306-319
[6.26]朱樟明,左平,杨银堂.考虑硅通孔的三维集成电路热传输解析模型.物理学报,2011,60(11):118401(1-5)
[6.27] Yan H X, Zhou Q, Hong X L. Thermal aware placement in3D ICs usingquadratic uniformity modeling approach. Integr. VLSI J.,2009,42:175-180.
[6.28] Huang P Y, Lee Y M. Full-Chip Thermal Analysis for the Early Design Stagevia Generalized Integral Transforms. IEEE Trans. VLSI Systems,2009,17(5):613-626
[6.29] Xu C, Jiang L J, Kolluri S K, et al. Fast3-D Thermal Analysis of ComplexInterconnect Structures Using Electrical Modeling and SimulationMethodologies. IEEE/ACM International Conference on Computer-AidedDesign, California, USA,2009.658-665.
[6.30] Lau J H, Yue T G. Thermal Management of3D IC Integration with TSV(Through Silicon Via). IEEE Electronic Components and TechnologyConference, San Diego, CA, USA,2009.635-640.
[6.31] Ajami A H, Banerjee K, Pedram M. Modeling and Analysis of NonuniformSubstrate Temperature Effects on Global ULSI Interconnects. IEEE Trans.Comput.-Aided Des. Integr. Circuits Syst.,2005,24(6):849-861.
[6.32] Ni M, Memik S O M. Self-Heating Aware Optimal Wire Sizing under ElmoreDelay Model [R]. Proc. Des. Autom. Test Eur. DATE Nice Acropolis,France, IEEE,2007:1373-1378
[6.33] Zhu Z M, Xiu L P, Yang Y T. A multilevel nano-scale interconnection RLCdelay model [J]. Chin. Phys. B,2010,19(7):077802(1-7)
[6.34] Wang N L, Zhou R D. A Novel Analytical Thermal Model for TemperatureEstimation of Multilevel ULSI Interconnects. J. Semiconductors,2004,25(11):1510-1514.
[6.35] Xu C, Li H., Suaya R. Compact AC modeling and performance analysis ofthrough silicon vias in3-D ICs. IEEE Trans. Electron. Devices,2010,57:3405–3417.
[6.36] Liang F, Wang G F, Lin H. Modelling of self-heating effects in multi-wallcarbon nanotube interconnects. Micro&Nano Letters,6(1):52-54.
[1.2] Claasen T．System on Chip：Changing IC Design Today and in the Future.IEEE Micro.,2004，23(3)：20-26.
[1.3]史密斯，虞慧华.专用集成电路.电子工业出版社，2007.
[1.4] Business Technology, Mastering the art of electronics evolution[EB/OL].201l.URLhttp://biztechreport.co.uk/201l/lO/mastering-the-art-of-electronics-evoIution/
[1.5] Khan A., Recent developments in high-performance system-on-chip IC design[A]. In; IEEE International Conference on Integrated Circuit Design andTechnology[C].2004:151-158.
[1.6]钟波，考虑温度的纳米级CMOS互连线延时和功耗研究.西安电子科技大学硕士论文,2010
[1.7] www.intel.com.
[1.8] http://www.samsung.com/
[1.9] http://www.tsmc.com/english/default.htm
[1.10] http://www.smics.com/chn/
[1.11] Semiconductor Industry Association2011International Technology Roadmapfor Semiconductors2011(ITRS2011).
[1.12] Tu K N. Recent advances on electromigration in very-large-scale-integrationof interconnects. Journal of applied physics,2003,94(9):5451-5473.
[1.13] Semiconductor Industry Association2007International Technology Roadmapfor Semiconductors2007(ITRS2007)
[1.14] Ismail Y I, Friedman E G, Neves J L. Equivalent Elmore Delay for RLC Trees.Computer-aided Design of Integrated Circuits and Systems.2000,19(1):83-97.
[1.15] Cheng C K, et al (著),喻文健等(译).超大规模集成电路互连线分析与综合.清华大学出版社,2008.
[1.16]董刚，杨银堂，柴常春等.多芯片组件互连的功耗分析.计算机辅助设计与图形学学报,2005,17(8):1809-1812.
[1.17] Zhang Y, Li H W, Min YH, Li X W, Selected Transition Time Adjustment forTolerating Crosstalk Effects on Network-on-Chip Interconnects. IEEETransaction On Very Large Scale Integration (VLSI) Systems.2001,19(10):1787-1800.
[1.18] Ho C C, C B S, S-Parameters-Based High Speed Sign al Characterization ofAl and Cu Interconnect on Low-k Hydrogen Silsesquioxane-Si Substrate。2007International Microsystems, Packaging, Assembly and CircuitsTechnology Conference, Piscataway, NJ, USA,2007,262-265.
[1.19] Alam S M, Wei F L, Gan C L,et al. Electromigration Reliability Comparisonof Cu and Al Interconnects,. Proceedings.6th International Symposium onQuality Electronic Design, San Jose, CA, USA,2005:303-308.
[1.20] Ling J, Xu T, Chen R, et al. Cu and Al-Cu Composite-Material Interconnectsfor Power Devices.2012IEEE62nd Electronic Components and TechnologyConference, San Diego, CA, USA,2012:1905-1911
[1.21] Semiconductor Industry Association2009International Technology Roadmapfor Semiconductors2009(ITRS2009).
[1.22]钱立波，基于65nmCMOS工艺的互连串扰及延时优化技术，西安电子科技大学硕士论文,2010..
[1.23] Lannon J, Gregory C, Lueck M, et al. High density Cu-Cu interconnectsbonding for3-D integration.2009IEEE59th Electronic Components andTechnology Conference, San Diego, CA, USA,2009:355-359.
[1.24] Rabaey J M, Chandrakasan A, Nikolie B, Digital Integrated Ciucuits:ADesignPerspective Second Editio. Pearson Education1stEdition2010
[1.25] Wang Y Y, Kang J F.Development of VLSI Interconnect IntegrationTechnology-Copper Interconnect with Low K Dielectrics. Chinese Journal ofSemiconductors,2002,23(11):1121-1134.
[1.26] A Y J, Sato S, Nihei M. Carbon Nanotubes for VLSI: Interconnect andTransistor Applications. Proceedings of the IEEE. December2010,98(12):2015-2.31
[1.27] Pavlidis V F. Interconnect-Based Design Methodolodies forThree-Dimendional Integrated Circuits. University of Rochester,2008
[1.28]王颀，单智阳，朱云涛等.串扰约束下超深亚微米项层互连线性能的优化.电子学报，2006，34(2)：214-219.
[1.29] John P. Shaping A VLSI Wire to Minimize Elmore Delay. ProceedingsEuropean Design and Test Conference. ED&TC97, Los Alamitos, CA, USA,1997:224-250
[1.30] Gao Y X, Wong D F. Optimal Shape Function for a Bidirectional Wire UnderElmore Delay Model IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems.1999,18(7):994-999
[1.31] El-moursy M A, Friedman E G. Wire shaping of RLC interconnects.Integration, the VLSI journal.2006,40:461-472
[1.32] Ni M, Memik S O. Self-Heating-Aware Optimal Wire Sizing under ElmoreDelay Model.200710th Design, Automation and Test in Europe Conferenceand Exhibition, Nice, France,2007:1373-1378.
[1.33] Kar R, Maheshwari V, Agarwal V, Mal A K, Bhattacharjee A. Modeling ofRLC Interconnect Delay for Ramp Input Using Diffusion Model Approach.IEEE Symposium on Industrial Electronics and Applications, Penang,Malaysia,2010:436-440
[1.34] Zhang H B, Wong M D F, Chao K Y, Deng L. A Practical Low-PowerNonregular Interconnect Design With Manufacturing for Design Approach.IEEE Journal On Emerging And Selected Topics In Circuits And Systems,2012,2(2):322-332.
[1.35] Li X C, Mao J F, Huang,H F, Liu Y Global Interconnect Width and SpacingOptimization for Latency, Bandwidth and Power Dissipation.IEEETransaction on electron device.2005,52(10):2272-2279
[1.36]任杰.深亚微米工艺下SOC互连线时延缓冲器插入与优化研究.上海交通大学硕士,2005
[1.37] Banerjee K, Mehrotra A.Power-Optimal Repeater Insertion Methodology forGlobal Interconnects in Nanometer Designs. IEEE Transactions on ElectronDevices.2002,49(11):2001-2007
[1.38] Chen G Q, Friredman E G. Low-Power Repeaters Driving RC and RLCInterconnects With Delay and Bandwidth Constraints. IEEE Transactions onVery Large Scale Integration Systems.2006,14(2):161-172
[1.39] Ku C J, Ismail Y.Thermal-Aware Methodology for Repeater InsertioninLow-Power VLSI Circuits． IEEE Transactions on Very Large ScaleIntegration Systems．2007,15(8):963-970
[1.40] Wwwraseketra R, Pamunuwa D, Zheng L R, Tenhunen. Minimal-Power,Delay-Balanced Smart Repeaters for Global Interconnects in the NanometerRegime. IEEE Transactions on Very Large Scale Integration (VLSI) systems,2008,16(5)
[1.41]朱樟明,万达经,杨银堂.一种基于多目标约束的互连线宽和线间距优化模型.物理学报.2010,59(7):4837-4842
[1.42] Jiang LL, Cheng Y H, Mao J F. Analysis and Optimization of Thermal-DrivenGlobal Interconnects in Nanometer Design. IEEE Components, Packaging,and Manufacturing Technology.2011,1(10):1564-1572
[1.43] Farjad Z, Masoumi N. Accurate Extraction of Inductively-Affected DelayUsing an Optimized Tapered Partitioning Scheme for Global Interconnects.2011IEEE9th International New Circuits and Systems Conference,Piscataway, NJ, USA,2011:138-140.
[1.44] Kim D H, Lim K S Through-Silicon-Via-aware Delay and Power PredictionModel for Buffered Interconnects in3D.Ics.12th ACM/IEEE InternationalWorkshop on System Level Interconnect Prediction, SLIP'10, Anaheim, CA,United states,2010:25-31.
[1.45] Lee Y J, Lim S K. Fast Delay Estimation with Buffer Insertion forThrough-Silicon-Via-Based3D Interconnects.201213th InternationalSymposium on Quality Electronic Design, Santa Clara, CA, USA,2012:228-235.
[2.1] Ni M, Memik S O M. Self-Heating Aware Optimal Wire Sizing under ElmoreDelay Model. Proc. Des.Autom. Test Eur. DATE NiceAcropolis,2007:1373
[2.2] Ajami A H, Banerjee K, Pedram M. Modeling and Analysis of NonuniformSubstrate Temperature Effects on Global ULSI Interconnects. IEEE Trans.Comput.-Aided Des. Integr. Circuits Syst,2005,24(6):849-861.
[2.3] Shang Q, Li X C, Mao L. Transient Thermal Analysis of Global InterconnectsBased on Transmission Lines.2012Asia-Pacific Symposium onElectromagnetic Compatibility, Singapore, Singapore,2012:245-248
[2.4]王增,董刚,杨银堂等.考虑温度分布效应的非对称RLC树时钟偏差研究.物理学报.2010,59(8):5646-5651
[2.5] Hsie M C. Packaging Effects of Cu/Low-k Interconnect Structure.2007International Conference on Thermal, Mechanical and Multi-PhysicsSimulation Experiments in Microelectronics and Micro-Systems. EuroSime,London, UK,2007:398-402
[2.6] Morusupalli R, Rao R, Lee T K, Shen Y L, et al. Critical temperature shift forStress Induced Voiding in Advanced Cu Interconnects for32nm and beyond.2012IEEE International Reliability Physics Symposium, Anaheim, CA, USA,2012:8.1-8.3
[2.7]张金松,吴懿平,王永国等.集成电路微互连结构中的热迁移.物理学报,2010,59(6):4395-4402
[2.8] http://ptm.asu.edu/
[2.9] Roy A and Chowdhury M H. Global Interconnect Optimization in thePresence of On-chip Inductance.2007IEEE International Symposium onCircuits and Systems, New Orleans, LA, USA,2007:885-888
[2.10] Savidis I, Friedman E G. Closed-Form Expressions of3-D Via Resistance,Inductance, and Capacitance. IEEE Transactions On Electron Devices,2009,56(9):1873-1881
[2.11] Kar R, Maheshwari V, Choudhary A. A Novel Bandwidth Estimation Methodfor Distributed On-Chip RLCG Interconnects.2010International Conferenceon Signal and Image Processing, Chennai, India,2010:372-376
[2.12]陈仲先,喻文健.超大规模集成电路分析与综合.清华大学出版社.2008.
[2.13]钟波,考虑温度的纳米级互连线延迟和功耗研究.硕士论文,西电电子科技大学,2010
[2.14] Katoch A, Seevinck E, H Veendrick. Fast Signal Propagation for Point toPoint On-Chip Long Interconnects using current Sensing. ESSCIRC2002.Proceedings of the28th European Solid-State Circuit Conference. Bologna,Italy,2002:195-198.
[2.15]鲁晟,高速低功耗片上互连接收电路研究与设计,硕士论文,上海交通大学,2013
[2.16] Palitl A K, Meyer V, Anheier W. Modeling and analysis of crosstalk couplingeffect on the victim interconnect using the ABCD network model. IEEE Int.Symp. Defect Fault Tolerance VLSI Syst. Cannes, France,2004:174-182.
[2.17] Sahoo S, Da任英磊,毛军发,李晓春.斜阶跃信号激励下的RLC互连线时延模型.微电子学,2005,35(3):290-292.
[2.18] Sahoo S, Datta M, Kar R. An Efficient Dynamic Power Estimation Methodfor On-Chip VLSI Interconnects. Proceedings of the Second InternationalConference on Emerging Applications of Information Technology, Kolkata,India,2011:379-382.
[2.19] Sengupta D, Maheshwari V, Kar R. Unified Delay Analysis for On-ChipRLCG Interconnects for Ramp Input using Fourth Order Transfer Function.2010International Conference on Signal and Image Processing, Chennai,India,2010:357-361
[2.20] Tuuna S, Nigussie E, Isoaho J. Modeling of Energy Dissipation in RLCCurrent-Mode Signaling. IEEE Trans. Very Large Scale Integr.(VLSI) Syst.,2012,20(6):1146-1151.
[2.21] Sahoo S, Datta M, Kar R. An Efficient Dynamic Power Estimation Method forOn-Chip VLSI Interconnects. Second International Conference on EmergingApplications of Information Technology, Kolkata, India,2011:379-382
[2.22] Chen G Q. Friedman E G.. Effective Capacitance of Inductive Interconnectsfor Short-Circuit Power Analysis. IEEE Transactions On Circuits AndSystems,2008,55(1):26-30.
[2.23] Karnik T, Borkar S, De V. Sub90-nm Technologies-Challenges andOpportunities for CAD. in Proc. Int. Conf. Comput.-Aided Des.2002:203-206.
[2.24] Pedram M, Nazarian S. Thermal modeling, analysis and manage-ment inVLSI circuits: principles and methods. Proc. of IEEE, SpecialIssue onThermalAnalysis of ULSI,2006,94(8):487–1501,
[2.25] Lee Y M, Chen C C P, Wong D F2002IEEE Trans. Circuits Syst. I, Fundam.Theory Appl.491671
[2.26] Chen C P, Chen, Y P, Wong D F. Optimal Wire-Sizing Formula Under theElmore Delay Model. Proceedings-Design Automation Conference,1996:487-490
[2.27] Ni M, Memik S O. Slef-Heating-Aware Optimal Wire Sizing under ElmoreDelay Model. Automation and Test in Europe Conference and Exhibition.2007:
[2.28] Palitl AK, Meyer V, Anheier W. Modeling and Analysis of Crosstalk CouplingEffect on the Victim Interconnect Using the ABCD Network Model. IEEEInternational Symposium on Defect and Fault Tolerance, Los Alamitos, CA,USA,2004:174-182
[2.29] Ajami A H. Banerjee K, Pedram M. Modeling and Analysis of NonuniformSubstrate Temperature Effects on Global ULSI Interconnects. IEEE Trans.Comput.-Aided Des. Integr. Circuits Syst,2005,24(6):849-861.
[2.30] Chen P Y. Wu C W. Kwai D M. On-Chip TSV Testing for3D IC beforeBonding Using Sense Amplification.200918th Asian Test Symposium,Piscataway, NJ, USA,2009:450-455
[2.31] Savidis I, Friedman E G. Closed-Form Expressions of3-D Via Reststance,Inductance, and Capacitance. IEEE Transactions on Electron Devices,2009,56(9):1873-1881
[2.32] Kim D H, Mukhopadhyay S, Lim S K. Fast and Accurate Analytical Modelingof Through-Silicon-Via Capacitive Coupling. IEEE Transactions OnComponents, Packaging,And Manufacturing Technology,2011,1(2):168-180
[2.33] Katti G, Stucchi M, Meyer K D, et al. Electrical Modeling andCharacterizaiton of Through Silicon via for Three-Dimensional ICs. IEEETrans. Electron Devi.,2010,57(1):256-262
[2.34] Todri A, Kundu S, et al. A Study of Taperd3-D TSVs for Power and ThermalIntegrity.IEEE Tansactions On Very large Scale Integration (VLSI) Sysstems,2013,21(2):306-319
[3.1] Fishburn J P, Schevon C A. Shaping A Distributed-RC Line to MinimizeElmore Delay. Proceedings. European Design and Test Conference. ED&TC97, USA,1995:1020-1022.
[3.2] Gao Y X, Wong D F. Shaping a VLSI Wire to Minimize Delay UsingTransmission Line Model. IEEE/ACM International Conference onComputer-Aided Design. Digest of Technical Papers, USA,1998:611-616.
[3.3] Lee Y M, Chen C C P, Wong D F. Optimal Wire-Sizing Function Under theElmore Delay Model With Bounded Wire Sizes. IEEE Trans Circuits Syst. I,Fundam. Theor Appl,2002,49(7):1671-1677.
[3.4] El-moursy M A, Friedman E G. Wire shaping of RLC interconnects.Integration, the VLSI journal.2006,40:461-472
[3.5] Kar R, Maheshwari V, Agarwal V, Mal A K, Bhattacharjee A. Modeling ofRLC Interconnect Delay for Ramp Input Using Diffusion Model Approach [R].IEEE Symposium on Industrial Electronics and Applications, Penang,Malaysia,2010:436-440
[3.6] Zhang H B, Wong M D F, Chao K Y, Deng L. A Practical Low-PowerNonregular Interconnect Design With Manufacturing for Design Approach [J].IEEE Journal On Emerging And Selected Topics In Circuits And Systems,2012,2(2):322-332.
[3.7] Fishburn J P, Schevon C A. Shaping A Distributed-RC Line to MinimizeElmore Delay. Proceedings. European Design and Test Conference. ED&TC97, USA,1995:1020-1022.
[3.8] Gao Y X, Wong D F. Shaping a VLSI Wire to Minimize Delay UsingTransmission Line Model. IEEE/ACM International Conference onComputer-Aided Design. Digest of Technical Papers, USA,1998:611-616.
[3.9] Lee Y M, Chen C C P, Wong D F. Optimal Wire-Sizing Function Under theElmore Delay Model With Bounded Wire Sizes. IEEE Trans Circuits Syst. I,Fundam. Theor Appl,2002,49(7):1671-1677.
[3.10] El-moursy M A, Friedman E G. Wire shaping of RLC interconnects.Integration, the VLSI journal.2006,40:461-472
[3.11] Kar R, Maheshwari V, Agarwal V, Mal A K, Bhattacharjee A. Modeling ofRLC Interconnect Delay for Ramp Input Using Diffusion Model Approach [R].IEEE Symposium on Industrial Electronics and Applications, Penang,Malaysia,2010:436-440
[3.12] Zhang H B, Wong M D F, Chao K Y, Deng L. A Practical Low-PowerNonregular Interconnect Design With Manufacturing for Design Approach [J].IEEE Journal On Emerging And Selected Topics In Circuits And Systems,2012,2(2):322-332.
[3.13] El-moursy M A, Fridman E G. Wire shaping of RLC interconnects. Integr.VLSI J,2006:40461-472
[3.14] Alpert Charles J. Devgan A, et al. Interconnect Synthesis Without WireTapering. IEEE Transactions on Computer-Aided Design of IntegratedCircuitsAnd Systems.2001,20(1):90-104
[3.15] Li R, Zhou D, Liu J, et al. Power-Optimal Simultaneous BufferInsertion/Sizing and Wire Sizing for Two-Pin Nets. IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems.2005,24(12):1915-1924
[3.16] Wang X S, Han L, Liu X C, et al. Wire Sizing Regulation Algorithm for VLSIInterconnect Timing Optimization.2012IEEE11th International Conferenceon Solid-State and Integrated Circuit Technology. Xi'an, China,2012: pp3.
[3.17] Tuuna S, Nigussie E, Isoaho J. Modeling of Energy Dissipation in RLCCurrent-Mode Signaling. IEEE Trans. Very Large Scale Integr.(VLSI) Syst.,2012,20(6):1146-1151.
[3.18] Sahoo S, Datta M, Kar R. An Efficient Dynamic Power Estimation Methodfor On-Chip VLSI Interconnects. Second International Conference onEmerging Applications of Information Technology, Los Alamitos, CA,USA.2011:397-382
[3.19] Li X C, Mao J F, et al. Dynamic Power Model of CMOS Gates DrivingTransmission Lines Based on Fourier Analysis. IEEE Transactions on ElectronDevices,2008,55(2):594-600.
[3.20] Quasi-Resonant Interconnects: A Low Power, Low Latency DesignMethodology. IEEE Transactions On Very Large Scale Integrations ON(VLSI),2009,17(2):181-193.
[3.21] Chao A K A, Kapur P, Morifuji E. Electro-Thermally Coupled PowerOptimization for Future Transistors and Its Applications. IEEE TransactionsOn Electron Devices,200754(7):1696-1704Kar R. Maheshwari V., Mondal S, et al. A Novel Power Estimation Method forOn-Chip VLSI Distributed RLCG Global Interconnects Using Model OrderReduction Technique. Advances in Computer Engineering (ACE),2010International Conference on, Bangalore, Karnataka, India,2012:105-109
[3.22] Li F, LinY, He L. Vdd Programmability to Reduce FPGA InterconnectPower," ICCAD2004. International Conference on Computer Aided Design,San Jose, CA, USA,2004:760-765
[3.23] http://www. eas. asu. edu/~ptm/
[4.1] Uchino T, Cong J. An Interconnect Energy Model ConsideringCouplingEffects. IEEE Trans. Comput.-Aided Des. of Integr. Circuits Syst,2002,21(7)763-776
[4.2]朱樟明,钟波,杨银堂.基于RLC型等效模型的互连网络精确焦耳热功耗计算.物理学报.2010,59(7):4895-4900.
[4.3] Sahoo S, Data M, Kar R. An Efficient Dynamic Power Estimation Method forOn-Chip VLSI Interconnects.2011Proceedings of the Second InternationalConference on Emerging Applications of Information Technology Kolkata,India,2011:379-382.
[4.4] Zhou Q M, Elmore K M. Elmore Model for Energy Estimationin RC Trees.ACM∕IEEE Design Automation Conf. San-Francisco, CA, USA,2006:965-970
[4.5]朱樟明,钟波,赫报田,杨银堂,一种考虑温度的分布式互连线功耗模型.物理学报,2009,58(10):7124-7129
[4.6] Li F, LinY, He L. Vdd Programmability to Reduce FPGA InterconnectPower," ICCAD2004. International Conference on Computer Aided Design,San Jose, CA, USA,2004:760-765
[4.7] Choi S M*, Baek D C, Jeong T Y. A Practical Modeling for TransientThermal Characteristics of Multilevel Interconnects.2011IEEE InternationalReliability Physics Symposium,2011:734-739
[4.8] Rzepka S, Banerjee K, MeuselE, et al. Characterization of self-heating inadvanced VLSI interconnect lines based on thermal finite element simulation.IEEE Trans. Compon., Packag., Manufact. Technol.-A,1998,21(3):406–411
[4.9] Ajami A H, Banerjee K, Pedram M. Modeling and Analysis of NonuniformSubstrate Temperature Effects on Global ULSI Interconnects. IEEE Trans.Comput.-Aided Des. Integr. Circuits Syst,2005,24(6):849-861.
[4.10] Ni M, Memik S O M. Self-Heating Aware Optimal Wire Sizing under ElmoreDelay Model. Proc. Des. Autom. Test Eur. Nice Acropolis, France,,2007:1373-1378
[4.11] Pedram M, Nazarian S. Thermal Modeling, Analysis, and Management inVLSICircuits: Principles and Methods. Proceedings of the IEEE,2006,94(8):1487-501.
[4.12] A Thermal Simulation Process Based on Electrical Modeling for ComplexInterconnect, Packaging, and3DI Structures. IEEE Transactions On AdvicedPackaging,2010,33(4):777-786
[4.13] http://www. eas. asu. edu/~ptm/
[4.14] Semiconductor Industry Association2009International Technology Roadmapfor Semiconductors2009(ITRS2009).
[4.15] Chandrakasan A P, Sheng S, Brodersen R W. Low-Power CMOS DigitalDesign. IEEE Journal of Solid-State Circuits,1992,27(4):473-484.
[4.16] Liu D, Svenson C. Power consum estimation in CMOS VLSI chips. IEEEJournal of Solid—State Circuits,1994,29(6):663-670
[4.17] Chandrakasan A P, Brodersen R W. Sources of power consumption. LowPower Digital CMOS Design, Norwell，MA：Kluwer,1995．
[4.18] Balasubramanian P, Narayanan H C, Anantha K. Low Power Design of DigitalCombinatorial Circuits with Complementary CMOS Logic. InternationalJournal of Electrical and Computer Engineering,2007,2(9):580-588
[5.1] Vinita V D, Jeffrey AD, et al. Optimal Voltage Scaling, Repeater Insertion, andWire Sizing for Wave-Pipelined Global Interconnects. IEEE Transactions onCircuits and Systems-I: Fundamental Theory and Applications,2008,55(4):1023-1030.
[5.2] Chen G Q, Friedman E G. Low-Power Repeaters Driving RC and RLCInterconnects With Delay and Bandwidth Constraints. IEEE Trans. Very LargeScale Integr.(VLSI) Syst.,2006,14(2):161-172.
[5.3] Abinash R, Chowdhury M H. Global Interconnect Optimization in thePresence of On-chip Inductance. IEEE International Symposium on Circuitsand Systems, Piscataway, NJ, USA,2007:885-889
[5.4] Faiz-ul-Hassan, Fernando R, Vanderbauwhede W A. Optimization of On-ChipLink Performance under Area, Power and Variability Constraints.22ndInternational Conference on Microelectronics, Cairo, Egypt,2010:48-51
[5.5] Zhu Z M, Wan D J, Yang Y T. An interconnect width and spacing optimizationmodel considering scattering effect. Chin. Phys B,2010,19(9):097803(1-5)
[5.6] Wwwraseketra R, Pamunuwa D, Zheng L R, Tenhunen. Minimal-Power,Delay-Balanced Smart Repeaters for Global Interconnects in the NanometerRegime. IEEE Transactions on Very Large Scale Integration (VLSI) systems,2008,16(5)
[5.7] Tang M, Mao J F. Wire Sizing Optimization for Buffered Global Interconnects.International Conference On Microwave and Millimeter Wave Technology,Piscataway, NJ, USA2008:431-434
[5.8] Zhu Z M, Zhong B, He B T. A novel nanometer CMOS interconnect optimalmodel with target delay and bandwidth constraint. Acta Phys. Sin.,2010,59(3):1997-2203
[5.9] Ashok N, Ramalingam S. Variability Aware Low-Power Delay Optimal BufferInsertion for Global Interconnects. IEEE Trans. Circuits Syst. I, Reg. Pap.,2010,57(12):3055-3063
[5.10] Sharma T. Sharma K G, SINGH B P. A. Efficient Interconnect Design withNovel Repeater Insertion for Low Power Applications. WSEAS Transactionson Circuits and Systems,2010,9(3):153-162.
[5.11] Fargol H, Nasser M. Interconnect Sizing and Spacing with Consideration ofBuffer Insertion for Simultaneous Crosstalk-Delay Optimization. IEEEInternational Conference on Design and Test of Integrated Systems inNanoscale Era, Piscataway, NJ, USA,2008:12008(1-6)
[5.12] Jakushokas R, Friedman E G. Resource Based Optimization for SimultaneousShield and Repeater Insertion. IEEE Trans. Very Large Scale Integr. VLSISyst.,2010,18(5):742-749.
[5.13] Mahmoud Z, Nasser M. Throughput Optimization for InterleavedRepeater-Inserted Interconnects in VLSI Design. IEEE3rd InternationalNanoelectronics Conference Jan., Hongkong, China2010:1443-1444
[5.14] Houman Z, Asim A, Yvon S. Repeater Insertion in Power-Managed VLSISystems. Proc.ACM Great Lakes Symp. VLSI GLSVLSI,2011:395-398.
[5.15] Massimo A, Stephane B, Yusuf L. Optimization of the wire grid size fordifferential routing: Analysis and impact on the power-delay-area tradeoff.Microelectron. J.,2010,41:669-679
[5.16] Sandeep S, A Mahesh K, Sreehari V. An Alternative approach to BufferInsertion for Delay and Power Reduction in VLSI Interconnects.201023rdInternational Conference on VLSI Design,2010:411-416
[5.17] Zhu Z M, Wan D J, Yang Y T. An optimization model of wire size formulti-objective constrain.Acta Phys. Sin.,200959(7):4837-4842
[5.18] Dong G, Liu J, Xue M, Yang Y T. Performance optimization of globalinterconnect based on dual supply and dual threshold voltages. Acta Phys. Sin.,2012,60(4):046602(1-8).
[5.19] Zhu Z M, Qian L B, Yang Y T, Chai C C. A novel interconnect-optimalrepeater insertion model with a target delay constraint. Journal ofSemiconductors,2008,20(4):1847-1850.
[5.20] Ni M, Memik S O M. Self-Heating Aware Optimal Wire Sizing under ElmoreDelay Model. Proc. Des.Autom. Test Eur. DATE NiceAcropolis,2007:1373
[5.21] Chiang T Y, Banerjee K, Saraswat K, Analytical thermal model for multilevelVLSI interconnects incorporating via effect. IEEE Elec-tron Device Lett.,2002,23(1):31–33
[5.22] Ajami A H, Banerjee K, Pedram M. Modeling and Analysis of NonuniformSubstrate Temperature Effects on Global ULSI Interconnects. IEEE Trans.Comput.-Aided Des. Integr. Circuits Syst,2005,24(6):849-861.
[5.23] Shang Q, Li X C, Mao L. Transient Thermal Analysis of Global InterconnectsBased on Transmission Lines.2012Asia-Pacific Symposium onElectromagnetic Compatibility, Singapore, Singapore,2012:245-248
[5.24] Semiconductor Industry Association2012International Technology Roadmapfor Semiconductors2012(ITRS2012).
[5.25]朱樟明,万达经,杨银堂.一种基于多目标约束的互连线宽和线间距优化模型.物理学报,2010,59(7):4837-4842.
[5.26]刘佳,董刚,杨银堂.基于双电源电压和双阈值电压的全局互连性能优化.物理学报2011,6(4):046602(1)-046602(8)
[5.27] Zhu Z M, Wan D J, Y Y T. An Interconnect-Line-Size Optimization ModelConsidering Scattering Effect. IEEE Electron Device Letters,2010,31(7):641-643
[5.28] Zhu Z M, Wan D J, Y Y T. An interconnect width and spacing optimizationmodel considering scattering effect. Chin. Phys. B,19(9):097803(1)-097803(5)
[5.29]贾文兴,基于解析模型的纳米级互连功耗建模及仿真.硕士论文,西电电子科技大学,2012
[5.30] Paul J M. Smit H, Gerard J M.Design techniques for low-power systems.Journal of SystemsArchitecture,2000,46(1):1-21
[5.31]刘恩科,朱秉升,罗晋生.半导体物理（第一版）,电子工业出版社2011
[5.32] Neamen D H. Semiconductor Physics and Devices Basic Principles ThirdEdition. McCraw Hill.2010
[5.33] Hodges D A, Jackson H G, Saleh R A. Analysis and design of digitalintegrated circuits: In Deep Submicron Technology(3rdEdition). McGrawHill.2003.
[5.34] Jiang L L, ChengY H. Analysis and Optimization of Thermal-Driven GlobalInterconnects in Nanometer Design. IEEE Transactions On Components,PackagingAnd Manufacturing Technology,20111(10):1564-1572.
[5.35]朱樟明,郝报田,李儒,杨银堂.一种基于延时和带宽约束的纳米级互连线优化模型,物理学报,201059(3):1997-2003.
[5.36] Zhu Z M, Hao B T, Yang Y T, et al. A novel low-swing interconnectoptimization model with delay and bandwidth constraintsChin. Phys. B,2010,19(12):127805(1)-127805(7)
[5.37] Zhu Z M, Qian L B, Yang Y T, Anovel interconnect-optimal repeater insertionmodel with target delay constraint in65nm CMOS. Chinese Physics B,200918(3):1188-1193
[5.38]朱樟明,钱利波,杨银堂,柴常春,一种基于目标延迟约束缓冲器插入的互连优化模型.半导体学报.2008,29(9):1847-1850
[5.39] http://www. eas. asu. edu/~ptm/
[6.1] Dae H K, Saibal M, Sung K L. TSV-aware Interconnect Length and PowerPrediction for3D Stacked ICs. IEEE International Interconnect TechnologyConference–IITC Sapporo,2009.26-28.
[6.2] Qian L B, Zhu Z M, Yang Y T. Through-silicon-via-aware interconnectprediction model for3D integrated circuirt. Acta Phys. Sin,201261(6)068001(1)-068001(7).
[6.3] Reitz S, Heinig A, Martin R, et al. Thermal Modeling of3D Stacks forFloorplanning.201117thInternational Workshop on Thermal Investigations ofICs and Systems, Paris, France2011.27-29.
[6.4] Bandyopadhyay T. Han K J. Chung D. Rigorous Electrical Modeling ofThrough Silicon Vias (TSVs) with MOS Capacitance Effects,2011,1(6):893-903
[6.5] Kim D H Mukhopadhyay S. Lim S K. TSV-aware Interconnect Length andPower Prediction for3D Stacked ICs.2009IEEE International InterconnectTechnology Conference–IITC. Sapporo, Hokkaido, Japan,2009:26-28.
[6.6] Mahajan R. Thermal management of CPUs: A perspective on trends, needsand opportunities. In International Workshop on Thermal Investigations of ICsand Systems,2002.
[6.7] Cheng E J, Shen Y L. Thermal expansion behavior of through-silicon-viastructures in three-dimensional microelectronic packaging. MicroelectronicsReliability,2012,52(3):534–540
[6.8] John H L, Tang G Y. b Effects of TSVs (through-silicon vias) on thermalperformances of3D IC integration system-in-package (SiP). MicroelectronicsReliability,2012,52(11):2660–2669
[6.9] Reitz S. Heinig A. Martin R. Thermal Modeling of3D Stacks forFloorplanning.201117th International Workshop on Thermal Investigationsof ICs and Systems, Paris, France,2011:pp6.
[6.10] Yan H X, Zhou Q, Hong X L. Thermal aware placement in3D ICs usingquadratic uniformity modeling approach. Integation, The VLSI J,2009,42:175-180.
[6.11] Huang P Y, Lee Y M. Full-Chip Thermal Analysis for the Early Design Stagevia Generalized Integral Transforms. IEEE Transactions On Very Large ScaleIntegration (VLSI) Systems,2009,17(5):613-626
[6.12] Zhang Y, King C R, Zaveri J, et al. Coupled Electrical and Thermal3D ICCentric Microfluidic Heat Sink Design and Technology.2011IEEE61stElectronic Components and Technology Conference (ECTC), Lake BuenaVista, FL, USA,2011:2037-2044
[6.13] Chuan X, Jiang L J, Kolluri S K, et al. Fast3-D Thermal Analysis of ComplexInterconnect Structures Using Electrical Modeling and SimulationMethodologies.2009IEEE/ACM International Conference onComputer-Aided Design (ICCAD2009), San Jose, CA, USA,2009:658-665
[6.14] Kiran P, Gabriel H L. Thermal Analysis of a3D Die-StackedHigh-Performance Microprocessor. GLSVLSI'06-2006ACM Great LakesSymposium on VLSI, Philadelphia, PA, United states,2006:19-24
[6.15] Cong J, Luo G J, Shi Y Y. Thermal-Aware Cell and Through-Silicon-ViaCo-Placement for3D ICs.201148th ACM/EDAC/IEEE Design AutomationConference (DAC2011), New York, NY, USA,2011:670-675.
[6.16] Ding H, Wang W, Qian Z L, et al. Thermal Modeling of Three-DimensionalIntegrated Circuits Considering the Thermal Removal Capability of DifferentTSVs.20113rd Asia Symposium on Quality Electronic Design, Piscataway,NJ, USA,2011:1-7.
[6.17] Wang X P, Zhao W S, Yin W Y. Electrothermal Modelling of Through SiliconVia (TSV) Interconnects.2010IEEE Electrical Design of AdvancedPackaging and Systems Symposium, Singapore, Singapore,2010: pp4
[6.18] Hossain M S, Masood K I, Barua A, Subrina S. Thermal management of3-DIC using Carbon Nanotube Thermal Via.20127th International Conference onElectrical&Computer Engineering (ICECE), Piscataway, NJ, USA,2012:205-208
[6.19] Du X Y, Tang Z A. Thermal Analysis of Four-Layer3D IC with TSVs Basedon Face-to-Back Bonding. IEEE Components, Packaging Manuf. Technol.Soc., Piscataway, NJ, USA,2011:4pp
[6.20] Lau J H, Yue T G. Effects of TSVs (through-silicon vias) on thermalperformances of3D IC integrationsystem-in-package (SiP). MicroelectronicsReliability,2012,52:2660-2669
[6.21] Chen P Y. Wu C W. Kwai D M. On-Chip TSV Testing for3D IC beforeBonding Using Sense Amplification.200918th Asian Test Symposium (ATS2009), Taichung, Taiwan,2009:450-455
[6.22] Savidis I. Friedman E G. Closed-Form Expressions of3-D Via Reststance,Inductance, and Capacitance. IEEE Transactions on Electron Devices,2009,56(9):1873-1881.
[6.23] Katti G, Stucchi M, Meyer K D,et al. Electrical modeling and characterizationof through silicon via for three-dimensional ICs. IEEE Trans. Electron Devi.,2010,57(1):256-262
[6.24] Jain A, Jones R E., Chatterjee R, et al. Analytical and Numerical Modeling ofthe Thermal Performance of Three-Dimensional Integrated Circuits.: IEEETransactions on Components and Packaging Technologies2010,33(1):56-63
[6.25] Todri A, Kundu S, et al. A Study of Taperd3-D TSVs for Power and ThermalIntegrity.IEEE Tansactions On Very large Scale Integration (VLSI) Sysstems,2013,21(2):306-319
[6.26]朱樟明,左平,杨银堂.考虑硅通孔的三维集成电路热传输解析模型.物理学报,2011,60(11):118401(1-5)
[6.27] Yan H X, Zhou Q, Hong X L. Thermal aware placement in3D ICs usingquadratic uniformity modeling approach. Integr. VLSI J.,2009,42:175-180.
[6.28] Huang P Y, Lee Y M. Full-Chip Thermal Analysis for the Early Design Stagevia Generalized Integral Transforms. IEEE Trans. VLSI Systems,2009,17(5):613-626
[6.29] Xu C, Jiang L J, Kolluri S K, et al. Fast3-D Thermal Analysis of ComplexInterconnect Structures Using Electrical Modeling and SimulationMethodologies. IEEE/ACM International Conference on Computer-AidedDesign, California, USA,2009.658-665.
[6.30] Lau J H, Yue T G. Thermal Management of3D IC Integration with TSV(Through Silicon Via). IEEE Electronic Components and TechnologyConference, San Diego, CA, USA,2009.635-640.
[6.31] Ajami A H, Banerjee K, Pedram M. Modeling and Analysis of NonuniformSubstrate Temperature Effects on Global ULSI Interconnects. IEEE Trans.Comput.-Aided Des. Integr. Circuits Syst.,2005,24(6):849-861.
[6.32] Ni M, Memik S O M. Self-Heating Aware Optimal Wire Sizing under ElmoreDelay Model [R]. Proc. Des. Autom. Test Eur. DATE Nice Acropolis,France, IEEE,2007:1373-1378
[6.33] Zhu Z M, Xiu L P, Yang Y T. A multilevel nano-scale interconnection RLCdelay model [J]. Chin. Phys. B,2010,19(7):077802(1-7)
[6.34] Wang N L, Zhou R D. A Novel Analytical Thermal Model for TemperatureEstimation of Multilevel ULSI Interconnects. J. Semiconductors,2004,25(11):1510-1514.
[6.35] Xu C, Li H., Suaya R. Compact AC modeling and performance analysis ofthrough silicon vias in3-D ICs. IEEE Trans. Electron. Devices,2010,57:3405–3417.
[6.36] Liang F, Wang G F, Lin H. Modelling of self-heating effects in multi-wallcarbon nanotube interconnects. Micro&Nano Letters,6(1):52-54.