嵌入式随机存储器测试研究及仿真
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摘要
随着集成电路设计和制造技术的不断进步,芯片的集成度和复杂度正按照摩尔定律的速度持续提高。尤其是超深亚微米(VDSM)工艺的使用,生产过程中出现的故障也越来越多样、难测。芯片测试遇到了前所未有的挑战,已成为制约整个行业发展的瓶颈。在这种情况下,从故障类型、测试设备及测试成本考虑,可测性设计(DFT)技术成为解决芯片测试问题的主要手段之一,日益引起人们的重视。
论文主要针对嵌入式系统随机存储器的测试,研究解决办法。首先,介绍了数字集成电路和存储器及测试技术发展现状、趋势。论述了存储器的基本结构、分类、故障模式和故障模型。然后,研究分析了存储器测试的方法,产生测试图形的各种测试生成算法,按图形的测试长度与存储单元大小关系分类举例介绍。这些测试算法,复杂程度不同,故障覆盖率也不同。详细分析了March算法,并将其扩展成能面向字存储器测试的算法。
内建自测试(Built-In-Self-Test,BIST)技术被认为是解决由于电路集成度越来越大所造成的测试费用巨大和测试访问困难等问题的最有希望的技术。本文针对存储器测试采用MBIST。MBIST是目前大规模存储器测试最通用的方法,该方法将BIST逻辑电路嵌入芯片内部,实现片上BIST结构,本文实现了BIST电路的控制器、地址产生器、向量生成器、响应分析器等电路,最终实现片上自动测试存储器。本文采用VHDL程序仿真BIST结构,并仿真一个随机存储器,将各种故障加入其中,采用March C算法,结果表明该方法能覆盖多数故障,从而验证基于March算法BIST结构测试的有效性。
With the increasing of the IC design and manufacturing technology, the integration and complexity of chips keeps increasing in accordance with Moore’s LAW. Especially the VDSM technology is usedm, the faults become more and more types and difficulty to test on the production process. Chip testing issue meets unprecedented challenges, has become a bottleneck restricting the development of the whole industry. In such circumstances, considering from the fault types, test equipments and testing costs, the DFT technology becomes a principal means to solve the chips testing problem, is paid attention gradually by people.
The thesis is about the embedded RAM testing, researches solution. First, the thesis introduces the digital IC, memory and testing technology development status and trends, describes the memory basic structure, categories, failure model and fault models. Then, the thesis researches and analysis memory testing methods, the algorithms which generate the test pattern graphics. The algorithms are described according to the relations between test pattern graphics’length and memory size. These algorithms, the complexity and fault coverage are both different. It analysis the March algorithm in details, and this algorithm has been developed into a kind of word-oriented algorithm.
The IC integration is more and more big; it causes the big testing expense and testing access difficult. BIST (Built-In-Self-Test) is considered for a technology which can solve these problems. The thesis uses MBIST for RAM testing. MBIST is widely used in the mass memory testing. The BIST logic circuit is embedded in the chip, on chip BIST structure. The BIST controller, address counter circuit, the data generator circuit and the response compare circuit have been implemented respectively, the test is automatically run on the chip. The BIST structure and a RAM which is added in many kinds of faults have been simulated with VHDL, use March C algorithm. The result shows the method can cover most faults, it testifies the validity of the MBIST testing based on March algorithm.
论文主要针对嵌入式系统随机存储器的测试,研究解决办法。首先,介绍了数字集成电路和存储器及测试技术发展现状、趋势。论述了存储器的基本结构、分类、故障模式和故障模型。然后,研究分析了存储器测试的方法,产生测试图形的各种测试生成算法,按图形的测试长度与存储单元大小关系分类举例介绍。这些测试算法,复杂程度不同,故障覆盖率也不同。详细分析了March算法,并将其扩展成能面向字存储器测试的算法。
内建自测试(Built-In-Self-Test,BIST)技术被认为是解决由于电路集成度越来越大所造成的测试费用巨大和测试访问困难等问题的最有希望的技术。本文针对存储器测试采用MBIST。MBIST是目前大规模存储器测试最通用的方法,该方法将BIST逻辑电路嵌入芯片内部,实现片上BIST结构,本文实现了BIST电路的控制器、地址产生器、向量生成器、响应分析器等电路,最终实现片上自动测试存储器。本文采用VHDL程序仿真BIST结构,并仿真一个随机存储器,将各种故障加入其中,采用March C算法,结果表明该方法能覆盖多数故障,从而验证基于March算法BIST结构测试的有效性。
With the increasing of the IC design and manufacturing technology, the integration and complexity of chips keeps increasing in accordance with Moore’s LAW. Especially the VDSM technology is usedm, the faults become more and more types and difficulty to test on the production process. Chip testing issue meets unprecedented challenges, has become a bottleneck restricting the development of the whole industry. In such circumstances, considering from the fault types, test equipments and testing costs, the DFT technology becomes a principal means to solve the chips testing problem, is paid attention gradually by people.
The thesis is about the embedded RAM testing, researches solution. First, the thesis introduces the digital IC, memory and testing technology development status and trends, describes the memory basic structure, categories, failure model and fault models. Then, the thesis researches and analysis memory testing methods, the algorithms which generate the test pattern graphics. The algorithms are described according to the relations between test pattern graphics’length and memory size. These algorithms, the complexity and fault coverage are both different. It analysis the March algorithm in details, and this algorithm has been developed into a kind of word-oriented algorithm.
The IC integration is more and more big; it causes the big testing expense and testing access difficult. BIST (Built-In-Self-Test) is considered for a technology which can solve these problems. The thesis uses MBIST for RAM testing. MBIST is widely used in the mass memory testing. The BIST logic circuit is embedded in the chip, on chip BIST structure. The BIST controller, address counter circuit, the data generator circuit and the response compare circuit have been implemented respectively, the test is automatically run on the chip. The BIST structure and a RAM which is added in many kinds of faults have been simulated with VHDL, use March C algorithm. The result shows the method can cover most faults, it testifies the validity of the MBIST testing based on March algorithm.
引文
[1] 杨士元. 数字系统的故障诊断与可靠性设计. 北京:清华大学出版社,2004,4: 149-151
[2] 张必超. 存储器测试技术及其在质量检验中的应用研究.四川大学硕士学位论文,2005: 5-8,27-38
[3] Appelo D. Exploiting programmable BIST for the diagnosis of embedded memory cores. Proc of Int’I Test Conf. Wshington DC: IEEE Computer Society Press,2003,379-385
[4] Tehranipour MH,NavabiZ. An efficient BIST method for testing of embedded SRAMs. Proc IEEE Int’I Symp on Circuits and systems. Sydney:IEEE Compute Society Press,2001,73-76
[5] Sachdev M,Verstraelen M. Development of a fault model and test algorithms for em bedded DRAMs. Proc of Int’I Test Conf.Washington DC:IEEE Computer society Press,1993:815-824
[6] Vishwani D.Agrawal, Charles R.Kime and Kewal K. Saluja.A Tutorial on Built-In Self-Test (Part 1:Principles). IEEE Design&Test of Computer,1993, (3):72-82
[7] Vishwani D.Agrawal, Charles R.Kime and Kewal K.Saluja. A Tutorial on Built-In Self-Test (Part 2:Applications). IEEE Design&Test of Computer,1993,(6):69-77
[8] 雷绍充,绍志标,梁峰. VLSI 测试方法学和可测性设计. 电子工业出版社,2005,1:125-256
[9] 王剑. DDR 存储器的测试方法研究及实现. 上海交通大学硕士学位论文,2004:7-9,15-18,49-51
[10] 姚俊. 基于 BIST 的嵌入式存储器可测性设计算法研究. 哈尔滨工程大学硕士学位论文,2007:16-20,32-37
[11] 曾芷德. 数字系统测试与可测性. 长沙:国防科技大学出版社,1992:56-73
[12] Nadir Zafer Basturkmen. New Built-in Self Test Methods For Scan Designs. Doctor thesis. 2002:1-20
[13] 吴光林. 一种并行内建自诊断测试嵌入式 SRAM 方案. 电路与系统学报,2003,10: 23-27
[14] 陆思安,何乐年,沈海斌,严晓浪. 嵌入式存储器内建自测试的原理及实现.固体电子学研究与进展,2004,24:205-208
[15] 檀彦卓,徐勇军,韩银和,李华伟,李晓维. 面向存储器核的内建自测试. 计算机工程与科学,2005,27:40-43
[16] Dongkyu Youn,Taehyung Kimand Sungju Park. A Microcode- based Memory BIST Implementing Modified March Algorithm. Asian Test Symposium,2001(10):391-395
[17] WANG Wei-Lun,LEE Kuen-Jong,WANG Jging-Fa. An on-chip march pattern generator for testing embedded memory cores. IEEE Trans on VLSI Systems,2001,9(5):14-17
[18] R Dean Adams. High Performance Memory Testing: Design Principle,Fault Modeling and Self-Test. Kluwer Academic Publishers,2003:20-25
[19] Mentor Graphics Corp.Built-In Self-Test Process Guide.Software Version 8. 2002,2:34-37
[20] 程玲,陈护勋. 存储器测试算法的实现. 计算机与数字工程,1998,5:14-16
[21] 范东华. 利用 BIST 技术测试并诊断嵌入式存储器. 测控技术,2001,1:33-3
[22] A.J.van de Goor I.B.S Tlli. March tests for word-oriented memories. Delft University of Technology Faculty of Information Technology and Systems Section Computer Architecture Digital Technique,2001:5-7
[23] 吴光林,胡晨,李锐,杨军,毛武晋. 一种并行内建自测试嵌入式 SRAM 方案. 电路与系统学报,2003,10(8):51-56
[24] 王晓云. 基于双口 RAM 的改进型 BIST 设计与研究. 上海大学硕士学位论文,2005 : 37-41
[25] Rajsuman,R. A new test methodology for testing embedded memores in core based system-on-chip ICs, Proc. IEEE Int.work shop on Testing embedded Cores Based system,1998:341-346
[26] Truong,K. A simple built-in self test for dual ported SRAMs. Memory Technology,Designand Testing,Records of the 2000 IEEE International Workshop on, 2000,7-8(8):79-84
[27] Van de Goor,A.J.,Tlili,I.B.S. March tests for word-oriented memories. Design, Automation and Test in Europe,Proceedings, 1998,3:501-508
[28] 江建慧,朱为国. 嵌入式存储器的内建自测试和内建自修复. 同济大学学报,2004(8):35-38
[29] 张卫新,侯朝焕. 一种改进的嵌入式 SRAM 内建自测试设计. 微电子学,2003(6):19-21
[30] 朱小莉,陈迪平,王镇道. SRAM 的一种可测性设计. 湖南大学学报(自然科学版),2003(12):18-21
[31] 高 平 , 成 立 等 . 数 字 VLSI 电 路 测 试 技 术 -BIST 方 案 . 半 导 体 技 术 ,2003(9):23-26
[32] Van de Goor AD J. Using march tests to test SRAMs. IEEE Design&Test of Computers,1993,10:8-14
[33] SynTest Technologies Inc. Syn Test user guide-rambist v1.1.0. SynTest Technologies Inc,2000
[34] Alan Allan et al. 2001 Technology Roadmap for Semiconductors. IEEE Computer, 2002,35( 1): 42-53
[35] Baosheng Wang,Josh Yang,Andre Ivanov. Reducing Test Time of Embedded SRAMs. IEEE Proceedings of the 2003 International Workshop on Memory Technology, Design and Testing,2003: 86-91
[36] C T Huang,J R Huang,C F Wu et al. A Programmable BIST Core for Embedded DRAM. IEEE Design and Test of Computers,1999: 59-69
[37] 高树静. 嵌入式微处理器可测性设计研究与实现. 青岛大学硕士学位论文,2003: 44-47
[38] 李忠诚. 基于 FAN 算法的测试产生系统及实验研究. 计算机辅助设计与图形学学报,1990(2):33-35
[39] S.Kirmura,E.M Clarke. A parallel Algrithm for Bonary Decision Diagrams. IEEE International Conference on Computer Design,1990:220-223
[40] 程玲,陈护勋. 存储器测试算法的实现. 计算机与数字工程,1998(5):14-16
[41] Franklin,M.,Saluja,K.K. Built-in Self-Testing of Random-Access Memories. IEEE Computer,Vo1.23 (10): 45 -56
[2] 张必超. 存储器测试技术及其在质量检验中的应用研究.四川大学硕士学位论文,2005: 5-8,27-38
[3] Appelo D. Exploiting programmable BIST for the diagnosis of embedded memory cores. Proc of Int’I Test Conf. Wshington DC: IEEE Computer Society Press,2003,379-385
[4] Tehranipour MH,NavabiZ. An efficient BIST method for testing of embedded SRAMs. Proc IEEE Int’I Symp on Circuits and systems. Sydney:IEEE Compute Society Press,2001,73-76
[5] Sachdev M,Verstraelen M. Development of a fault model and test algorithms for em bedded DRAMs. Proc of Int’I Test Conf.Washington DC:IEEE Computer society Press,1993:815-824
[6] Vishwani D.Agrawal, Charles R.Kime and Kewal K. Saluja.A Tutorial on Built-In Self-Test (Part 1:Principles). IEEE Design&Test of Computer,1993, (3):72-82
[7] Vishwani D.Agrawal, Charles R.Kime and Kewal K.Saluja. A Tutorial on Built-In Self-Test (Part 2:Applications). IEEE Design&Test of Computer,1993,(6):69-77
[8] 雷绍充,绍志标,梁峰. VLSI 测试方法学和可测性设计. 电子工业出版社,2005,1:125-256
[9] 王剑. DDR 存储器的测试方法研究及实现. 上海交通大学硕士学位论文,2004:7-9,15-18,49-51
[10] 姚俊. 基于 BIST 的嵌入式存储器可测性设计算法研究. 哈尔滨工程大学硕士学位论文,2007:16-20,32-37
[11] 曾芷德. 数字系统测试与可测性. 长沙:国防科技大学出版社,1992:56-73
[12] Nadir Zafer Basturkmen. New Built-in Self Test Methods For Scan Designs. Doctor thesis. 2002:1-20
[13] 吴光林. 一种并行内建自诊断测试嵌入式 SRAM 方案. 电路与系统学报,2003,10: 23-27
[14] 陆思安,何乐年,沈海斌,严晓浪. 嵌入式存储器内建自测试的原理及实现.固体电子学研究与进展,2004,24:205-208
[15] 檀彦卓,徐勇军,韩银和,李华伟,李晓维. 面向存储器核的内建自测试. 计算机工程与科学,2005,27:40-43
[16] Dongkyu Youn,Taehyung Kimand Sungju Park. A Microcode- based Memory BIST Implementing Modified March Algorithm. Asian Test Symposium,2001(10):391-395
[17] WANG Wei-Lun,LEE Kuen-Jong,WANG Jging-Fa. An on-chip march pattern generator for testing embedded memory cores. IEEE Trans on VLSI Systems,2001,9(5):14-17
[18] R Dean Adams. High Performance Memory Testing: Design Principle,Fault Modeling and Self-Test. Kluwer Academic Publishers,2003:20-25
[19] Mentor Graphics Corp.Built-In Self-Test Process Guide.Software Version 8. 2002,2:34-37
[20] 程玲,陈护勋. 存储器测试算法的实现. 计算机与数字工程,1998,5:14-16
[21] 范东华. 利用 BIST 技术测试并诊断嵌入式存储器. 测控技术,2001,1:33-3
[22] A.J.van de Goor I.B.S Tlli. March tests for word-oriented memories. Delft University of Technology Faculty of Information Technology and Systems Section Computer Architecture Digital Technique,2001:5-7
[23] 吴光林,胡晨,李锐,杨军,毛武晋. 一种并行内建自测试嵌入式 SRAM 方案. 电路与系统学报,2003,10(8):51-56
[24] 王晓云. 基于双口 RAM 的改进型 BIST 设计与研究. 上海大学硕士学位论文,2005 : 37-41
[25] Rajsuman,R. A new test methodology for testing embedded memores in core based system-on-chip ICs, Proc. IEEE Int.work shop on Testing embedded Cores Based system,1998:341-346
[26] Truong,K. A simple built-in self test for dual ported SRAMs. Memory Technology,Designand Testing,Records of the 2000 IEEE International Workshop on, 2000,7-8(8):79-84
[27] Van de Goor,A.J.,Tlili,I.B.S. March tests for word-oriented memories. Design, Automation and Test in Europe,Proceedings, 1998,3:501-508
[28] 江建慧,朱为国. 嵌入式存储器的内建自测试和内建自修复. 同济大学学报,2004(8):35-38
[29] 张卫新,侯朝焕. 一种改进的嵌入式 SRAM 内建自测试设计. 微电子学,2003(6):19-21
[30] 朱小莉,陈迪平,王镇道. SRAM 的一种可测性设计. 湖南大学学报(自然科学版),2003(12):18-21
[31] 高 平 , 成 立 等 . 数 字 VLSI 电 路 测 试 技 术 -BIST 方 案 . 半 导 体 技 术 ,2003(9):23-26
[32] Van de Goor AD J. Using march tests to test SRAMs. IEEE Design&Test of Computers,1993,10:8-14
[33] SynTest Technologies Inc. Syn Test user guide-rambist v1.1.0. SynTest Technologies Inc,2000
[34] Alan Allan et al. 2001 Technology Roadmap for Semiconductors. IEEE Computer, 2002,35( 1): 42-53
[35] Baosheng Wang,Josh Yang,Andre Ivanov. Reducing Test Time of Embedded SRAMs. IEEE Proceedings of the 2003 International Workshop on Memory Technology, Design and Testing,2003: 86-91
[36] C T Huang,J R Huang,C F Wu et al. A Programmable BIST Core for Embedded DRAM. IEEE Design and Test of Computers,1999: 59-69
[37] 高树静. 嵌入式微处理器可测性设计研究与实现. 青岛大学硕士学位论文,2003: 44-47
[38] 李忠诚. 基于 FAN 算法的测试产生系统及实验研究. 计算机辅助设计与图形学学报,1990(2):33-35
[39] S.Kirmura,E.M Clarke. A parallel Algrithm for Bonary Decision Diagrams. IEEE International Conference on Computer Design,1990:220-223
[40] 程玲,陈护勋. 存储器测试算法的实现. 计算机与数字工程,1998(5):14-16
[41] Franklin,M.,Saluja,K.K. Built-in Self-Testing of Random-Access Memories. IEEE Computer,Vo1.23 (10): 45 -56