6H-SiC肖特基势垒源漏MOSFET理论和实验的研究
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摘要
碳化硅(SiC)由于其有热导率高、电子的饱和速度大、击穿电压高等优点而成为制作高温、高频、大功率和抗辐射器件的极具潜力的宽带隙半导体材料。本文提出了一种新型SiC金属氧化物半导体场效应晶体管(MOSFET)结构——SiC肖特基势垒源漏MOSFET。该结构能有效地抑制在器件尺寸大幅度降低时困扰常规MOSFET的短沟效应,避免了离子注入和高温退火工艺对SiC常规MOSFET性能的严重影响。目前国内外在此方面的研究还处于空白,本文从以下方面开展了研究工作:
(1)SiC肖特基接触模型研究。本文通过精确求解一维定态薛定谔方程得到电子通过三角形势垒的隧穿几率,该方法比WKB近似更精确。利用本文计算隧穿几率的方法,采用费米分布代替常用的玻尔兹曼分布优化了SiC肖特基结的电流输运模型。该模型具有更大的普适性、更适合工作在高场条件下的SiC材料,并且能够连续的计算热电子发射电流和隧穿电流。
(2)SiC肖特基势垒源漏MOSFET的理论模型研究。在深入研究肖特基源漏MOSFET工作机理的基础上,对SiC肖特基源漏N沟MOSFET建立了数值-解析模型。模型中引入了有效沟道厚度的概念来描述电流流过的等效截面,正确地计入了隧道电流和势垒降低的影响,能够正确地反映器件的特性。模拟结果显示源极肖特基接触的势垒高度是影响器件特性的主要因素,随着温度升高,器件的特性将变得更好。对SiC肖特基势垒源漏MOSFET的阈值电压给出物理描述:在表面进入强反型后,当源极载流子主要以场发射方式进入沟道时器件进入线性区,此时的栅电压就是器件的阈值电压。
(3)SiC肖特基势垒源漏MOSFET器件结构的研究。初步的实验结果说明侧墙是影响器件特性的主要因素。采用二维模拟软件模拟了侧墙对器件特性的影响。模拟结果说明侧墙厚度在0.1μm以下时对器件特性的负面影响较小。0.1μm以上沟道要在较大的源漏电压下才能开启,饱和电流急剧减小。本文首次提出和论证了具有场致源漏扩展效应的SiC肖特基势垒源漏MOSFET。这种结构通过覆盖在钝化层上的金属场板实现场致源漏扩展,肖特基势垒的宽度被这个金属场板控制。该结构能有效地消除侧墙的影响,提高器件的开态电流。而且该器件的特性对侧墙的厚度不敏感,使得工艺过程更容易控制。
(4)6H-SiC多晶硅源漏-MOSFET的实验研究。高频CV测试中采用了正面接地的新的测试结构,克服了常规测试结构的缺点。通过实验说明了该结构是可行的。本文首次提出采用多晶硅做源漏接触,设计和制备了6H-SiC多晶硅源漏-MOSFET。对测试结果的分析说明:由于刻蚀对SiC造成的表面损伤严重影响了栅氧化层的质量,导致栅电压的控制能力很弱。在此基础上提出了工艺改进措施以及进一步的设想。
Silicon carbide is an attractive wide band semiconductor material in high-temperature, high-frequency, high-power and radiation resistant applications due to its excellent physical properties such as high breakdown voltage, high thermal conductivity and high saturation electron drift velocity. A novel SiC Schottky Barrier Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistor (SiC SBSD-MOSFET) is proposed in this dissertation. This kind device can effectively suppress short channel effects for the scaling down of conventional MOSFETs, avoiding the serious effect of the steps of ion implantation and annealing at high temperature on the conventional SiC MOSFET. There are few papers about this device so far. The main studies and contributions of this dissertation are as follows.
(1) The study on the model of SiC schottky contacts. The electron tunneling probabilities through triangular barrier to be accurately solved by the one-dimensional time-independent Schro|¨dinger equation is calculated. The presented method is more accurate than the usually used method with WKB approximation. The model of SiC schottky contacts is optimized in which Femi distribution is adopted instead of Boltzmann distribution based on the tunneling probabilities calculated with the presented method. The proposed model has the advantages of more universality, more suitability for SiC in high-field application and seamless calculation of thermionic emission and tunneling current.
(2) The study on the theoretical model of SiC SBSD-MOSFET. A numerical-analytical model for SiC SBSD-NMOSFET is presented based on the analysis of the operational mechanism of this device. The device performance is correctly described by presented model including the effect of tunneling current and the barrier lowering in which an equivalent channel thickness is proposed for describing equivalent cross-section of current. The simulated results show that the barrier height at source contact greatly affects on the device performance and its feature will have more improvement as operational temperature rises. Threshold voltage of SiC SBSD-MOSFETs is analyzed. The threshold voltage of the device is defined as the gate voltage at which carriers from the source contact enter the channel by field emission mode while the channel is strongly inverted.
(3) The study on the structure of SiC SBSD-MOSFET. The width of sidewall strongly affects on the device performance from the first experiment. The effect of sidewall on the performance of this kind device is simulated with 2-D simulator. The simulated results show that sidewall with the width less than 0.1μm slightly affects on the device performance. However when the width of sidewall exceeds 0.1μm, the conduction does not occur until the drain voltage is high enough and saturation current is pretty low. A novel SiC SBSD-NMOSFET with field-induced source/drain extension is proposed and demonstrated for the first time. In the new device the FISD extension is induced by a metal field-plate lying on the top of the passivation oxide and the width of Schottky barrier is controlled by the metal field-plate. The new structure not only eliminates the effect of the sidewalls but also significantly improves the on-state current. Moreover the performance of the presented device exhibits very weak dependence on the widths of sidewalls, so process control becomes easier and more reliable.
(4) The study on the experiment of 6H-SiC MOSFET with polysilicon as source/drain contacts. A new front-to-front measurement structure is used for High-frequency C-V measurement. Experiment results show this structure is feasible with advantages over conventional test structure. The scheme of polysilicon as source/drain contacts is proposed for the first time. 6H-SiC MOSFETs with polysilicon as source/drain contacts are designed and fabricated. Measurement and analysis results show that the serious effect of etching process on the surface of SiC is the cause of inferior quality of gate oxide which strongly depresses the control of gate voltage on the channel. The further modification of the process is put forward based on above analysis.
(1)SiC肖特基接触模型研究。本文通过精确求解一维定态薛定谔方程得到电子通过三角形势垒的隧穿几率,该方法比WKB近似更精确。利用本文计算隧穿几率的方法,采用费米分布代替常用的玻尔兹曼分布优化了SiC肖特基结的电流输运模型。该模型具有更大的普适性、更适合工作在高场条件下的SiC材料,并且能够连续的计算热电子发射电流和隧穿电流。
(2)SiC肖特基势垒源漏MOSFET的理论模型研究。在深入研究肖特基源漏MOSFET工作机理的基础上,对SiC肖特基源漏N沟MOSFET建立了数值-解析模型。模型中引入了有效沟道厚度的概念来描述电流流过的等效截面,正确地计入了隧道电流和势垒降低的影响,能够正确地反映器件的特性。模拟结果显示源极肖特基接触的势垒高度是影响器件特性的主要因素,随着温度升高,器件的特性将变得更好。对SiC肖特基势垒源漏MOSFET的阈值电压给出物理描述:在表面进入强反型后,当源极载流子主要以场发射方式进入沟道时器件进入线性区,此时的栅电压就是器件的阈值电压。
(3)SiC肖特基势垒源漏MOSFET器件结构的研究。初步的实验结果说明侧墙是影响器件特性的主要因素。采用二维模拟软件模拟了侧墙对器件特性的影响。模拟结果说明侧墙厚度在0.1μm以下时对器件特性的负面影响较小。0.1μm以上沟道要在较大的源漏电压下才能开启,饱和电流急剧减小。本文首次提出和论证了具有场致源漏扩展效应的SiC肖特基势垒源漏MOSFET。这种结构通过覆盖在钝化层上的金属场板实现场致源漏扩展,肖特基势垒的宽度被这个金属场板控制。该结构能有效地消除侧墙的影响,提高器件的开态电流。而且该器件的特性对侧墙的厚度不敏感,使得工艺过程更容易控制。
(4)6H-SiC多晶硅源漏-MOSFET的实验研究。高频CV测试中采用了正面接地的新的测试结构,克服了常规测试结构的缺点。通过实验说明了该结构是可行的。本文首次提出采用多晶硅做源漏接触,设计和制备了6H-SiC多晶硅源漏-MOSFET。对测试结果的分析说明:由于刻蚀对SiC造成的表面损伤严重影响了栅氧化层的质量,导致栅电压的控制能力很弱。在此基础上提出了工艺改进措施以及进一步的设想。
Silicon carbide is an attractive wide band semiconductor material in high-temperature, high-frequency, high-power and radiation resistant applications due to its excellent physical properties such as high breakdown voltage, high thermal conductivity and high saturation electron drift velocity. A novel SiC Schottky Barrier Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistor (SiC SBSD-MOSFET) is proposed in this dissertation. This kind device can effectively suppress short channel effects for the scaling down of conventional MOSFETs, avoiding the serious effect of the steps of ion implantation and annealing at high temperature on the conventional SiC MOSFET. There are few papers about this device so far. The main studies and contributions of this dissertation are as follows.
(1) The study on the model of SiC schottky contacts. The electron tunneling probabilities through triangular barrier to be accurately solved by the one-dimensional time-independent Schro|¨dinger equation is calculated. The presented method is more accurate than the usually used method with WKB approximation. The model of SiC schottky contacts is optimized in which Femi distribution is adopted instead of Boltzmann distribution based on the tunneling probabilities calculated with the presented method. The proposed model has the advantages of more universality, more suitability for SiC in high-field application and seamless calculation of thermionic emission and tunneling current.
(2) The study on the theoretical model of SiC SBSD-MOSFET. A numerical-analytical model for SiC SBSD-NMOSFET is presented based on the analysis of the operational mechanism of this device. The device performance is correctly described by presented model including the effect of tunneling current and the barrier lowering in which an equivalent channel thickness is proposed for describing equivalent cross-section of current. The simulated results show that the barrier height at source contact greatly affects on the device performance and its feature will have more improvement as operational temperature rises. Threshold voltage of SiC SBSD-MOSFETs is analyzed. The threshold voltage of the device is defined as the gate voltage at which carriers from the source contact enter the channel by field emission mode while the channel is strongly inverted.
(3) The study on the structure of SiC SBSD-MOSFET. The width of sidewall strongly affects on the device performance from the first experiment. The effect of sidewall on the performance of this kind device is simulated with 2-D simulator. The simulated results show that sidewall with the width less than 0.1μm slightly affects on the device performance. However when the width of sidewall exceeds 0.1μm, the conduction does not occur until the drain voltage is high enough and saturation current is pretty low. A novel SiC SBSD-NMOSFET with field-induced source/drain extension is proposed and demonstrated for the first time. In the new device the FISD extension is induced by a metal field-plate lying on the top of the passivation oxide and the width of Schottky barrier is controlled by the metal field-plate. The new structure not only eliminates the effect of the sidewalls but also significantly improves the on-state current. Moreover the performance of the presented device exhibits very weak dependence on the widths of sidewalls, so process control becomes easier and more reliable.
(4) The study on the experiment of 6H-SiC MOSFET with polysilicon as source/drain contacts. A new front-to-front measurement structure is used for High-frequency C-V measurement. Experiment results show this structure is feasible with advantages over conventional test structure. The scheme of polysilicon as source/drain contacts is proposed for the first time. 6H-SiC MOSFETs with polysilicon as source/drain contacts are designed and fabricated. Measurement and analysis results show that the serious effect of etching process on the surface of SiC is the cause of inferior quality of gate oxide which strongly depresses the control of gate voltage on the channel. The further modification of the process is put forward based on above analysis.
引文
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