基于子频带分解的多通道有源电力滤波与无功补偿
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摘要
当前，电力系统的结构日益复杂，电能质量已成为突出和需要迫切解决的问题。其中，无功和谐波对系统的稳定性及生产、传输、利用效率的影响尤为严重，因此已成为交流输电系统的重要研究内容之一。针对谐波治理与无功补偿研究中存在的问题，本文开展了以下四个方面的研究工作。
首先，针对谐波和无功的频谱特性，本文利用小波包方法实现了多通道有源电力滤波与无功补偿。在同步旋转坐标变换的基础上，该方法利用小波包分解与重构技术将补偿容量实时分解到不同子频带内，避免了系统输出波形质量与单一器件工作频率之间的矛盾，有效提高了整个无功补偿和谐波抑制装置的系统容量。该方法是一种系统的多模块多重化技术，着眼于整个系统的谐波治理与无功补偿目标，为大容量、高性能补偿系统提供了一种可行解决方案。同时提出基于锁相环控制循环缓存深度的数据处理手段，较好的解决了小波分析与重构造成的延迟问题，使分解后的指令电流实时跟踪畸变电流的变化。理论分析和仿真结果验证了多通道子带滤波与无功补偿系统的有效性及其动静态性能。
其次，讨论了基于提升格式的小波包算法的特性，继而探讨了提升小波包在多通道子带滤波与无功补偿应用的可行性。完善了一种快速提升结构的小波包分解与重构算法，这种结构通过翻转算法改进了传统提升格式离散小波变换的实现，达到了优化关键路径和硬件资源占用率的目的。本文还探讨了基于VLSI技术实现翻转结构的9／7小波包分解与重构算法方案，为实现多通道有源电力滤波与无功补偿的控制器做出了初步探索。
此外，本文讨论了实时检测三相电压频率和相位信息的三相锁相环方法，解决了有源电力滤波与无功补偿控制算法中的同步问题。并且分析了三相锁相环在谐波、直流偏移、不平衡等情况下的检测误差。为解决复杂的控制算法和日益提高的控制速度与精度要求之间的矛盾，本文提出并设计了基于FPGA技术的有源电力滤波器的控制器，并详细研究了畸变电流检测、低通滤波器和电流矢量双滞环控制的设计和优化方法。受益于硬件结构的并行运算特性，采用FPGA控制器的有源电力滤波装置能够取得良好的动静态实验结果。
最后，本文提出一种适用于STATCOM的直接电流控制方法。针对无功补偿电流的基频特性，建立起计算参考电压的数学模型，并完成了相关仿真和实验研究。同时提出一种简化的SVPWM方案，该算法将传统SVPWM算法的复杂运算全部转化为简单的整数操作，优化了控制器的工作频率和资源占用率，并成功应用在高性能STATCOM控制器的设计中。另外，本文建立了基于电压电流双环STATCOM控制系统的数学模型，推导出PI控制器参数的计算准则，并设计了基于FPGA控制器的动态无功补偿实验平台，完成动态无功补偿的相关实验。实验结果表明采用电压电流双环控制的动态无功补偿系统的动静态性能良好。
Recently, the distribution power system has become much more complex, and it requires more stable and higher quality for power generation, distribution, and consumption. Harmonic and reactive power currents in distribution power system will bring about serious problems. How to use of specialized equipments to cancel the harmonic and reactive power current becomes more and more important. Therefore, active power filter and reactive power compensator have been considered as an effective solution for these problems. To solve the problems existed in the research field of harmonic suppression and reactive power compensation, this paper works in the four areas as listed below.
First, a novel wavelet packet (WP) based sub-bands approach for multichannel harmonic suppression and reactive power compensation is presented and analyzed. This technique distributes power rating into separated channels in frequency domain according to the characteristics of reactive power current and dominant harmonics. Based on this approach, the multiple power modules avoid the conflict between power rating and switching frequency of power electronic unit. Therefore, the proposed approach is suitable to implement harmonic suppression and reactive power compensation in high power applications. The influence of system frequency fluctuating on circle buffer realized periodized extension scheme is analyzed. Then an approach using phase-lock loop (PLL) controlled circle buffer to overcome this problem is presented. Simulation results show good steady-state and dynamic performance of the proposed approach, even when the distorted currents are three-phase unbalanced.
Second, the characteristic of lifting-based discrete wavelet transform and the possibility of adopting this transform into the sub-bands decomposition is discussed. An efficient flipping structure for lifting-based discrete wavelet transform is introduced and analyzed. It can improve and possibly minimize the critical path and hardware resource requirement of the lifting-based discrete wavelet transform by flipping conventional lifting structures. An efficient flipping 9/7 WP-based structure is designed using very large scale integration (VLSI) technology. Though the paper could not complete the whole control design, it makes a useful exploration of the sub-bands decomposition based multi-channels algorithm realization for future harmonic suppression and reactive power compensation application.
Third, according to the synchronization problem of active power filter, three phase phase-locked loop is introduced in this paper. Moreover, the control error of this system is discussed under harmonic, offset, and unbalance conditions. Addressing the architecture optimization, the algorithmic strength reduction, folded architecture and pipling method are adopted to design the controllers, including synchronous reference frame theory based distortion detection, infinite impulse response (IIR) low-pass filter, three-phase phase-lock loop, and hysteresis current controller. As a result, the entire control scheme of shunt active power filter is synthesized on a single medium scale field programmable gate arrays (FPGA) using VerilogHDL. Experimental results achieved from an shunt active power filter system show the steady-state and dynamic performance with realtime and accurate control.
At last, to reduce the switching frequency and current error of a static synchronous compensator (STATCOM) for reactive power compensation, a novel direct current control (DCC) strategy is proposed. The proposed controller outputs the optimum switching pattern according to the double band hysteresis threshold scheme. By using reference current derivative transform instead of predictive method, the scheme accurately detects the location of reference voltage vector in stationary reference frame. This technique can achieve a stable and fast response, while maintaining the switching frequency lower than other conventional current control techniques. Meanwhile, a compact algorithm of space vector pulse width modulation (SVPWM) for three-phase inverters is proposed and developed in this paper. Simplified by the proposed method, the conventional SVPWM is decomposed into fast integer operations entirely by using an intermediate vector, which will properly counteract the redundant calculations of the remaining procedures. This concept can not only simplify a two-level scheme, but is also suited for multilevel implementation. Since it can be implemented without any multiplier or divider, the fast algorithm is especially suitable for FPGA applications. Then an area- and speed-efficient IP-core based on this algorithm is built and tested. It ensures lower hardware resource usage, and at the same time, operates several times faster than some reported examples. An voltage and current control of STATCOM is proposed by using the simplified SVPWM-based controller. Experimental results are investigated to demonstrate the STATCOM performance using the design controller under steady state and dynamic operation.
首先，针对谐波和无功的频谱特性，本文利用小波包方法实现了多通道有源电力滤波与无功补偿。在同步旋转坐标变换的基础上，该方法利用小波包分解与重构技术将补偿容量实时分解到不同子频带内，避免了系统输出波形质量与单一器件工作频率之间的矛盾，有效提高了整个无功补偿和谐波抑制装置的系统容量。该方法是一种系统的多模块多重化技术，着眼于整个系统的谐波治理与无功补偿目标，为大容量、高性能补偿系统提供了一种可行解决方案。同时提出基于锁相环控制循环缓存深度的数据处理手段，较好的解决了小波分析与重构造成的延迟问题，使分解后的指令电流实时跟踪畸变电流的变化。理论分析和仿真结果验证了多通道子带滤波与无功补偿系统的有效性及其动静态性能。
其次，讨论了基于提升格式的小波包算法的特性，继而探讨了提升小波包在多通道子带滤波与无功补偿应用的可行性。完善了一种快速提升结构的小波包分解与重构算法，这种结构通过翻转算法改进了传统提升格式离散小波变换的实现，达到了优化关键路径和硬件资源占用率的目的。本文还探讨了基于VLSI技术实现翻转结构的9／7小波包分解与重构算法方案，为实现多通道有源电力滤波与无功补偿的控制器做出了初步探索。
此外，本文讨论了实时检测三相电压频率和相位信息的三相锁相环方法，解决了有源电力滤波与无功补偿控制算法中的同步问题。并且分析了三相锁相环在谐波、直流偏移、不平衡等情况下的检测误差。为解决复杂的控制算法和日益提高的控制速度与精度要求之间的矛盾，本文提出并设计了基于FPGA技术的有源电力滤波器的控制器，并详细研究了畸变电流检测、低通滤波器和电流矢量双滞环控制的设计和优化方法。受益于硬件结构的并行运算特性，采用FPGA控制器的有源电力滤波装置能够取得良好的动静态实验结果。
最后，本文提出一种适用于STATCOM的直接电流控制方法。针对无功补偿电流的基频特性，建立起计算参考电压的数学模型，并完成了相关仿真和实验研究。同时提出一种简化的SVPWM方案，该算法将传统SVPWM算法的复杂运算全部转化为简单的整数操作，优化了控制器的工作频率和资源占用率，并成功应用在高性能STATCOM控制器的设计中。另外，本文建立了基于电压电流双环STATCOM控制系统的数学模型，推导出PI控制器参数的计算准则，并设计了基于FPGA控制器的动态无功补偿实验平台，完成动态无功补偿的相关实验。实验结果表明采用电压电流双环控制的动态无功补偿系统的动静态性能良好。
Recently, the distribution power system has become much more complex, and it requires more stable and higher quality for power generation, distribution, and consumption. Harmonic and reactive power currents in distribution power system will bring about serious problems. How to use of specialized equipments to cancel the harmonic and reactive power current becomes more and more important. Therefore, active power filter and reactive power compensator have been considered as an effective solution for these problems. To solve the problems existed in the research field of harmonic suppression and reactive power compensation, this paper works in the four areas as listed below.
First, a novel wavelet packet (WP) based sub-bands approach for multichannel harmonic suppression and reactive power compensation is presented and analyzed. This technique distributes power rating into separated channels in frequency domain according to the characteristics of reactive power current and dominant harmonics. Based on this approach, the multiple power modules avoid the conflict between power rating and switching frequency of power electronic unit. Therefore, the proposed approach is suitable to implement harmonic suppression and reactive power compensation in high power applications. The influence of system frequency fluctuating on circle buffer realized periodized extension scheme is analyzed. Then an approach using phase-lock loop (PLL) controlled circle buffer to overcome this problem is presented. Simulation results show good steady-state and dynamic performance of the proposed approach, even when the distorted currents are three-phase unbalanced.
Second, the characteristic of lifting-based discrete wavelet transform and the possibility of adopting this transform into the sub-bands decomposition is discussed. An efficient flipping structure for lifting-based discrete wavelet transform is introduced and analyzed. It can improve and possibly minimize the critical path and hardware resource requirement of the lifting-based discrete wavelet transform by flipping conventional lifting structures. An efficient flipping 9/7 WP-based structure is designed using very large scale integration (VLSI) technology. Though the paper could not complete the whole control design, it makes a useful exploration of the sub-bands decomposition based multi-channels algorithm realization for future harmonic suppression and reactive power compensation application.
Third, according to the synchronization problem of active power filter, three phase phase-locked loop is introduced in this paper. Moreover, the control error of this system is discussed under harmonic, offset, and unbalance conditions. Addressing the architecture optimization, the algorithmic strength reduction, folded architecture and pipling method are adopted to design the controllers, including synchronous reference frame theory based distortion detection, infinite impulse response (IIR) low-pass filter, three-phase phase-lock loop, and hysteresis current controller. As a result, the entire control scheme of shunt active power filter is synthesized on a single medium scale field programmable gate arrays (FPGA) using VerilogHDL. Experimental results achieved from an shunt active power filter system show the steady-state and dynamic performance with realtime and accurate control.
At last, to reduce the switching frequency and current error of a static synchronous compensator (STATCOM) for reactive power compensation, a novel direct current control (DCC) strategy is proposed. The proposed controller outputs the optimum switching pattern according to the double band hysteresis threshold scheme. By using reference current derivative transform instead of predictive method, the scheme accurately detects the location of reference voltage vector in stationary reference frame. This technique can achieve a stable and fast response, while maintaining the switching frequency lower than other conventional current control techniques. Meanwhile, a compact algorithm of space vector pulse width modulation (SVPWM) for three-phase inverters is proposed and developed in this paper. Simplified by the proposed method, the conventional SVPWM is decomposed into fast integer operations entirely by using an intermediate vector, which will properly counteract the redundant calculations of the remaining procedures. This concept can not only simplify a two-level scheme, but is also suited for multilevel implementation. Since it can be implemented without any multiplier or divider, the fast algorithm is especially suitable for FPGA applications. Then an area- and speed-efficient IP-core based on this algorithm is built and tested. It ensures lower hardware resource usage, and at the same time, operates several times faster than some reported examples. An voltage and current control of STATCOM is proposed by using the simplified SVPWM-based controller. Experimental results are investigated to demonstrate the STATCOM performance using the design controller under steady state and dynamic operation.
引文
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