高性能片上网络关键技术研究
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摘要
随着半导体工艺的发展,片上系统(System on Chip, SoC)集成的IP核越来越多,单个芯片可集成数百个IP核。传统的总线通信方式在可扩展性、带宽、功耗、延迟和可靠性等方面难以满足复杂SoC系统需求。通过借鉴分布式计算网络通信方式,片上网络(Network on Chip, NoC)技术在芯片内部各个模块间采用路由和分组交换技术进行数据通信,可有效地解决复杂的SoC通信问题。
本论文深入分析了NoC设计的关键技术,总结了系统级NoC设计方法。为了提高NoC系统在功耗、网络吞吐率及平均网络延迟等方面的性能,在系统级对NoC拓扑结构、映射算法和功耗管理等方面展开深入研究,提出了一些新颖的具有实际应用价值的理论与方法。主要的研究内容和研究成果如下：
(1)在NoC拓扑结构方面,提出了一种新颖的基于五角星形的NoC拓扑结构。该结构采用约翰逊编码实现NoC节点编码,使用全局同步局部异步策略设计基于约翰逊编码的环形FIFO。利用地址的独热码编码方式降低信号亚稳态发生概率,提高存储器读写操作速度。根据五角星形拓扑结构特点,设计由区间路由与组内路由组成的最短路径路由算法。通过理论分析和实验仿真两种方法证明五角星形拓扑结构比2D Mesh和Octagon结构具有更优的网络性能。
(2)为了评估NoC系统FPGA资源占用情况,本文在Xilinx FPGA上验证了基于五角星形拓扑结构的NoC系统。随着系统规模的增长,Pentacle结构牺牲部分面积可获得NoC性能明显的提高。根据拓扑结构的特点,探讨了降低路由算法资源占用的方法,提出了针对五角星形拓扑结构的基于约翰逊编码的路由算法,经仿真验证证明该方法比二进制编码的路由算法占用更少的FPGA资源。
(3)针对带宽和时延约束的低能耗NoC映射问题,提出两种基于遗传算法的映射优化算法,分别为灾变遗传退火和自适应混沌遗传退火算法。论文对优化算法中使用到的遗传基因编码、Boltzmann更新机制、交叉与变异操作、灾变遗传、多邻域的模拟退火以及自适应的混沌优化策略进行了深入研究,并通过大量实验得到了合适的算法参数。在算法的实际优化过程中,引入Boltzmann更新机制选择遗传个体,根据当前种群适应度的计算结果动态调整个体被选择的概率,使得算法搜索向适应度最优的方向靠拢,增加较优个体被选择的概率；对遗传操作后的较优个体采用多邻域的模拟退火操作进行优化,提高算法的精确度。对处于停滞状态的种群,灾变遗传退火算法使用灾变操作重新初始化部分较差个体,跳出局部极值；而自适应混沌遗传退火则引入自适应混沌方法优化适应度较差个体,增加种群多样性。仿真结果表明,两种算法均具有较强的全局搜索和局部寻优的能力,有效地避免了早熟收敛,提高了算法收敛速度。与标准遗传算法、混沌遗传算法相比,具有较好的节能效果,有效地降低了NoC系统通信能耗。
(4)针对支持电压频率岛的NoC能耗优化问题,提出了基于电压频率岛划分、分配以及任务映射的能耗优化方法。该方法通过基于处理器可靠性约束的电压频率岛划分,降低了处理器能耗；利用近凸区域选择的电压频率岛分配策略,减少了不同电压岛间复杂路由器的个数；借助量子粒子群算法优化了NoC映射,降低了系统的通信能耗。经过随机通信任务和应用实例的仿真验证,证明所提出的算法有效地降低了NoC系统的整体能耗。论文在NoC平台中引入多个电压频率岛,通过电压频率岛划分、电压分配、映射优化3种策略的有机结合,在满足处理器可靠性约束条件下实现了NoC功耗的有效管理。
本文提出的拓扑结构、映射算法以及基于电压频率岛的能耗优化方法,为高性能片上网络系统设计提供重要的技术基础和新的解决思路。
With the development of semiconductor technology, more and more IP cores can be integrated into a System on Chip (SoC), with hundreds of IP cores on a single chip. Conventional bus communication mode fails to meet the requirements of complex SoC in scalability, bandwidth, power, delay and reliability. Borrowing ideas from the distributed computing network communication mode, Network on Chip (NoC) technology employs routing and packet-switching to realize data communication between modules on the chip, thus effectively facilitating complex SoC communication.
This dissertation analyses in detail the key technologies of NoC design and summarizes a system level NoC design approach. An in-depth study is made of NoC topology, mapping algorithm and power management on system level in an attempt to improve the performance of NoC system in power consumption, network throughput and average network delay. The major researches and the findings are:
(1) A novel Pentacle NoC topology is proposed, which employs Johnson code to realize NoC node coding. Global synchronization local asynchronization strategy is used to design circular FIFO based on Johnson code. The one-hot coding of address lowers the probability of occurrence of the signal metastable state and improves the memory read/write speed. Based on the features of Pentacle topology, the shortest path routing algorithm consisting of interval routing and in-group routing is designed. Both theoretical analysis and simulation prove that the Pentacle topology is superior to2D Mesh and Octagon topology in network performance.
(2) The NoC system based on Pentacle topology is verified on Xilinx FPGA to evaluate its FPGA resource occupancy. With the increase in system scale, a dramatic improvement in NoC performance can be achieved by sacrificing part of the area of Pentacle structure. Various methods for lowering the resource occupancy of the routing algorithm are discussed, and the algorithm based on Johnson code is proposed for Pentacle topology. Simulation verifies that the proposed method occupies less FPGA resources than binary-coded routing algorithm.
(3) Two mapping optimization algorithms based on genetic algorithm, namely the catastrophic genetic annealing and adaptive chaos genetic annealing, are proposed for the low energy consumption mapping of NoC with bandwidth and delay constraints. A thorough study is made of the genetic coding, Boltzmann updating mechanism, cross and mutation operation, catastrophic genetics, multi-neighborhood simulated annealing and the adaptive chaos optimization strategy used in the optimization algorithm, and proper algorithm parameters are obtained through extensive experiments. In actual algorithm optimization, Boltzmann updating mechanism is introduced to select genetic individuals. The probability of an individual being selected is dynamically adjusted according to current population fitness for the algorithm search to get close to the optimal fitness thus increasing the probability of better individuals being selected; better individuals in genetic operations are optimized by multi-neighborhood simulated annealing to improve algorithm accuracy. For the population in stagnation, the catastrophic genetic annealing algorithm uses catastrophic operation to reinitialize part of worse individuals so as to jump out of a local optimum; while the adaptive chaos genetic annealing introduces adaptive chaos technique to optimize worse fitness individuals for better population diversity. Simulation shows that both algorithms have good global searching and local optimization ability, thus effectively avoiding premature convergence and improving algorithm convergence speed; and that they have higher energy efficiency than standard genetic algorithms and chaos genetic algorithms, thus significantly lowering the energy consumption of NoC system communication.
(4) For energy consumption optimization of NoC with voltage frequency islands, an optimization method is proposed based on voltage frequency island partitioning, assignment and task mapping. Voltage frequency island partitioning based on processor reliability constraint is used to reduce processor energy consumption; the voltage-frequency islands assignment strategy of near convex region selection is employed to reduce the number of complex routers between different voltage islands; and NoC mapping is optimized by Quantum-behaved Particle Swarm Optimization algorithm to lower system communication energy consumption. Simulation of random communication tasks and examples of application shows that the proposed algorithm can effectively reduce the overall energy consumption of the NoC system. The introduction of multiple voltage frequency islands on the NoC platform realizes effective NoC power management while satisfying processor reliability constraints by incorporating the three strategies of voltage frequency island partitioning, voltage assignment and mapping optimization.
The topology, mapping algorithm and energy consumption optimization based on voltage frequency island proposed in this dissertation provide crucial technical foundation for and a novel approach to high performance NoC system design.
本论文深入分析了NoC设计的关键技术,总结了系统级NoC设计方法。为了提高NoC系统在功耗、网络吞吐率及平均网络延迟等方面的性能,在系统级对NoC拓扑结构、映射算法和功耗管理等方面展开深入研究,提出了一些新颖的具有实际应用价值的理论与方法。主要的研究内容和研究成果如下：
(1)在NoC拓扑结构方面,提出了一种新颖的基于五角星形的NoC拓扑结构。该结构采用约翰逊编码实现NoC节点编码,使用全局同步局部异步策略设计基于约翰逊编码的环形FIFO。利用地址的独热码编码方式降低信号亚稳态发生概率,提高存储器读写操作速度。根据五角星形拓扑结构特点,设计由区间路由与组内路由组成的最短路径路由算法。通过理论分析和实验仿真两种方法证明五角星形拓扑结构比2D Mesh和Octagon结构具有更优的网络性能。
(2)为了评估NoC系统FPGA资源占用情况,本文在Xilinx FPGA上验证了基于五角星形拓扑结构的NoC系统。随着系统规模的增长,Pentacle结构牺牲部分面积可获得NoC性能明显的提高。根据拓扑结构的特点,探讨了降低路由算法资源占用的方法,提出了针对五角星形拓扑结构的基于约翰逊编码的路由算法,经仿真验证证明该方法比二进制编码的路由算法占用更少的FPGA资源。
(3)针对带宽和时延约束的低能耗NoC映射问题,提出两种基于遗传算法的映射优化算法,分别为灾变遗传退火和自适应混沌遗传退火算法。论文对优化算法中使用到的遗传基因编码、Boltzmann更新机制、交叉与变异操作、灾变遗传、多邻域的模拟退火以及自适应的混沌优化策略进行了深入研究,并通过大量实验得到了合适的算法参数。在算法的实际优化过程中,引入Boltzmann更新机制选择遗传个体,根据当前种群适应度的计算结果动态调整个体被选择的概率,使得算法搜索向适应度最优的方向靠拢,增加较优个体被选择的概率；对遗传操作后的较优个体采用多邻域的模拟退火操作进行优化,提高算法的精确度。对处于停滞状态的种群,灾变遗传退火算法使用灾变操作重新初始化部分较差个体,跳出局部极值；而自适应混沌遗传退火则引入自适应混沌方法优化适应度较差个体,增加种群多样性。仿真结果表明,两种算法均具有较强的全局搜索和局部寻优的能力,有效地避免了早熟收敛,提高了算法收敛速度。与标准遗传算法、混沌遗传算法相比,具有较好的节能效果,有效地降低了NoC系统通信能耗。
(4)针对支持电压频率岛的NoC能耗优化问题,提出了基于电压频率岛划分、分配以及任务映射的能耗优化方法。该方法通过基于处理器可靠性约束的电压频率岛划分,降低了处理器能耗；利用近凸区域选择的电压频率岛分配策略,减少了不同电压岛间复杂路由器的个数；借助量子粒子群算法优化了NoC映射,降低了系统的通信能耗。经过随机通信任务和应用实例的仿真验证,证明所提出的算法有效地降低了NoC系统的整体能耗。论文在NoC平台中引入多个电压频率岛,通过电压频率岛划分、电压分配、映射优化3种策略的有机结合,在满足处理器可靠性约束条件下实现了NoC功耗的有效管理。
本文提出的拓扑结构、映射算法以及基于电压频率岛的能耗优化方法,为高性能片上网络系统设计提供重要的技术基础和新的解决思路。
With the development of semiconductor technology, more and more IP cores can be integrated into a System on Chip (SoC), with hundreds of IP cores on a single chip. Conventional bus communication mode fails to meet the requirements of complex SoC in scalability, bandwidth, power, delay and reliability. Borrowing ideas from the distributed computing network communication mode, Network on Chip (NoC) technology employs routing and packet-switching to realize data communication between modules on the chip, thus effectively facilitating complex SoC communication.
This dissertation analyses in detail the key technologies of NoC design and summarizes a system level NoC design approach. An in-depth study is made of NoC topology, mapping algorithm and power management on system level in an attempt to improve the performance of NoC system in power consumption, network throughput and average network delay. The major researches and the findings are:
(1) A novel Pentacle NoC topology is proposed, which employs Johnson code to realize NoC node coding. Global synchronization local asynchronization strategy is used to design circular FIFO based on Johnson code. The one-hot coding of address lowers the probability of occurrence of the signal metastable state and improves the memory read/write speed. Based on the features of Pentacle topology, the shortest path routing algorithm consisting of interval routing and in-group routing is designed. Both theoretical analysis and simulation prove that the Pentacle topology is superior to2D Mesh and Octagon topology in network performance.
(2) The NoC system based on Pentacle topology is verified on Xilinx FPGA to evaluate its FPGA resource occupancy. With the increase in system scale, a dramatic improvement in NoC performance can be achieved by sacrificing part of the area of Pentacle structure. Various methods for lowering the resource occupancy of the routing algorithm are discussed, and the algorithm based on Johnson code is proposed for Pentacle topology. Simulation verifies that the proposed method occupies less FPGA resources than binary-coded routing algorithm.
(3) Two mapping optimization algorithms based on genetic algorithm, namely the catastrophic genetic annealing and adaptive chaos genetic annealing, are proposed for the low energy consumption mapping of NoC with bandwidth and delay constraints. A thorough study is made of the genetic coding, Boltzmann updating mechanism, cross and mutation operation, catastrophic genetics, multi-neighborhood simulated annealing and the adaptive chaos optimization strategy used in the optimization algorithm, and proper algorithm parameters are obtained through extensive experiments. In actual algorithm optimization, Boltzmann updating mechanism is introduced to select genetic individuals. The probability of an individual being selected is dynamically adjusted according to current population fitness for the algorithm search to get close to the optimal fitness thus increasing the probability of better individuals being selected; better individuals in genetic operations are optimized by multi-neighborhood simulated annealing to improve algorithm accuracy. For the population in stagnation, the catastrophic genetic annealing algorithm uses catastrophic operation to reinitialize part of worse individuals so as to jump out of a local optimum; while the adaptive chaos genetic annealing introduces adaptive chaos technique to optimize worse fitness individuals for better population diversity. Simulation shows that both algorithms have good global searching and local optimization ability, thus effectively avoiding premature convergence and improving algorithm convergence speed; and that they have higher energy efficiency than standard genetic algorithms and chaos genetic algorithms, thus significantly lowering the energy consumption of NoC system communication.
(4) For energy consumption optimization of NoC with voltage frequency islands, an optimization method is proposed based on voltage frequency island partitioning, assignment and task mapping. Voltage frequency island partitioning based on processor reliability constraint is used to reduce processor energy consumption; the voltage-frequency islands assignment strategy of near convex region selection is employed to reduce the number of complex routers between different voltage islands; and NoC mapping is optimized by Quantum-behaved Particle Swarm Optimization algorithm to lower system communication energy consumption. Simulation of random communication tasks and examples of application shows that the proposed algorithm can effectively reduce the overall energy consumption of the NoC system. The introduction of multiple voltage frequency islands on the NoC platform realizes effective NoC power management while satisfying processor reliability constraints by incorporating the three strategies of voltage frequency island partitioning, voltage assignment and mapping optimization.
The topology, mapping algorithm and energy consumption optimization based on voltage frequency island proposed in this dissertation provide crucial technical foundation for and a novel approach to high performance NoC system design.
引文
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