分布式功率变换器的控制结构设计及其同步、容错性能研究
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摘要
电力电子系统集成、标准化和模块化技术是本世纪电力电子技术发展的必由之路。对于由电力电子模块通过一定的连接方式而构成的功率变换器或电源应用系统的相关技术的研究,是近些年电力电子学科一个重要而热门的方向。本文以采用分布式控制的、由若干电力电子基本单元构成的新型变换器系统为主要研究对象,对于新型变换器系统所出现的新特点以及可能出现的新问题等方面进行了系统而详细的研究。
首先论文以采用分布式控制并由若干电力电子基本单元构成的功率变换器为研究对象,分析了这种变换器的特点,并对其硬件结构和控制设计进行了详细的描述,主要包括电力电子基本单元功率级的拓扑选取、分布式控制下分层结构的功能划分、各基本模块单元的组网方式、通信协议的设计以及数据报文格式的定义等等。基于系统集成技术的分布式功率变换器对实现系统高可靠性,缩短开发周期、降低大规模生产成本有非常重要的作用。本文所提出的分布式功率变换器的控制结构设计的基本思路和理论分析对后续工作的研究具有重要的参考价值。
本文进一步提出了一种基于FPGA的异步过采样混合信号控制结构。该控制结构仅包含了一个FPGA控制器、一个DAC转换器以及一个比较器。其中,FPGA控制器用来完成DPWM信号产生以及PID算法的实现。DAC转换器与比较器协同工作用来实现两种操作功能:一种定义为转换状态用来完成逐次逼近AD转换,一种定义为调制状态用来实现模拟域下的PWM调制器功能。这种混合信号的控制结构具有即时响应的优点,它的动态特性非常接近模拟控制方案。更重要的是,在该控制结构中所用器件都适合功率集成。这种混合控制结构的优良性能为其在更多更广的工业控制系统中的应用提供了可能。
此外,本文对不同调制方式下采用分布式控制的变换器系统的同步特性以及同步误差对系统输出的影响进行了系统而详细的讨论和研究。首先,本文以PSPWM调制的三相五电平级联型逆变器为例,考虑了载波同步误差、调制波同步误差和采样同步误差三种误差形态对同步性能的影响。三种误差都将导致输出相电压的谐波频谱中额外的低次载波边带谐波成分的出现。并且随着同步误差的增大,输出相电压的THD值也会随之增大。本文对三种误差对系统输出的影响进行了详细的分析,从理论计算和仿真结果以及实验结果中进行横向和纵向的对比,得出在误差影响下系统输出相电压各谐波成分分布的一般规律,并总结了三种误差对输出相电压影响程度大小的重要结论,其中,载波同步误差对输出相电压的影响要比相同的调制波同步误差和采样同步误差对输出相电压的影响显著得多。
以SVPWM调制的三相全桥逆变器为例,分析了同步误差对系统输出特性的影响。通过双傅立叶分析计算和Matlab仿真,本文对采用SVPWM调制的分布式控制的变换器在存在同步误差情况下的谐波能量转移特性进行了详细而系统的分析和验证。同步误差将导致输出线电压中额外的低次基波边带谐波、载波边带谐波以及奇数倍数次载波谐波成分的出现。同样,所得同步误差对谐波分布规律影响的相关结论对于基于基本单元构建的采用分布式控制SVPWM调制的变换器系统的同步特性的研究将有一定的指导意义。
最后,本文以具有冗余开关状态的由基本单元构成的多电平变换器拓扑为研究对象,讨论了当开关管器件发生故障时容错技术的实现。我们所采取的系统重构策略是以联动处理互补工作的开关管对为基础,按照故障分类情况,对故障开关管对进行联动处理,从而使系统不受故障开关管对的影响,仍然能实现正常的平衡的线电压输出。而且,在重构后的电路运行状态下,硬件电路和器件的电压应力都没有改变。本文中以PDPWM和PSPWM调制方法为例,讨论故障下的重构方法。但是这种重构思想可以很容易推广到其他载波调制方法上去,当然也为其他容错技术的实现提供了新的思路。该种方法非常简单易实现,只需修改软件,无需再增加任何硬件结构,这种“无负担”属性也会使其受到业界青睐,在多电平变换器应用领域将获得良好的应用。
论文各章节中都包含了大量的仿真和实验验证,用以证明了理论分析的正确性和可靠性。
Power electronics system integration, standardization and modulation are the most significant issues for power electronics developments in this century. The related technologies of distributed power converters or power systems, which are built with power electronics modules by some interconnection method, are the important research focuses. Hence, the distributed converters built with several power electronics basic cells have been studied in this paper, and new characteristics and possible problems of distributed converters have been investigated systematically and particularly.
First, the distributed converters built with several power electronics basic cells have been studied in the paper. The characteristics of distributed converters as well as the hardware designs and control methods are presented in detail. Particularly, the topology selection of the basic cell's power stage, the function design of distributed control, the interconnection of basic cells, the communication protocol design and the definition of the data transportation formats are investigated specifically. The distributed power converters play an important role in improving system reliability, shortening design cycle time and decreasing manufacturing cost. The proposed control design methods for distributed power converters are valuable for the further research.
Furthermore, the FPGA-based mixed-signal controller with asynchronous over sampling for switch mode converters is investigated in the paper. The proposed control architecture contains a FPGA, a DAC and a comparator, where the FPGA is a control processor that implements DPWM generation and a PID control algorithm. The DAC in conjunction with the comparator operates in two operational modes: one is a conversion mode performing successive approximation A/D conversion, and the other is a modulation mode providing an instant pulse-width modulator in the analog domain. The fast response of this mixed-signal control architecture makes itself close in dynamic behaviour to its analog counterpart. Furthermore, the proposed solution is also effective, since all components used are viable for power electronics integration. Its features and performance are sufficient to promote itself for implementation in many industrial digital control systems.
Besides, synchronization effects and performance degradation of the distributed inverters built with several power electronic basic cells controlled with different PWM strategies, are presented in this paper. The paper analyzes the synchronization performance when three kinds of synchronization errors (i.e., carrier synchronization error, reference synchronization error, and sampling synchronization error) exist by a three phase five-level cascaded inverter built with basic cells. All synchronization errors will lead to additional low order carrier sideband harmonics in the phase leg output voltage, and the THD of the phase leg output voltage increases as the synchronization error increases. This paper analyzes the impact of the three kinds of synchronization errors on the whole system performance systematically, as well as detailed synchronization implementation. Meanwhile, the harmonic energy distribution rules of the output voltage with the synchronization errors are derived from the comparisons of theoretical analysis, simulations and experimental results, as well as the conclusions on the performance degradation with the three kinds of errors. It is noticeable that the carrier synchronization error affects the output voltage performance more significantly than the reference synchronization error and the sampling error.
Further, the paper presents the performance degradation of a distributed inverter built with several basic cells using a SVPWM strategy. The transfer of the total harmonic energy of the line-to-line output voltage was explicitly analyzed using Fourier analysis and Matlab simulation, when a synchronization error or startup delay exists between two basic cells. The synchronization error leads to baseband low order haromincs, additional carrier sideband harmonics and odd multiples of carrier harmincs in the line-to-line output voltage. The derived conclusions on the harmonics distribution rules with the synchronization error are valuable for practical applications of SVPWM inverters built with basic modules using a distributed control scheme.
Finally, this paper focuses on the fault-tolerance potential of multilevel inverters with redundant switching states built with basic cells. The gate signals can be reconfigured according to the failure modes when some of the power devices fail. Balanced line-to-line voltage will be achieved with the proposed method when device failure occurs. Furthermore, the circuit structures can be the same as the general ones and the voltage stress of the devices does not increase. The solutions for PDPWM and PSPWM strategy are discussed in this paper but the concept can be extended to other carrier-based PWM strategies easily. And also the concept provides a new idea for the fault tolerant technology. The proposed method can easily be implemented since the reconfiguration of the PWM strategy can be implemented in software, without extra hardware requirements. Its perfect characteristics enable itself to be widely used in the multilevel converter applications.
The validity and accuracy of the theoretical analysis is proven by many simulations and experimental results in each chapter.
The work is sponsored by the National Nature Science Foundation of China (50777055).
首先论文以采用分布式控制并由若干电力电子基本单元构成的功率变换器为研究对象,分析了这种变换器的特点,并对其硬件结构和控制设计进行了详细的描述,主要包括电力电子基本单元功率级的拓扑选取、分布式控制下分层结构的功能划分、各基本模块单元的组网方式、通信协议的设计以及数据报文格式的定义等等。基于系统集成技术的分布式功率变换器对实现系统高可靠性,缩短开发周期、降低大规模生产成本有非常重要的作用。本文所提出的分布式功率变换器的控制结构设计的基本思路和理论分析对后续工作的研究具有重要的参考价值。
本文进一步提出了一种基于FPGA的异步过采样混合信号控制结构。该控制结构仅包含了一个FPGA控制器、一个DAC转换器以及一个比较器。其中,FPGA控制器用来完成DPWM信号产生以及PID算法的实现。DAC转换器与比较器协同工作用来实现两种操作功能:一种定义为转换状态用来完成逐次逼近AD转换,一种定义为调制状态用来实现模拟域下的PWM调制器功能。这种混合信号的控制结构具有即时响应的优点,它的动态特性非常接近模拟控制方案。更重要的是,在该控制结构中所用器件都适合功率集成。这种混合控制结构的优良性能为其在更多更广的工业控制系统中的应用提供了可能。
此外,本文对不同调制方式下采用分布式控制的变换器系统的同步特性以及同步误差对系统输出的影响进行了系统而详细的讨论和研究。首先,本文以PSPWM调制的三相五电平级联型逆变器为例,考虑了载波同步误差、调制波同步误差和采样同步误差三种误差形态对同步性能的影响。三种误差都将导致输出相电压的谐波频谱中额外的低次载波边带谐波成分的出现。并且随着同步误差的增大,输出相电压的THD值也会随之增大。本文对三种误差对系统输出的影响进行了详细的分析,从理论计算和仿真结果以及实验结果中进行横向和纵向的对比,得出在误差影响下系统输出相电压各谐波成分分布的一般规律,并总结了三种误差对输出相电压影响程度大小的重要结论,其中,载波同步误差对输出相电压的影响要比相同的调制波同步误差和采样同步误差对输出相电压的影响显著得多。
以SVPWM调制的三相全桥逆变器为例,分析了同步误差对系统输出特性的影响。通过双傅立叶分析计算和Matlab仿真,本文对采用SVPWM调制的分布式控制的变换器在存在同步误差情况下的谐波能量转移特性进行了详细而系统的分析和验证。同步误差将导致输出线电压中额外的低次基波边带谐波、载波边带谐波以及奇数倍数次载波谐波成分的出现。同样,所得同步误差对谐波分布规律影响的相关结论对于基于基本单元构建的采用分布式控制SVPWM调制的变换器系统的同步特性的研究将有一定的指导意义。
最后,本文以具有冗余开关状态的由基本单元构成的多电平变换器拓扑为研究对象,讨论了当开关管器件发生故障时容错技术的实现。我们所采取的系统重构策略是以联动处理互补工作的开关管对为基础,按照故障分类情况,对故障开关管对进行联动处理,从而使系统不受故障开关管对的影响,仍然能实现正常的平衡的线电压输出。而且,在重构后的电路运行状态下,硬件电路和器件的电压应力都没有改变。本文中以PDPWM和PSPWM调制方法为例,讨论故障下的重构方法。但是这种重构思想可以很容易推广到其他载波调制方法上去,当然也为其他容错技术的实现提供了新的思路。该种方法非常简单易实现,只需修改软件,无需再增加任何硬件结构,这种“无负担”属性也会使其受到业界青睐,在多电平变换器应用领域将获得良好的应用。
论文各章节中都包含了大量的仿真和实验验证,用以证明了理论分析的正确性和可靠性。
Power electronics system integration, standardization and modulation are the most significant issues for power electronics developments in this century. The related technologies of distributed power converters or power systems, which are built with power electronics modules by some interconnection method, are the important research focuses. Hence, the distributed converters built with several power electronics basic cells have been studied in this paper, and new characteristics and possible problems of distributed converters have been investigated systematically and particularly.
First, the distributed converters built with several power electronics basic cells have been studied in the paper. The characteristics of distributed converters as well as the hardware designs and control methods are presented in detail. Particularly, the topology selection of the basic cell's power stage, the function design of distributed control, the interconnection of basic cells, the communication protocol design and the definition of the data transportation formats are investigated specifically. The distributed power converters play an important role in improving system reliability, shortening design cycle time and decreasing manufacturing cost. The proposed control design methods for distributed power converters are valuable for the further research.
Furthermore, the FPGA-based mixed-signal controller with asynchronous over sampling for switch mode converters is investigated in the paper. The proposed control architecture contains a FPGA, a DAC and a comparator, where the FPGA is a control processor that implements DPWM generation and a PID control algorithm. The DAC in conjunction with the comparator operates in two operational modes: one is a conversion mode performing successive approximation A/D conversion, and the other is a modulation mode providing an instant pulse-width modulator in the analog domain. The fast response of this mixed-signal control architecture makes itself close in dynamic behaviour to its analog counterpart. Furthermore, the proposed solution is also effective, since all components used are viable for power electronics integration. Its features and performance are sufficient to promote itself for implementation in many industrial digital control systems.
Besides, synchronization effects and performance degradation of the distributed inverters built with several power electronic basic cells controlled with different PWM strategies, are presented in this paper. The paper analyzes the synchronization performance when three kinds of synchronization errors (i.e., carrier synchronization error, reference synchronization error, and sampling synchronization error) exist by a three phase five-level cascaded inverter built with basic cells. All synchronization errors will lead to additional low order carrier sideband harmonics in the phase leg output voltage, and the THD of the phase leg output voltage increases as the synchronization error increases. This paper analyzes the impact of the three kinds of synchronization errors on the whole system performance systematically, as well as detailed synchronization implementation. Meanwhile, the harmonic energy distribution rules of the output voltage with the synchronization errors are derived from the comparisons of theoretical analysis, simulations and experimental results, as well as the conclusions on the performance degradation with the three kinds of errors. It is noticeable that the carrier synchronization error affects the output voltage performance more significantly than the reference synchronization error and the sampling error.
Further, the paper presents the performance degradation of a distributed inverter built with several basic cells using a SVPWM strategy. The transfer of the total harmonic energy of the line-to-line output voltage was explicitly analyzed using Fourier analysis and Matlab simulation, when a synchronization error or startup delay exists between two basic cells. The synchronization error leads to baseband low order haromincs, additional carrier sideband harmonics and odd multiples of carrier harmincs in the line-to-line output voltage. The derived conclusions on the harmonics distribution rules with the synchronization error are valuable for practical applications of SVPWM inverters built with basic modules using a distributed control scheme.
Finally, this paper focuses on the fault-tolerance potential of multilevel inverters with redundant switching states built with basic cells. The gate signals can be reconfigured according to the failure modes when some of the power devices fail. Balanced line-to-line voltage will be achieved with the proposed method when device failure occurs. Furthermore, the circuit structures can be the same as the general ones and the voltage stress of the devices does not increase. The solutions for PDPWM and PSPWM strategy are discussed in this paper but the concept can be extended to other carrier-based PWM strategies easily. And also the concept provides a new idea for the fault tolerant technology. The proposed method can easily be implemented since the reconfiguration of the PWM strategy can be implemented in software, without extra hardware requirements. Its perfect characteristics enable itself to be widely used in the multilevel converter applications.
The validity and accuracy of the theoretical analysis is proven by many simulations and experimental results in each chapter.
The work is sponsored by the National Nature Science Foundation of China (50777055).
引文
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