高速高精度电流舵数模转换器关键设计技术的研究与实现
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摘要
在有线或者无线通讯、视频信号处理、直接数字信号合成等应用领域,高速高精度数模转换器(DAC)的性能在很大程度上已经成为了整个系统性能的瓶颈。电流舵DAC由于其结构本征的高速特性和较好的驱动能力,被广泛应用在高速高精度领域。但是,由于影响电流舵DAC特性的因素很多,这给芯片的设计带来了一定的困难。本文主要针对电流舵DAC的设计难点,对设计关键技术进行了研究,并实现验证。
本文系统地分析了影响DAC特性的误差源,并对其所造成的性能下降进行了定性或定量的分析。这些误差源产生了包括静态的和动态的误差,分别在输入信号为低频和高频时占据主导。DAC中的静态误差主要为幅值误差,包括了与工艺相关的失配误差和与电流源位置相关的梯度性误差。动态误差主要有时序误差、时钟抖动、有限输出阻抗、输出波动效应、开关瞬态非线性等。这些动态误差源有的直接使DAC的输出产生谐波失真,有的会通过二阶效应的影响给DAC造成非线性失真。DAC的失真是这些误差所造成的失真量之和,通常这些误差源对DAC的影响会在不同频率范围下起主导作用。本文通过研究分析可以将各误差源对DAC动态特性影响的图谱归纳为：在直流至低输入频率时,静态幅值误差与有限输出电阻占据主要作用；随着输入频率的增大,时序误差对DAC动态性能的影响渐渐增强；当信号频率继续上升时,DAC动态的性能受输出波动效应以及开关瞬态非线性造成的二阶误差影响很大,其随信号频率的上升以-20dB每十倍频的速度下降；当信号频率很高时,DAC的有限输出阻抗所造成的失真占据了主导,使DAC的动态性能以-40dB每十倍频的速度下降。
本文基于对DAC中误差源的分析提出了相应的设计策略和方案：包括DAC的5+3+4分段策略；一种温度计译码快速求解方法和一种冗余行列译码方式；共中心梯度补偿的电流源阵列排布方案；提高DAC输出阻抗的有效方式；抑制输出波动效应的策略；适用于高速DAC的开关信号特征；一种适用于产生低摆幅开关信号的驱动电路的结构。
此外,本文还针对时域误差提出了一种动态校正技术,该校正技术采用时间差放大器(TDA)对被校正通路和参考通路的延迟差进行检测和放大,然后利用时数转换器(TDC)将放大的延迟差量化为数字量,并驱动被校正信号通路中的数字控制延迟线(DDL)对延迟误差进行补偿,从而使其与参考通路达到相对同步。该校正方法结构简单,校正系统中模拟电路较少,容易在版图中进行匹配提高校正精度。同时,校正电路本身的误差作为公共的误差使得其不会在各信号通路间引入额外的失配延迟误差。本文通过前、后仿真的验证表明了所提出的校正方法对时域误差进行校正的有效性。
根据所提出的设计方案,本文在TSMC0.18μm工艺下设计实现了一款12位400MS/s采样率的本征精度(Intrinsic Accuracy)电流舵DAC原型电路,该电路采用5+3+4的分段方式,核心电路面积为1.44mm2。经测试,该DAC的DNL和INL均优于±0.6LSB,表明在没有静态校正的情况下,DAC中电流源MOS管的尺寸选择合理,电流源阵列的布局方式有效。在DAC工作在400MS/s采样率时,其低输入频率下测得的SFDR为78.8dBc,98.5MHz输出频率下测得的SFDR为66dBc,奈奎斯特频率下测得的SFDR为50dBc,其70dBc的SFDR带宽约为70MHz。测试结果表明,作为一款本征精度的DAC原型电路,其具有良好的动态特性,能够在高速高精度条件下应用。
The performance of the high-speed and high resolution digital-to-analog converter (DAC) has become the bottleneck of the overall system in the applications such as wire or wireless communications, video signal processing, and direct digital signal synthesis. The current-steering DAC is widely used in high-speed and high-resolution fields because of its intrinsic high speed and driving capability. However, various factors influences the performance of the current-steering DAC, which makes the chip design difficult. This paper mainly focuses on the design difficulties and studies the key techniques which are implemented and validated.
This paper systematically analyzes the error sources which impact the DAC's performance, and further gives qualitative or quantitative analysis on the performance degradation caused by them. These error sources produce both static and dynamic errors which are dominant at low and high signal frequency, respectively. The mainly static error in the DAC is amplitude error, including mismatch error which is related to the technology process and gradient error which is related to the position of the current source. The dynamic errors are mainly timing error, clock jitter, finite output impedance, output variation effect and nonlinear switching transient. Some of them directly generate harmonic distortions on the DAC's output, and some can cause nonlinear distortion to the DAC through the second-order effects. The total distortion of the DAC is superposition of the distortion caused by these errors, and they are dominant in different frequency ranges. According to the analysis in this paper, the influences on the DAC caused by various error sources can be summarized as follows. The static amplitude error and finite output resistance play the major roles when the input varies from DC to low frequency. With the input frequency increasing, the timing error gradually affects the dynamic performance of the DAC. When the input frequency continues to increase, the errors from the output variation and its second-order effect caused by switching transient will influence more and more on the DAC's performance. It causes the dynamic performance degradation at a speed of-20dB per decade with the input frequency increasing. When the frequency goes up to very high, the finite output impedance of the DAC is dominant and will cause the performance decline at-40dB per decade.
Based on the studies on the DAC's error sources, this paper gives the corresponding design strategies and schemes including a5+3+4DAC segmentation strategy, a fast solution of the binary to thermometer decoding, a low-column redundant decoding method, a centroid arrangement with gradient compensation of the current sources in the layout array, a way of increasing the output impedance, a design strategy of the switching signal, and a switch driver which is suitable to generate the switching signal with low voltage swing.
In addition, a dynamic calibration technique for reducing the timing error is also presented in this paper. The proposed calibration technique employs a time difference amplifier (TDA) to detect and amplify the timing differences between the signal path to be correct and the reference signal path. Then, the timing error is digitalized by time-to-digital converter (TDC) and is further used to control the digital delay line (DDL) to compensate the timing error by adjusting the delay generated by the DDL The calibration technique has a simple structure with less analog circuits which are easy to match in the layout and good for increasing the calibration accuracy. Meanwhile, as the error caused by the calibration circuit is a common value, it will introduce less mismatches between different signal paths. The effectiveness of the proposed calibration technique is validated by the fore and post simulations in this paper.
According to the proposed design strategy, a12-bit400MS/s current-steering DAC with intrinsic accuracy is implemented in TSMC0.18μm technology. The DAC uses a5+3+4segmentation strategy. The chip core area is1.44mm2. The measured DNL and INL are both better than±0.6LSB, which validate the proper size selection of the current sources and the effectiveness of the arrangement strategy without any static calibration. When the DAC is operating at400MS/s, the measured SFDR is78.8 dBc at a low signal frequency and66dBc at a high input frequency of98.5MHz. The measured SFDR at Nyquist frequency drops down to50dBc, and the70dBc SFDR bandwidth is about70MHz. The measurement results show that the designed DAC is suitable for high-speed and high-resolution appications.
本文系统地分析了影响DAC特性的误差源,并对其所造成的性能下降进行了定性或定量的分析。这些误差源产生了包括静态的和动态的误差,分别在输入信号为低频和高频时占据主导。DAC中的静态误差主要为幅值误差,包括了与工艺相关的失配误差和与电流源位置相关的梯度性误差。动态误差主要有时序误差、时钟抖动、有限输出阻抗、输出波动效应、开关瞬态非线性等。这些动态误差源有的直接使DAC的输出产生谐波失真,有的会通过二阶效应的影响给DAC造成非线性失真。DAC的失真是这些误差所造成的失真量之和,通常这些误差源对DAC的影响会在不同频率范围下起主导作用。本文通过研究分析可以将各误差源对DAC动态特性影响的图谱归纳为：在直流至低输入频率时,静态幅值误差与有限输出电阻占据主要作用；随着输入频率的增大,时序误差对DAC动态性能的影响渐渐增强；当信号频率继续上升时,DAC动态的性能受输出波动效应以及开关瞬态非线性造成的二阶误差影响很大,其随信号频率的上升以-20dB每十倍频的速度下降；当信号频率很高时,DAC的有限输出阻抗所造成的失真占据了主导,使DAC的动态性能以-40dB每十倍频的速度下降。
本文基于对DAC中误差源的分析提出了相应的设计策略和方案：包括DAC的5+3+4分段策略；一种温度计译码快速求解方法和一种冗余行列译码方式；共中心梯度补偿的电流源阵列排布方案；提高DAC输出阻抗的有效方式；抑制输出波动效应的策略；适用于高速DAC的开关信号特征；一种适用于产生低摆幅开关信号的驱动电路的结构。
此外,本文还针对时域误差提出了一种动态校正技术,该校正技术采用时间差放大器(TDA)对被校正通路和参考通路的延迟差进行检测和放大,然后利用时数转换器(TDC)将放大的延迟差量化为数字量,并驱动被校正信号通路中的数字控制延迟线(DDL)对延迟误差进行补偿,从而使其与参考通路达到相对同步。该校正方法结构简单,校正系统中模拟电路较少,容易在版图中进行匹配提高校正精度。同时,校正电路本身的误差作为公共的误差使得其不会在各信号通路间引入额外的失配延迟误差。本文通过前、后仿真的验证表明了所提出的校正方法对时域误差进行校正的有效性。
根据所提出的设计方案,本文在TSMC0.18μm工艺下设计实现了一款12位400MS/s采样率的本征精度(Intrinsic Accuracy)电流舵DAC原型电路,该电路采用5+3+4的分段方式,核心电路面积为1.44mm2。经测试,该DAC的DNL和INL均优于±0.6LSB,表明在没有静态校正的情况下,DAC中电流源MOS管的尺寸选择合理,电流源阵列的布局方式有效。在DAC工作在400MS/s采样率时,其低输入频率下测得的SFDR为78.8dBc,98.5MHz输出频率下测得的SFDR为66dBc,奈奎斯特频率下测得的SFDR为50dBc,其70dBc的SFDR带宽约为70MHz。测试结果表明,作为一款本征精度的DAC原型电路,其具有良好的动态特性,能够在高速高精度条件下应用。
The performance of the high-speed and high resolution digital-to-analog converter (DAC) has become the bottleneck of the overall system in the applications such as wire or wireless communications, video signal processing, and direct digital signal synthesis. The current-steering DAC is widely used in high-speed and high-resolution fields because of its intrinsic high speed and driving capability. However, various factors influences the performance of the current-steering DAC, which makes the chip design difficult. This paper mainly focuses on the design difficulties and studies the key techniques which are implemented and validated.
This paper systematically analyzes the error sources which impact the DAC's performance, and further gives qualitative or quantitative analysis on the performance degradation caused by them. These error sources produce both static and dynamic errors which are dominant at low and high signal frequency, respectively. The mainly static error in the DAC is amplitude error, including mismatch error which is related to the technology process and gradient error which is related to the position of the current source. The dynamic errors are mainly timing error, clock jitter, finite output impedance, output variation effect and nonlinear switching transient. Some of them directly generate harmonic distortions on the DAC's output, and some can cause nonlinear distortion to the DAC through the second-order effects. The total distortion of the DAC is superposition of the distortion caused by these errors, and they are dominant in different frequency ranges. According to the analysis in this paper, the influences on the DAC caused by various error sources can be summarized as follows. The static amplitude error and finite output resistance play the major roles when the input varies from DC to low frequency. With the input frequency increasing, the timing error gradually affects the dynamic performance of the DAC. When the input frequency continues to increase, the errors from the output variation and its second-order effect caused by switching transient will influence more and more on the DAC's performance. It causes the dynamic performance degradation at a speed of-20dB per decade with the input frequency increasing. When the frequency goes up to very high, the finite output impedance of the DAC is dominant and will cause the performance decline at-40dB per decade.
Based on the studies on the DAC's error sources, this paper gives the corresponding design strategies and schemes including a5+3+4DAC segmentation strategy, a fast solution of the binary to thermometer decoding, a low-column redundant decoding method, a centroid arrangement with gradient compensation of the current sources in the layout array, a way of increasing the output impedance, a design strategy of the switching signal, and a switch driver which is suitable to generate the switching signal with low voltage swing.
In addition, a dynamic calibration technique for reducing the timing error is also presented in this paper. The proposed calibration technique employs a time difference amplifier (TDA) to detect and amplify the timing differences between the signal path to be correct and the reference signal path. Then, the timing error is digitalized by time-to-digital converter (TDC) and is further used to control the digital delay line (DDL) to compensate the timing error by adjusting the delay generated by the DDL The calibration technique has a simple structure with less analog circuits which are easy to match in the layout and good for increasing the calibration accuracy. Meanwhile, as the error caused by the calibration circuit is a common value, it will introduce less mismatches between different signal paths. The effectiveness of the proposed calibration technique is validated by the fore and post simulations in this paper.
According to the proposed design strategy, a12-bit400MS/s current-steering DAC with intrinsic accuracy is implemented in TSMC0.18μm technology. The DAC uses a5+3+4segmentation strategy. The chip core area is1.44mm2. The measured DNL and INL are both better than±0.6LSB, which validate the proper size selection of the current sources and the effectiveness of the arrangement strategy without any static calibration. When the DAC is operating at400MS/s, the measured SFDR is78.8 dBc at a low signal frequency and66dBc at a high input frequency of98.5MHz. The measured SFDR at Nyquist frequency drops down to50dBc, and the70dBc SFDR bandwidth is about70MHz. The measurement results show that the designed DAC is suitable for high-speed and high-resolution appications.
引文
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