8位高速电流舵型DAC电路研究与设计
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摘要
通过阅读大量文献,较为全面地概括了数模转换器(DAC)的国内外动态,介绍了DAC的基本原理和结构,分析了DAC主要误差来源和模型,对几种典型的DAC结构进行了详细的分析,并设计出一个8位高速DAC。
通过对温度码和二进制码这两种不同DAC结构的讨论,针对高速要求,将本次设计结构确定为温度计码电流舵DAC;并进行了原理分析和电路设计以及版图设计,建立了完整的电流型DAC转换器基本子电路单元和仿真方案。
仿真结果显示,DAC的转换速率到达500 MSPS,积分非线性误差和微分非线性误差均小于0.5LSB。在奈奎斯特(Nyquist)频率下,无杂散动态范围(SFDR)达68dB,总谐波失真(THD)达-61dB。在保证转换精度前提下,采用温度计码电流舵结构可以明显提高DAC采样速率和动态性能。
在电路结构上,提出了单位电流源中的开关差分控制信号交叉点的最优值,并在差分开关上叠加一对常开PMOS管,有效减小了输出毛刺面积,改善了动态性能。
讨论了有关DAC的一些基本设计思路和手段,并针对分段式结构高速DAC的一些常见问题,进行了理论分析、数学建模和模拟仿真。给出了实际的电流源、开关、偏置、带隙基准等单元子电路的设计结果以及仿真结果。
A general introduction on Digital-Analog Converter study of domestic and aboard is presented. DAC principle and structures, and different converters such as current converting and voltage converting are analized.A 8-bit high speed DAC is designed. Based on the study of binary weighted DAC and thermometer-coded DAC, a thermometer-coded current-steering DAC is adopted. The principle, sub-circuit and layout of this DAC are also presented. The converter has the thermometer-coded architecture.
This architecture implements the 8-bit DAC and achieves a good performance of dynamic character. This sample rate of this converter can be up to 500Msps. The SFDR and THD are up to 68dB and -61dB. The INL and DNL are smaller than 0.5LSB.
The Structure of the converter is improved based on traditional one so that the area of glitch is reduced sharply and the dynamic character is improved.
Some of the basic design theory and technology are presented. The basic cell architectures implemented in DAC are also presented. To improve the DAC, some of the cell architectures have to be designed carefully. The details of those cells are described. The actual circuit of current source, switch,bias and bandgap is presented.
通过对温度码和二进制码这两种不同DAC结构的讨论,针对高速要求,将本次设计结构确定为温度计码电流舵DAC;并进行了原理分析和电路设计以及版图设计,建立了完整的电流型DAC转换器基本子电路单元和仿真方案。
仿真结果显示,DAC的转换速率到达500 MSPS,积分非线性误差和微分非线性误差均小于0.5LSB。在奈奎斯特(Nyquist)频率下,无杂散动态范围(SFDR)达68dB,总谐波失真(THD)达-61dB。在保证转换精度前提下,采用温度计码电流舵结构可以明显提高DAC采样速率和动态性能。
在电路结构上,提出了单位电流源中的开关差分控制信号交叉点的最优值,并在差分开关上叠加一对常开PMOS管,有效减小了输出毛刺面积,改善了动态性能。
讨论了有关DAC的一些基本设计思路和手段,并针对分段式结构高速DAC的一些常见问题,进行了理论分析、数学建模和模拟仿真。给出了实际的电流源、开关、偏置、带隙基准等单元子电路的设计结果以及仿真结果。
A general introduction on Digital-Analog Converter study of domestic and aboard is presented. DAC principle and structures, and different converters such as current converting and voltage converting are analized.A 8-bit high speed DAC is designed. Based on the study of binary weighted DAC and thermometer-coded DAC, a thermometer-coded current-steering DAC is adopted. The principle, sub-circuit and layout of this DAC are also presented. The converter has the thermometer-coded architecture.
This architecture implements the 8-bit DAC and achieves a good performance of dynamic character. This sample rate of this converter can be up to 500Msps. The SFDR and THD are up to 68dB and -61dB. The INL and DNL are smaller than 0.5LSB.
The Structure of the converter is improved based on traditional one so that the area of glitch is reduced sharply and the dynamic character is improved.
Some of the basic design theory and technology are presented. The basic cell architectures implemented in DAC are also presented. To improve the DAC, some of the cell architectures have to be designed carefully. The details of those cells are described. The actual circuit of current source, switch,bias and bandgap is presented.
引文
[1] Sam Blackman.A low Power, 8-bit, 200MHz Digital-to-Analog Converter:[doctor degree paper ], University of California, California, Berkerly: 1999.
[2] 詹桦.高速数模转换器的设计:[硕士学位论文],浙江大学,杭州:2003.
[3] 徐振英.数模转换器应用技术.第二版.北京:科学出版社,2000:77.
[4] 任雪刚.12 位 DAC 电路研究与设计:[硕士学位论文],电子科技大学,成都:2002.
[5] 陈震初.发展我国数据转换电路的几点建议.微电子学,1998,28(4):233-235.
[6] 许居衍,徐世六.关于 A/D 与 D/A 转换器发展动向的一些思考.微电子学,1998,28(4):217-223.
[7] 于继洲.集成 A/D 和 D/A 转换器应用技术.第一版.北京:国防工业出版社,1989:85-86.
[8] 茹纪军.高速电流舵型 CMOS 数模转换器的研究与设计:[硕士学位论文],电子科技大学,成都: 2005.
[9] 赵保经,蒋建飞.大规模集成数-模和模-数转换器设计原理.第一版.北京:科学出版社,1996:112-113.
[10] 何艳红.8 位高速 D/A 转换器设计研究:[硕士学位论文],电子科技大学,成都:2004.
[11] Philip E.Allen, Douglas R.Holberg.CMOS 模拟集成电路设计.冯军,李智群译.第二版.北京:电子工业出版社,2002:244-246.
[12] Jose Bastos, Augusto M. Marques, Michel S.J. Steyaert, and Willy Sansen.A 12-bit intrinsic accuracy high-speed CMOS DAC.Solid-State Circuits, 1998, 33(12): 13-16.
[13] H. Kohno, Y Nakamura, A.Kondo, H.Amishiro, T.Miki, and K.Okada.A 350MS/s 3.3V 8-bit CMOS D/A converter.IEEE 1995 Custom Integrated Circuits Conf.(CICC), vol. 1: 137-141.
[14] Hassanzadeh, M.R.Talebzadeh, J.Shoaei, o.a high-speed, current-steering digital-to-analog converter in 0.6μm cmos.Electronic circuit and systems, 2002, 9th international conference, vol. 1:9-12
[15] Albiol, M.Gonzalez, J.L.Alarcon, E.Improved current source sizing for high-speed high-accuracy current-steering d/a converter.Circuit and systems, 2003.17(10): 837-839
[16] Yonghua cong, Geiger, R.L.Formulation of INL and DNL jield estimation in current-steeringd/a converter.ISCAS 2002 IEEE international symposium on, 3:1959-1961.
[17] 熊险峰.高速高精度十二位 D/A 转换器的研究与设计:[硕士学位论文],湖南大学,长沙:2003.
[18] Tao Shui, Schreier, R.Hudson, F.Mismatch shaping for a current-mode multibit delta-sigma DAC, Solid-State Circuits, IEEE Journal, 1999, 34(3): 331 – 338.
[19] 江金光,何恰刚,吴杰.12 位 80MHz 采样率具有梯度误差补偿的 CMOS 电流舵 D/A 转换器实现.半导体学报.2003,24(12):1324-1329.
[20] 毕查德.拉扎维.模拟 CMOS 集成电路设计.陈贵灿,程军、张瑞智等译.第一版.西安:西安交通大学出版社,2003:319-320.
[21] 杨勇.高速低功耗数模转换器的研究和设计:[硕士学位论文],电子科技大学,成都:2004.
[22] 王毓银.脉冲与数字电路.第二版.北京:高等教育出版社,1992:349-362.
[23] 朱樟明,杨银堂,柴常春等.一种基于 0.35μm CMOS 工艺的 14 位 100MSPS DAC 设计.固体电子学研究与进展.2004,24(2):191-195.
[2] 詹桦.高速数模转换器的设计:[硕士学位论文],浙江大学,杭州:2003.
[3] 徐振英.数模转换器应用技术.第二版.北京:科学出版社,2000:77.
[4] 任雪刚.12 位 DAC 电路研究与设计:[硕士学位论文],电子科技大学,成都:2002.
[5] 陈震初.发展我国数据转换电路的几点建议.微电子学,1998,28(4):233-235.
[6] 许居衍,徐世六.关于 A/D 与 D/A 转换器发展动向的一些思考.微电子学,1998,28(4):217-223.
[7] 于继洲.集成 A/D 和 D/A 转换器应用技术.第一版.北京:国防工业出版社,1989:85-86.
[8] 茹纪军.高速电流舵型 CMOS 数模转换器的研究与设计:[硕士学位论文],电子科技大学,成都: 2005.
[9] 赵保经,蒋建飞.大规模集成数-模和模-数转换器设计原理.第一版.北京:科学出版社,1996:112-113.
[10] 何艳红.8 位高速 D/A 转换器设计研究:[硕士学位论文],电子科技大学,成都:2004.
[11] Philip E.Allen, Douglas R.Holberg.CMOS 模拟集成电路设计.冯军,李智群译.第二版.北京:电子工业出版社,2002:244-246.
[12] Jose Bastos, Augusto M. Marques, Michel S.J. Steyaert, and Willy Sansen.A 12-bit intrinsic accuracy high-speed CMOS DAC.Solid-State Circuits, 1998, 33(12): 13-16.
[13] H. Kohno, Y Nakamura, A.Kondo, H.Amishiro, T.Miki, and K.Okada.A 350MS/s 3.3V 8-bit CMOS D/A converter.IEEE 1995 Custom Integrated Circuits Conf.(CICC), vol. 1: 137-141.
[14] Hassanzadeh, M.R.Talebzadeh, J.Shoaei, o.a high-speed, current-steering digital-to-analog converter in 0.6μm cmos.Electronic circuit and systems, 2002, 9th international conference, vol. 1:9-12
[15] Albiol, M.Gonzalez, J.L.Alarcon, E.Improved current source sizing for high-speed high-accuracy current-steering d/a converter.Circuit and systems, 2003.17(10): 837-839
[16] Yonghua cong, Geiger, R.L.Formulation of INL and DNL jield estimation in current-steeringd/a converter.ISCAS 2002 IEEE international symposium on, 3:1959-1961.
[17] 熊险峰.高速高精度十二位 D/A 转换器的研究与设计:[硕士学位论文],湖南大学,长沙:2003.
[18] Tao Shui, Schreier, R.Hudson, F.Mismatch shaping for a current-mode multibit delta-sigma DAC, Solid-State Circuits, IEEE Journal, 1999, 34(3): 331 – 338.
[19] 江金光,何恰刚,吴杰.12 位 80MHz 采样率具有梯度误差补偿的 CMOS 电流舵 D/A 转换器实现.半导体学报.2003,24(12):1324-1329.
[20] 毕查德.拉扎维.模拟 CMOS 集成电路设计.陈贵灿,程军、张瑞智等译.第一版.西安:西安交通大学出版社,2003:319-320.
[21] 杨勇.高速低功耗数模转换器的研究和设计:[硕士学位论文],电子科技大学,成都:2004.
[22] 王毓银.脉冲与数字电路.第二版.北京:高等教育出版社,1992:349-362.
[23] 朱樟明,杨银堂,柴常春等.一种基于 0.35μm CMOS 工艺的 14 位 100MSPS DAC 设计.固体电子学研究与进展.2004,24(2):191-195.