CMOS片上ESD保护电路设计研究
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摘要
随着半导体制造工艺的飞速进步,集成电路工艺的不断更新换代,特征尺寸沿着摩尔定律不断缩小,各种微电子器件的集成度大为提高,随之而来的就是芯片可靠性方面的问题。在集成电路的可靠性设计中,其中最常见也是首先要考虑的便是静电放电保护电路的设计。
静电放电保护电路的设计涉及包括半导体物理、半导体器件、电路设计、集成电路工艺学、静电放电模型、传输线理论、热力学分布等方面的知识,还涉及到电路仿真、失效分析等技术。这些知识和技术内容较杂,分布面又很广,对于集成电路工程师来要完善的掌握也是有一定困难的。
本文对静电放电模型、集成电路的ESD失效机制、失效分析技术、静电保护电路设计进行了研究。对于CMOS数字、模拟、射频管脚和电源ESD钳位电路,针对已有电路的不足提出了几点改进的方法,给出了通过失效分析进行改进的过程,最后通过ESD测试结果验证了它们的有效性。
本文主要工作和特色如下:
1、对常用的CMOS数字输入/输出管脚、模拟管脚和射频管脚的ESD电路进行研究,通过在实际芯片实现后ESD测试中暴露出来的问题,运用失效分析工具进行分析,然后灵活利用半浮栅、镇流、衬底耦合等技术提出了对电路的改良,并且详细分析了版图设计中的各种细节问题,最后通过ESD测试证明这些改进可以在静电放电时对芯片内部电路进行有效的保护。
2、通过对现有电源钳位ESD保护电路的电路结构、工作原理进行分析和研究,讨论了它们的优点和存在的问题,提出了一种改进的电源动态侦测ESD保护电路。
3、对三种常见的CMOS集成电路电源总线的ESD保护结构进行了研究,分析了它们的设计依据、总线结构和工作原理,针对它们存在的问题,提出了一种改进的进行ESD保护的电源总线拓扑结构。
4、运用改进的电源动态侦测ESD保护电路和电源总线拓扑结构,完成了全芯片的电源系统设计,运用HSPICE仿真验证了该结构的正确性,并通过ESD测试证实了其有效性。
每一代集成电路制造工艺的更新都对ESD设计提出了新的更高的要求,而反过来ESD保护电路的设计也推动这新工艺、新技术的不断向前发展。在今天的集成电路设计中,ESD保护电路设计已经成为了集成电路可靠性设计不可或缺的一个重要环节。在这种情况下,ESD保护电路的研究也对我国集成电路设计水平的提高有着重大的意义。
With the rapid progress in semiconductor manufacturing processes, the continuous upgrading of technology in integrated circuits, feature size shrinking along the Moore's Law, a variety of integration of microelectronic devices greatly increased, the ensuing problems is the reliability of the chip. In the reliability in IC design, one of the most common and first thing to consider is the electrostatic discharge (ESD) protection circuit design.
ESD protection circuit design involves including semiconductor physics, semiconductor devices, circuit design, IC-technology, electrostatic discharge model, transmission line theory, thermodynamics distribution of knowledge, but also to the circuit simulation, failure analysis techniques. Such knowledge and technical contains much, distributing broad, it is difficult for integrated circuit engineers to perfect master them all.
In this paper, we focused on ESD model, IC ESD failure mechanisms, failure analysis techniques, and ESD protection circuit design. For CMOS digital, analog, RF pin and power supply ESD clamp circuit for the circuit has been put forward through the failure analysis process, and the final adoption of ESD test results confirm their effectiveness.
The work features in this paper are as follows:
1. For commonly used CMOS digital input / output pins, analog and RF pins pin ESD circuit study, after the ESD testing exposed problems, the use of failure analysis tools for analysis, and flexible use of semi-floating gate, substrate coupling techniques proposed improvements to the circuit, and a detailed analysis of the layout of the various details, the final test proved that these improvements can afford effectively protection to the internal circuitry of the chip through electrostatic discharge.
2. By analyzing and researching the existing power clamp ESD protection circuit of the circuit structure, working principle, discussing their advantages and problems, and proposed an improved power dynamic detection ESD protection circuits.
3. The three kinds of common CMOS IC power bus ESD protection structures have been studied to analyze their design basis, bus structure and working principle, then put forward an improved ESD protection for power bus topology.
4. Using the improved detection power dynamics ESD protection circuit and power bus topology, a full-chip power supply system design is completed, using HSPICE simulations verify the correctness of the structure, and ESD test verified its effectiveness.
Each generation of IC manufacturing processes make a new and higher requirement to ESD protection design, but in turn, ESD protection circuit is also designed to promote the new technology’s continuous moving forward. In today's integrated circuit design, ESD protection circuit design has become an integral important part of integrated circuit reliability design. In such cases, ESD protection circuit study has great significance of raising the level of China's IC design.
静电放电保护电路的设计涉及包括半导体物理、半导体器件、电路设计、集成电路工艺学、静电放电模型、传输线理论、热力学分布等方面的知识,还涉及到电路仿真、失效分析等技术。这些知识和技术内容较杂,分布面又很广,对于集成电路工程师来要完善的掌握也是有一定困难的。
本文对静电放电模型、集成电路的ESD失效机制、失效分析技术、静电保护电路设计进行了研究。对于CMOS数字、模拟、射频管脚和电源ESD钳位电路,针对已有电路的不足提出了几点改进的方法,给出了通过失效分析进行改进的过程,最后通过ESD测试结果验证了它们的有效性。
本文主要工作和特色如下:
1、对常用的CMOS数字输入/输出管脚、模拟管脚和射频管脚的ESD电路进行研究,通过在实际芯片实现后ESD测试中暴露出来的问题,运用失效分析工具进行分析,然后灵活利用半浮栅、镇流、衬底耦合等技术提出了对电路的改良,并且详细分析了版图设计中的各种细节问题,最后通过ESD测试证明这些改进可以在静电放电时对芯片内部电路进行有效的保护。
2、通过对现有电源钳位ESD保护电路的电路结构、工作原理进行分析和研究,讨论了它们的优点和存在的问题,提出了一种改进的电源动态侦测ESD保护电路。
3、对三种常见的CMOS集成电路电源总线的ESD保护结构进行了研究,分析了它们的设计依据、总线结构和工作原理,针对它们存在的问题,提出了一种改进的进行ESD保护的电源总线拓扑结构。
4、运用改进的电源动态侦测ESD保护电路和电源总线拓扑结构,完成了全芯片的电源系统设计,运用HSPICE仿真验证了该结构的正确性,并通过ESD测试证实了其有效性。
每一代集成电路制造工艺的更新都对ESD设计提出了新的更高的要求,而反过来ESD保护电路的设计也推动这新工艺、新技术的不断向前发展。在今天的集成电路设计中,ESD保护电路设计已经成为了集成电路可靠性设计不可或缺的一个重要环节。在这种情况下,ESD保护电路的研究也对我国集成电路设计水平的提高有着重大的意义。
With the rapid progress in semiconductor manufacturing processes, the continuous upgrading of technology in integrated circuits, feature size shrinking along the Moore's Law, a variety of integration of microelectronic devices greatly increased, the ensuing problems is the reliability of the chip. In the reliability in IC design, one of the most common and first thing to consider is the electrostatic discharge (ESD) protection circuit design.
ESD protection circuit design involves including semiconductor physics, semiconductor devices, circuit design, IC-technology, electrostatic discharge model, transmission line theory, thermodynamics distribution of knowledge, but also to the circuit simulation, failure analysis techniques. Such knowledge and technical contains much, distributing broad, it is difficult for integrated circuit engineers to perfect master them all.
In this paper, we focused on ESD model, IC ESD failure mechanisms, failure analysis techniques, and ESD protection circuit design. For CMOS digital, analog, RF pin and power supply ESD clamp circuit for the circuit has been put forward through the failure analysis process, and the final adoption of ESD test results confirm their effectiveness.
The work features in this paper are as follows:
1. For commonly used CMOS digital input / output pins, analog and RF pins pin ESD circuit study, after the ESD testing exposed problems, the use of failure analysis tools for analysis, and flexible use of semi-floating gate, substrate coupling techniques proposed improvements to the circuit, and a detailed analysis of the layout of the various details, the final test proved that these improvements can afford effectively protection to the internal circuitry of the chip through electrostatic discharge.
2. By analyzing and researching the existing power clamp ESD protection circuit of the circuit structure, working principle, discussing their advantages and problems, and proposed an improved power dynamic detection ESD protection circuits.
3. The three kinds of common CMOS IC power bus ESD protection structures have been studied to analyze their design basis, bus structure and working principle, then put forward an improved ESD protection for power bus topology.
4. Using the improved detection power dynamics ESD protection circuit and power bus topology, a full-chip power supply system design is completed, using HSPICE simulations verify the correctness of the structure, and ESD test verified its effectiveness.
Each generation of IC manufacturing processes make a new and higher requirement to ESD protection design, but in turn, ESD protection circuit is also designed to promote the new technology’s continuous moving forward. In today's integrated circuit design, ESD protection circuit design has become an integral important part of integrated circuit reliability design. In such cases, ESD protection circuit study has great significance of raising the level of China's IC design.
引文
[1] Ajith Amerasekera, Charvaka Duvvury. ESD in Silicon Integrated Circuits [M]. Chichester: John Wiley & Sons Ltd, 1995.
[2]国际电工委员会. IEC61000-4-2
[3]美国军用标准. Mil-std-1686c
[4]常昌远,钟锐译.ESD电路与器件[M].电子工业出版社, 2008.
[5] D.C. Wunsch and R.R. Bell. Determination of threshold voltage levels of semiconductor diodes and transistors due tu pulsed voltages. IEEE Transactions. On Nuclear Science 1968; NS-15 (6): 244-259
[6] W.D. Brown. Semiconductor device degradation by high amplitude current pulses. IEEE Transactions On Nuclear Science 1972; NS-19:68-75.
[7] E.N. Enlow. Determining an emitter-base failure threshold density of npn transistors. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1981; 145-150.
[8] D.R. Alexander and E.W. Enlow. Predicting lower bounds on failure power distributions of silicon npn transistors. IEEE Transactions On Nuclear Science 1981; NS-28 (6).
[9] D. Pierce and R. Mason. A Probabilistic estimator for bounding transistor emitter-base junction transient-induced failures. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1982; 82-90.
[10] M. Ash. Semiconductor junction non-linear failure power thresholds: Wunsch-Bell revisited. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1983; 122-127.
[11] R. Renninger, M.C. Jon, D. Lin, T. Diep and T.L. Welser. A field induced charged-device model simulator. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1989; 59-72.
[12] T. Polgreen and P. Chatterjee. Improving the ESD failure threshold of silicided nMOS output transistors by ensuring uniform current flow. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1989; 167-174.
[13] S. Voldman, V. Gross, M. Hargrove, J. Never, J. Slinkman, M. O’Boyle, T. Scott and J. Delecki. Shallow trench isolation double-diode electrostatic discharge circuit and interaction with DRAM circuitry. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1992; 277-288.
[14] D.L. Lin. ESD sensitivity and VLSI technology trends: Thermal breakdown and dielectric breakdown. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) symposium, 1993; 73-82.
[15] S. Voldman and V. Gross. Scaling, optimization, and desigh considerations of electrostatic discharge protection circuits in CMOS technology. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1993; 251-260.
[16] ESD Association S5.1, 1993. HBM-ESD Sensitivity Testing: Human body model (HBM)-Component level.
[17] H. Gieser and M. Haunschild. Very-fast transmission line pulsing of integrated structures and the charged device model. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1993; 85-94.
[18] ESD Association S5.2, 1994. MM-ESD Sensitivity Testing: Machine model (MM)-Component level.
[19] S. Voldman. ESD robustness and scaling implications of aluminum and copper interconnects in advanced semiconductor technology. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1997; 316-329.
[20] ESD Association S5.3, 1997. CDM-ESD Sensitivity Testing: Charged device model (CDM)-Component level.
[21] S. Voldman, P. Juliano, R.Johnson, N. Schmidt, A. Joseph, S. Furkay, E. Rosenbaum, J. Dunn, D.L. Harame and B. Meyerson. Electrostatic discharge and high current pulse characterization of epitaxial base silicon germanium heterojunction bipolar transistors. Proceedings of the International Reliability Physics Symposium (IRPS), 2000; 310-316.
[22] ESD Association. ESD SP 5.5-2004: Standard practice for electrostatic discharge sensitivity testing-transmission line pulse(TLP) component level.
[23]刘尚合,武占成.静电放电及危害防护[M].北京邮电大学出版社,2004.
[24] Speakman T S. A model for the failure of bipolar silicon integrated circuits subjected to electrostatic discharge. International Reliability Physics Symposium Proceedings, 1974
[25] Hyatt H et al. A closer look at the ESD event. EOS/ESD Symposium Proceedings. 1981
[26] Calcavecchio R J, Pratt D J. A standard test to determine the susceptibility of a machine to electrostatic discharge. Proceedings of the 1986 IEEE EMC, 475～481
[27] Maas J S, Pratt D J, Boxleitner W. Furniture ESD - The forgotten parameter in ESD testing. IEEE EMC 1991, 248～252
[28]侯志刚,许新新,张宪敏等.超深亚微米器件的失效机理及其可靠性研究[J].可靠性分析与研究.2005.12:39~42
[29]梁惠来,张国强. IC失效分析方法的研究[J].电子测量技术. 2006.29(4): 168~169.
[30] http://www.perfictlab.com/pages/P.Lab%20services-FIB.html
[31]李兴鸿,王勇,赵春荣.电测试在集成电路失效分析中的应用[J].中国集成电路. 2003(52):52~53
[32]费轻宇.VLSI失效分析技术研究进展[J].电子产品可靠性与环境试验. 2005(12):60~64
[33] D. Krakauer, K. Mistry and H. Partovi. Circuit interactions during electrostatic discharge. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1994: 113-119.
[34]薛忠杰. CMOS VLSI ESD保护电路设计技术[J].微电子技术. 27(2): 46~51, 1999.
[35]杜鸣,郝跃,朱志炜. CMOS工艺中GG_NMOS结构ESD保护电路设计[J].半导体学报. 26(8):1619~1622, 2005.
[36] Ma Xiaohui. On-chip ESD protection for multiple Vdd & Gnd [J]. Semiconductor Technology, 26(10):62~64, 2001.
[37]李岷.亚微米CMOS集成电路静电保护结构设计研究.硕士论文,上海交通大学,2002.
[38]崔强.集成电路中的ESD防护研究.硕士论文,浙江大学,2008.
[2]国际电工委员会. IEC61000-4-2
[3]美国军用标准. Mil-std-1686c
[4]常昌远,钟锐译.ESD电路与器件[M].电子工业出版社, 2008.
[5] D.C. Wunsch and R.R. Bell. Determination of threshold voltage levels of semiconductor diodes and transistors due tu pulsed voltages. IEEE Transactions. On Nuclear Science 1968; NS-15 (6): 244-259
[6] W.D. Brown. Semiconductor device degradation by high amplitude current pulses. IEEE Transactions On Nuclear Science 1972; NS-19:68-75.
[7] E.N. Enlow. Determining an emitter-base failure threshold density of npn transistors. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1981; 145-150.
[8] D.R. Alexander and E.W. Enlow. Predicting lower bounds on failure power distributions of silicon npn transistors. IEEE Transactions On Nuclear Science 1981; NS-28 (6).
[9] D. Pierce and R. Mason. A Probabilistic estimator for bounding transistor emitter-base junction transient-induced failures. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1982; 82-90.
[10] M. Ash. Semiconductor junction non-linear failure power thresholds: Wunsch-Bell revisited. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1983; 122-127.
[11] R. Renninger, M.C. Jon, D. Lin, T. Diep and T.L. Welser. A field induced charged-device model simulator. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1989; 59-72.
[12] T. Polgreen and P. Chatterjee. Improving the ESD failure threshold of silicided nMOS output transistors by ensuring uniform current flow. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1989; 167-174.
[13] S. Voldman, V. Gross, M. Hargrove, J. Never, J. Slinkman, M. O’Boyle, T. Scott and J. Delecki. Shallow trench isolation double-diode electrostatic discharge circuit and interaction with DRAM circuitry. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1992; 277-288.
[14] D.L. Lin. ESD sensitivity and VLSI technology trends: Thermal breakdown and dielectric breakdown. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) symposium, 1993; 73-82.
[15] S. Voldman and V. Gross. Scaling, optimization, and desigh considerations of electrostatic discharge protection circuits in CMOS technology. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1993; 251-260.
[16] ESD Association S5.1, 1993. HBM-ESD Sensitivity Testing: Human body model (HBM)-Component level.
[17] H. Gieser and M. Haunschild. Very-fast transmission line pulsing of integrated structures and the charged device model. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1993; 85-94.
[18] ESD Association S5.2, 1994. MM-ESD Sensitivity Testing: Machine model (MM)-Component level.
[19] S. Voldman. ESD robustness and scaling implications of aluminum and copper interconnects in advanced semiconductor technology. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1997; 316-329.
[20] ESD Association S5.3, 1997. CDM-ESD Sensitivity Testing: Charged device model (CDM)-Component level.
[21] S. Voldman, P. Juliano, R.Johnson, N. Schmidt, A. Joseph, S. Furkay, E. Rosenbaum, J. Dunn, D.L. Harame and B. Meyerson. Electrostatic discharge and high current pulse characterization of epitaxial base silicon germanium heterojunction bipolar transistors. Proceedings of the International Reliability Physics Symposium (IRPS), 2000; 310-316.
[22] ESD Association. ESD SP 5.5-2004: Standard practice for electrostatic discharge sensitivity testing-transmission line pulse(TLP) component level.
[23]刘尚合,武占成.静电放电及危害防护[M].北京邮电大学出版社,2004.
[24] Speakman T S. A model for the failure of bipolar silicon integrated circuits subjected to electrostatic discharge. International Reliability Physics Symposium Proceedings, 1974
[25] Hyatt H et al. A closer look at the ESD event. EOS/ESD Symposium Proceedings. 1981
[26] Calcavecchio R J, Pratt D J. A standard test to determine the susceptibility of a machine to electrostatic discharge. Proceedings of the 1986 IEEE EMC, 475～481
[27] Maas J S, Pratt D J, Boxleitner W. Furniture ESD - The forgotten parameter in ESD testing. IEEE EMC 1991, 248～252
[28]侯志刚,许新新,张宪敏等.超深亚微米器件的失效机理及其可靠性研究[J].可靠性分析与研究.2005.12:39~42
[29]梁惠来,张国强. IC失效分析方法的研究[J].电子测量技术. 2006.29(4): 168~169.
[30] http://www.perfictlab.com/pages/P.Lab%20services-FIB.html
[31]李兴鸿,王勇,赵春荣.电测试在集成电路失效分析中的应用[J].中国集成电路. 2003(52):52~53
[32]费轻宇.VLSI失效分析技术研究进展[J].电子产品可靠性与环境试验. 2005(12):60~64
[33] D. Krakauer, K. Mistry and H. Partovi. Circuit interactions during electrostatic discharge. Proceedings of the Electrostatic Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1994: 113-119.
[34]薛忠杰. CMOS VLSI ESD保护电路设计技术[J].微电子技术. 27(2): 46~51, 1999.
[35]杜鸣,郝跃,朱志炜. CMOS工艺中GG_NMOS结构ESD保护电路设计[J].半导体学报. 26(8):1619~1622, 2005.
[36] Ma Xiaohui. On-chip ESD protection for multiple Vdd & Gnd [J]. Semiconductor Technology, 26(10):62~64, 2001.
[37]李岷.亚微米CMOS集成电路静电保护结构设计研究.硕士论文,上海交通大学,2002.
[38]崔强.集成电路中的ESD防护研究.硕士论文,浙江大学,2008.