100-MS/s可重构流水线结构模数转换器的研究
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摘要
随着集成电路技术和工艺的飞速发展,集成电路已经进入片上系统阶段(SoC)。片上系统需要在单个硅片上同时实现模拟电路和数字电路,因此,设计出基于标准CMOS工艺的高性能模数转换器就变得非常重要。无线通信、图像处理、视频技术等的快速发展和广泛应用,进一步推动模数转换器向着高速、高分辨率、低功耗的方向发展。而流水线结构模数转换器则以其高分辨率、高精度以及在速度和功耗之间的很好折衷而得到了广泛的应用。本文就是基于无线局域网中对多标准无线收发器的需要,来对一种100MHz采样频率的可重构流水线结构模数转换器进行研究。
本文首先在系统结构上选取了在较高采样频率下整个电路功耗较低的1.5位/级结构,这不仅可以简化每级流水线中SubADC和SubDAC的设计,还可以通过数字校正电路来消除一定范围内的比较器失调;针对传统结构中分辨率位数固定以及最后一级流水线的数字输出不能进行校正的不足,设计了一种可重构流水线结构,该结构前九级采用相同的结构,并通过一个重构配置控制电路来使这九级电路有选择的工作,从而实现6~10位不同的分辨率位数,而第十级则为一个精度不高的比较器,来对第九级的数字输出进行校正。其次分析了10位1.5位/级流水线模数转换器中的数字校正算法,并针对其不能判断输入信号是否超出模数转换器量化范围的不足,设计产生了一个溢出判断信号从而使模数转换器具有了溢出判断功能。最后分析了MOS采样保持电路中的各种非理想因素,并针对这些因素在设计中采用了CMOS全差分采样保持电路,它不仅可以消除时钟馈通等共模信号的影响,还可以消除由采样开关带来的与输入信号相关的电荷注入效应;此外还针对采样开关存在的非线性,设计了一种高线性度的bootstrapped CMOS采样开关电路。
在Simulink下对整个系统及数字校正电路进行了行为级仿真,并基于SMIC 0.18um CMOS数模混合工艺模型采用Hspice软件对开关电路进行了仿真,仿真结果表明:所设计的流水线结构模数转换器能够实现6~10位不同的分辨率位数,并可以有效的校正每一级流水线中比较器存在的失调;溢出判断信号OF能正确的判断输入信号是否超出模数转换器的量化范围;在输入信号为24.4140625MHz(1V～2V)的正弦信号时,测到的bootstrapped CMOS开关电路的无杂散动态范围(SFDR)约为80dB,同一般的CMOS传输门开关电路相比,将非线性失真降低了约20dB。
With the rapid development of semi-conductor technology, integrated circuit has stepped into a new era of system on chip (SoC). SoC requires the integration of analog circuits and digital circuits on a single chip. So it is very important to design a high performance A/D converter, which is based on standard CMOS technology. With the explosive development and wide use of wireless communication, imaging process and video process, A/D converter also trends to be high-speed high-resolution and low-power dissipation. Pipelined A/D converter has an excellent combination of high-resolution and high-precision; at the same time, it has a good trade-off between speed and power dissipation, so it is widely used. For the requirement of multi-standard transceiver of wireless LAN, this thesis will research for a 100-MHz sample/s reconfigurable pipelined A/D converter.
firstly, this thesis chooses a 1.5 bit/stage pipelined A/D converter, whose power dissipation is very low at high sampling frequency. This structure not only could make the design of SubADC and SubDAC simply, but also could eliminate the offset of comparators by digital error correction circuit. Aiming at the fixed resolution and the ninth stage’s digital output couldn’t be corrected of the traditional 1.5 bit/stage pipelined structure, this thesis designs a reconfigurable pipelined A/D converter. In the reconfigurable pipelined structure, the first nine stages adopt the same structure, some of which are chosed to operate to achieve the different resolution (6~10-bit) by the reconfigurable control circuit, and the tenth stage just is a simple comparator, which is used to correct the digital output of the ninth stage. Secondly, this thesis analyzes the digital error correction theory of 10-bit 1.5 bit/stage pipelined A/D converter which couldn’t detect the input signal’s overflow. Then designs circuit and obtains an overflow detect signal which could detect whether the input signal is overflow. Finally this thesis analyzes the non-ideal characteristics of MOS sample-and-hold circuit. To reduce these non-ideal characteristics, this thesis adopts a CMOS full differential sample-and-hold circuit, which could reduce the effect of clock feedthrough and channel charge injection. Besides, in order to improve linearity of sample switch, designs a bootstrapped CMOS switch circuit.
The whole system and digital error correction circuit are simulated in the simulink environment; at the same time, based on SMIC 0.18 um CMOS mixed-signal process model the switch circuit is simulated by using Hspice. And the results of simulation show that: the reconfigurable pipelined A/D converter could reconfigure its resolution from 6-bit to 10-bit and also could eliminate efficiently the offset error of comparators of each stage. The overflow detect signal OF could detect correctly whether the input signal is overflow. At 24.4140625 MHz input frequency and 100 MHz sampling frequency, the SFDR of bootstrapped CMOS switch circuit is about 80 dB, which is lower 20 dB than the common CMOS switch circuit.
本文首先在系统结构上选取了在较高采样频率下整个电路功耗较低的1.5位/级结构,这不仅可以简化每级流水线中SubADC和SubDAC的设计,还可以通过数字校正电路来消除一定范围内的比较器失调;针对传统结构中分辨率位数固定以及最后一级流水线的数字输出不能进行校正的不足,设计了一种可重构流水线结构,该结构前九级采用相同的结构,并通过一个重构配置控制电路来使这九级电路有选择的工作,从而实现6~10位不同的分辨率位数,而第十级则为一个精度不高的比较器,来对第九级的数字输出进行校正。其次分析了10位1.5位/级流水线模数转换器中的数字校正算法,并针对其不能判断输入信号是否超出模数转换器量化范围的不足,设计产生了一个溢出判断信号从而使模数转换器具有了溢出判断功能。最后分析了MOS采样保持电路中的各种非理想因素,并针对这些因素在设计中采用了CMOS全差分采样保持电路,它不仅可以消除时钟馈通等共模信号的影响,还可以消除由采样开关带来的与输入信号相关的电荷注入效应;此外还针对采样开关存在的非线性,设计了一种高线性度的bootstrapped CMOS采样开关电路。
在Simulink下对整个系统及数字校正电路进行了行为级仿真,并基于SMIC 0.18um CMOS数模混合工艺模型采用Hspice软件对开关电路进行了仿真,仿真结果表明:所设计的流水线结构模数转换器能够实现6~10位不同的分辨率位数,并可以有效的校正每一级流水线中比较器存在的失调;溢出判断信号OF能正确的判断输入信号是否超出模数转换器的量化范围;在输入信号为24.4140625MHz(1V～2V)的正弦信号时,测到的bootstrapped CMOS开关电路的无杂散动态范围(SFDR)约为80dB,同一般的CMOS传输门开关电路相比,将非线性失真降低了约20dB。
With the rapid development of semi-conductor technology, integrated circuit has stepped into a new era of system on chip (SoC). SoC requires the integration of analog circuits and digital circuits on a single chip. So it is very important to design a high performance A/D converter, which is based on standard CMOS technology. With the explosive development and wide use of wireless communication, imaging process and video process, A/D converter also trends to be high-speed high-resolution and low-power dissipation. Pipelined A/D converter has an excellent combination of high-resolution and high-precision; at the same time, it has a good trade-off between speed and power dissipation, so it is widely used. For the requirement of multi-standard transceiver of wireless LAN, this thesis will research for a 100-MHz sample/s reconfigurable pipelined A/D converter.
firstly, this thesis chooses a 1.5 bit/stage pipelined A/D converter, whose power dissipation is very low at high sampling frequency. This structure not only could make the design of SubADC and SubDAC simply, but also could eliminate the offset of comparators by digital error correction circuit. Aiming at the fixed resolution and the ninth stage’s digital output couldn’t be corrected of the traditional 1.5 bit/stage pipelined structure, this thesis designs a reconfigurable pipelined A/D converter. In the reconfigurable pipelined structure, the first nine stages adopt the same structure, some of which are chosed to operate to achieve the different resolution (6~10-bit) by the reconfigurable control circuit, and the tenth stage just is a simple comparator, which is used to correct the digital output of the ninth stage. Secondly, this thesis analyzes the digital error correction theory of 10-bit 1.5 bit/stage pipelined A/D converter which couldn’t detect the input signal’s overflow. Then designs circuit and obtains an overflow detect signal which could detect whether the input signal is overflow. Finally this thesis analyzes the non-ideal characteristics of MOS sample-and-hold circuit. To reduce these non-ideal characteristics, this thesis adopts a CMOS full differential sample-and-hold circuit, which could reduce the effect of clock feedthrough and channel charge injection. Besides, in order to improve linearity of sample switch, designs a bootstrapped CMOS switch circuit.
The whole system and digital error correction circuit are simulated in the simulink environment; at the same time, based on SMIC 0.18 um CMOS mixed-signal process model the switch circuit is simulated by using Hspice. And the results of simulation show that: the reconfigurable pipelined A/D converter could reconfigure its resolution from 6-bit to 10-bit and also could eliminate efficiently the offset error of comparators of each stage. The overflow detect signal OF could detect correctly whether the input signal is overflow. At 24.4140625 MHz input frequency and 100 MHz sampling frequency, the SFDR of bootstrapped CMOS switch circuit is about 80 dB, which is lower 20 dB than the common CMOS switch circuit.
引文
[1] R. J. Baker. CMOS: Circuit design, layout, and simulation.北京:机械工业出版社, 2003.6: 675-726
[2] David A. Johns, Ken Martin著,曾朝阳,赵阳,方顺等译.模拟集成电路设计.北京:机械工业出版社, 2005.7: 317-378
[3] Seung-Chan HEO, Young Chao-Jang. An 8-bit 200MS/s CMOS folding/interpolating ADC. IECE Tran., 2003: 676-681
[4] Pervez M. Aziz, Henrik V. Sorensen, and Jan Van Der Spiegel. An overview of sigma-delta converters. Signal Process Magazine, IEEE, 1996(13): 61-84
[5]张媛媛,姜岩峰.Σ?Δ模拟/数字转换器综述.微电子学, 2006, 36(4):456-460
[6] Christian Paulus, Hans-Markin Bluthgen. A 4 GS/s 6b Flash ADC in 0.13 um CMOS. Symposium On VLSI Circuits Digest of Technical Papers, 2004: 420-423
[7] Y. Chiu. high-performance pipeline A/D converter design in deep-submicron CMOS. PhD Thesis, University of California, Berkerley, 2004
[8] S. Zargari et al.. A Single-Chip Dual-Band Tri-Mode CMOS Transceiver for IEEE802.11 a/b/g WLAN. ISSCC Dig. Tech. Papers, Feb., 2004: 96-97
[9] Alireza Shirvani et al.. A Dual-band triple-mode SoC for 802.011 a/b/g Embedded WLAN in 90 nm CMOS. IEEE 2006 Custom Integrated Circuits Conference(CICC), Sept. 2006: 89-92
[10] Tadashi Maeda et al.. A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver. IEEE Journal of Solid-State Circuits, Nov. 2006: 2481-2490
[11] M. Yotsuyansgi, E. Etoh, and K. Hirata. A 10-b 50-MHz pipelined CMOS A/D converter with S/H. IEEE Journal of Solid-State Circuits, Mar. 1993: 292-300
[12] Min B. M., Kim P.,Boisvert D. et al.. A 69-mW 10-bit 80-M sample/s pipelined CMOS ADC. IEEE Journal of Solid-State Circuits,2003: 2301-2039
[13] Y. I. Park, S. Karthikeryan, F. Tsay, and E. Bartolime. A 10-b 100-M sample/s CMOS pipelined ADC with 1.8-V power supply. IEEE international Solid-State Circuits Conference, Feb. 2001: 130-131
[14] Hernes B., Briskemyr A. et al.. A 1.2 V 220 MS/s 10b pipeline ADC implemented in 0.13 um digital CMOS. IEEE International Solid-State Circuits Conference, Feb. 2004
[15] Ishii H., Tanabe K., Iida T.. A 1.0 V 40 mW 10b 100 Ms/s pipeline ADC in 90 nm CMOS. IEEE 2005 Custom Integrated Circuits Conference, Sep. 2005: 395-398
[16]黄飞鹏,王静光等.一种57.6 mW 10位50 Ms/s流水线操作CMOS A/D转换器.半导体学报, 2005.11,26(11): 2231-2236
[17] Jun Ming and Stephen H. Lewis. An 8-bit 80-M sample/s pipelined analog-to-digital converter with background calibration. IEEE Journal of Solid-State Circuits, Oct. 2001: 1489-1497
[18]雷监铭,刘三清,东振中等. 12位10 MS/s CMOS流水线结构A/D转换器的设计.微电子学, 2001, 31(2): 87-89
[19] Y. Chiu, P. R. Gray, and B. Nikolic. A 1.8-V, 14-b, 10-MS/s pipelined ADC in 0.18-um CMOS with 99-dB SFDR. IEEE International Solid-State Circuits Conference, Feb. 2004: 458-459
[20]范俊玲,权海洋. 12位50M Sample/s CMOS流水线A/D转换器.微机发展, 2005.12, 15(12): 122-125
[21] Singer L., Timko M. et al.. A 12b 65M Sample/s CMOS ADC with 82 dB SFDR at 120MHz. IEEE international Solid-State Circuits Conference, 2000: 38-39
[22] Terje Nortvedt Anderson, Hernes B. et al.. A cost-efficient high-speed 12-bit pipeline ADC in 0.18-um digital CMOS. IEEE Journal of Solid-State Circuits, July 2005: 1506-1513
[23] Abo A. M., Gray P. R.. A 1.5-V 10-bit 14.3 MS/s CMOS pipeline analog-to-digital converter. IEEE Journal of Solid-State Circuits, 1999: 599-606
[24] Arias J.,Boccuzzi V. et al.. Low-power pipeline ADC for wireless LANs. IEEE Journal of Solid-State Circuits, Aug. 2004: 1338-1340
[25] Andersen T. N. et al.. A 97mW 110MS/s 12b pipeline ADC implemented in 0.18 um digital CMOS. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Mar. 2005: 219-222
[26] Hui Liu, Hassoun M.. High speed re-configurable pipeline ADC cell design. 2001 Southwest Symposium on Mixed-Signal Design, Feb. 2001: 158-161
[27] Shang-yuan(sean) Chung, Terry L, Sculey. A digitally self-calibrating 14-bit 10MHz CMOS pipelined A/D converter. IEEE Journal of Solid-State Circuits, 2002: 674-583
[28] Gines A. J., Peralias E. J., Rueda A.. Full calibration digital techniques for pipeline ADCs. IEEE International Symposium on Circuits and Systems, May 2005: 1976-1979
[29] Chuang S-Y., Scullery T.. A digital self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter. IEEE Journal of Solid-State Circuits, 2002: 674-683
[30] Xiaopeng Li, Bugeja A. R.. Ismail M., A fast and accurate calibration method for high-speed high-resolution pipeline ADC. IEEE International Symposium on Circuits and Systems, May 2002: 26-29
[31]毕查德·拉扎维(著),陈贵灿(译).模拟CMOS集成电路设计.西安:西安交通大学出版社, 2003: 330-355
[32] Chen J., Gu Y-B, Wu T. et al.. Weak inversion charge injection in analog MOS switch. IEEE Journal of Solid-State Circuits, 1995: 1091-1097
[33] Wilson W. B., Massoud H. Z., Swanson E. J. et al.. Measurement and modeling of charge feedthrough in n-channel MOS analog switch. IEEE Journal of Solid-State Circuits, 1985: 1206-1213
[34]陈曦,何乐年.一种用于流水线A/D转换器的低功耗采样/保持电路.微电子学, 2005, 35(5): 545-548
[35]谭珺,唐长文等.一种100MHz采样频率CMOS采样/保持电路.微电子学, 2006.2, 36(1): 90-93
[36] Gatti U., Maloberti F., Palmisano G... An accurate CMOS sample-and-hold circuit. IEEE Journal of Solid-State Circuits, 1992: 102-122
[37]王照刚,陈诚等.一种低电压高精度125MHz采样/保持电路.微电子学, 2004.6, 34(3): 306-309
[38]陈红卫,吴建辉.一种新型高速高分辨率采样保持电路.应用科学学报, 2005.5, 23(3): 274-277
[39]唐林,杨谟华等.一种用于10位100 MSPS流水线A/D转换器的CMOS线性采样开关.微电子学, 2005, 35(2): 199-202
[40]郑晓燕,王洪利,仇玉林等.流水线ADC的系统级仿真.电子器件, 2006.12, 29(4):1288-1291
[41] Bilhan E. et al.. Behavioral model of pipeline ADC by using simulink. 2001 Southwest Symposium on Mixed-Signal Design, Feb. 2001:147-15
[2] David A. Johns, Ken Martin著,曾朝阳,赵阳,方顺等译.模拟集成电路设计.北京:机械工业出版社, 2005.7: 317-378
[3] Seung-Chan HEO, Young Chao-Jang. An 8-bit 200MS/s CMOS folding/interpolating ADC. IECE Tran., 2003: 676-681
[4] Pervez M. Aziz, Henrik V. Sorensen, and Jan Van Der Spiegel. An overview of sigma-delta converters. Signal Process Magazine, IEEE, 1996(13): 61-84
[5]张媛媛,姜岩峰.Σ?Δ模拟/数字转换器综述.微电子学, 2006, 36(4):456-460
[6] Christian Paulus, Hans-Markin Bluthgen. A 4 GS/s 6b Flash ADC in 0.13 um CMOS. Symposium On VLSI Circuits Digest of Technical Papers, 2004: 420-423
[7] Y. Chiu. high-performance pipeline A/D converter design in deep-submicron CMOS. PhD Thesis, University of California, Berkerley, 2004
[8] S. Zargari et al.. A Single-Chip Dual-Band Tri-Mode CMOS Transceiver for IEEE802.11 a/b/g WLAN. ISSCC Dig. Tech. Papers, Feb., 2004: 96-97
[9] Alireza Shirvani et al.. A Dual-band triple-mode SoC for 802.011 a/b/g Embedded WLAN in 90 nm CMOS. IEEE 2006 Custom Integrated Circuits Conference(CICC), Sept. 2006: 89-92
[10] Tadashi Maeda et al.. A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver. IEEE Journal of Solid-State Circuits, Nov. 2006: 2481-2490
[11] M. Yotsuyansgi, E. Etoh, and K. Hirata. A 10-b 50-MHz pipelined CMOS A/D converter with S/H. IEEE Journal of Solid-State Circuits, Mar. 1993: 292-300
[12] Min B. M., Kim P.,Boisvert D. et al.. A 69-mW 10-bit 80-M sample/s pipelined CMOS ADC. IEEE Journal of Solid-State Circuits,2003: 2301-2039
[13] Y. I. Park, S. Karthikeryan, F. Tsay, and E. Bartolime. A 10-b 100-M sample/s CMOS pipelined ADC with 1.8-V power supply. IEEE international Solid-State Circuits Conference, Feb. 2001: 130-131
[14] Hernes B., Briskemyr A. et al.. A 1.2 V 220 MS/s 10b pipeline ADC implemented in 0.13 um digital CMOS. IEEE International Solid-State Circuits Conference, Feb. 2004
[15] Ishii H., Tanabe K., Iida T.. A 1.0 V 40 mW 10b 100 Ms/s pipeline ADC in 90 nm CMOS. IEEE 2005 Custom Integrated Circuits Conference, Sep. 2005: 395-398
[16]黄飞鹏,王静光等.一种57.6 mW 10位50 Ms/s流水线操作CMOS A/D转换器.半导体学报, 2005.11,26(11): 2231-2236
[17] Jun Ming and Stephen H. Lewis. An 8-bit 80-M sample/s pipelined analog-to-digital converter with background calibration. IEEE Journal of Solid-State Circuits, Oct. 2001: 1489-1497
[18]雷监铭,刘三清,东振中等. 12位10 MS/s CMOS流水线结构A/D转换器的设计.微电子学, 2001, 31(2): 87-89
[19] Y. Chiu, P. R. Gray, and B. Nikolic. A 1.8-V, 14-b, 10-MS/s pipelined ADC in 0.18-um CMOS with 99-dB SFDR. IEEE International Solid-State Circuits Conference, Feb. 2004: 458-459
[20]范俊玲,权海洋. 12位50M Sample/s CMOS流水线A/D转换器.微机发展, 2005.12, 15(12): 122-125
[21] Singer L., Timko M. et al.. A 12b 65M Sample/s CMOS ADC with 82 dB SFDR at 120MHz. IEEE international Solid-State Circuits Conference, 2000: 38-39
[22] Terje Nortvedt Anderson, Hernes B. et al.. A cost-efficient high-speed 12-bit pipeline ADC in 0.18-um digital CMOS. IEEE Journal of Solid-State Circuits, July 2005: 1506-1513
[23] Abo A. M., Gray P. R.. A 1.5-V 10-bit 14.3 MS/s CMOS pipeline analog-to-digital converter. IEEE Journal of Solid-State Circuits, 1999: 599-606
[24] Arias J.,Boccuzzi V. et al.. Low-power pipeline ADC for wireless LANs. IEEE Journal of Solid-State Circuits, Aug. 2004: 1338-1340
[25] Andersen T. N. et al.. A 97mW 110MS/s 12b pipeline ADC implemented in 0.18 um digital CMOS. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Mar. 2005: 219-222
[26] Hui Liu, Hassoun M.. High speed re-configurable pipeline ADC cell design. 2001 Southwest Symposium on Mixed-Signal Design, Feb. 2001: 158-161
[27] Shang-yuan(sean) Chung, Terry L, Sculey. A digitally self-calibrating 14-bit 10MHz CMOS pipelined A/D converter. IEEE Journal of Solid-State Circuits, 2002: 674-583
[28] Gines A. J., Peralias E. J., Rueda A.. Full calibration digital techniques for pipeline ADCs. IEEE International Symposium on Circuits and Systems, May 2005: 1976-1979
[29] Chuang S-Y., Scullery T.. A digital self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter. IEEE Journal of Solid-State Circuits, 2002: 674-683
[30] Xiaopeng Li, Bugeja A. R.. Ismail M., A fast and accurate calibration method for high-speed high-resolution pipeline ADC. IEEE International Symposium on Circuits and Systems, May 2002: 26-29
[31]毕查德·拉扎维(著),陈贵灿(译).模拟CMOS集成电路设计.西安:西安交通大学出版社, 2003: 330-355
[32] Chen J., Gu Y-B, Wu T. et al.. Weak inversion charge injection in analog MOS switch. IEEE Journal of Solid-State Circuits, 1995: 1091-1097
[33] Wilson W. B., Massoud H. Z., Swanson E. J. et al.. Measurement and modeling of charge feedthrough in n-channel MOS analog switch. IEEE Journal of Solid-State Circuits, 1985: 1206-1213
[34]陈曦,何乐年.一种用于流水线A/D转换器的低功耗采样/保持电路.微电子学, 2005, 35(5): 545-548
[35]谭珺,唐长文等.一种100MHz采样频率CMOS采样/保持电路.微电子学, 2006.2, 36(1): 90-93
[36] Gatti U., Maloberti F., Palmisano G... An accurate CMOS sample-and-hold circuit. IEEE Journal of Solid-State Circuits, 1992: 102-122
[37]王照刚,陈诚等.一种低电压高精度125MHz采样/保持电路.微电子学, 2004.6, 34(3): 306-309
[38]陈红卫,吴建辉.一种新型高速高分辨率采样保持电路.应用科学学报, 2005.5, 23(3): 274-277
[39]唐林,杨谟华等.一种用于10位100 MSPS流水线A/D转换器的CMOS线性采样开关.微电子学, 2005, 35(2): 199-202
[40]郑晓燕,王洪利,仇玉林等.流水线ADC的系统级仿真.电子器件, 2006.12, 29(4):1288-1291
[41] Bilhan E. et al.. Behavioral model of pipeline ADC by using simulink. 2001 Southwest Symposium on Mixed-Signal Design, Feb. 2001:147-15