视频格式转换技术及其VLSI设计研究
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摘要
视频格式转换芯片,是数字电视和数字处理电视的核心芯片之一,具有巨大的市场价值。它的主要功能是通过数字信号处理的方法把众多格式的输入信号转换成特定格式的输出信号。主要处理过程包含去隔行、帧频提升、分辨率提升,及各种画质增强。
由于视频信号格式的多样性、处理算法的复杂性以及观众对画质的苛刻要求,视频格式转换芯片的研发面临着两方面技术难题:第一,开发兼顾主观效果和硬件开销的优秀视频格式转换算法;第二,设计高性能的VLSI实现方案。
在总结和学习现有技术的基础上,本文从视频格式转换算法研究入手,着重论述了核心算法模块的VLSI实现方案和芯片总体架构的设计方案,并分析了相应的仿真验证结果。主要贡献在于以下几方面:
第一,归纳总结了现有的视频格式转换算法,并在此基础上提出了一种运动自适应去隔行算法。
第二,针对运动自适应去隔行算法的特点,提出了基于运动量存储的数据调度方案和折叠复用式缓存结构,大幅降低了硬件开销、减轻了系统的运算负担。
第三,针对芯片设计难点,提出了两种总体控制策略及相应的芯片架构设计方案,并从鲁棒性、可扩展性和实时处理视频信号的能力等角度,分析对比两种方案的优劣,最终得出结论。
As one of the most important chips in DTV and DPTV, video format conversion chip has a huge commercial value. Its main function is converting different input video formats into a given one through digital signal processing flow. It comprises de-interlacing, frame rate up-conversion, scaling and many image enhancement processes.
Due to the diversity of input video formats, the complexity of processing algorithms and viewers’high requirements on image effect, it is necessary to overcome two difficulties to implement the chip: one is developing excellent video format conversion algorithms, which perfectly balance image effect and hardware expense; the other is designing high performance VLSI solutions.
After investigating existing technologies, the author starts with developing video format conversion algorithms, expatiates on the VLSI implementation of key-algorithm blocks and the top-level system design of the chip, then analyzes the simulation results. Main contributions of the dissertation are shown below.
First, sum up existing video format conversion algorithms; bring forward a motion-adaptive de-interlacing algorithm.
Second, due to the operation characteristics of the de-interlacing algorithm, a motion-value stored data transfer strategy and zigzag FIFO structure are proposed to reduce hardware expense and alleviate computational burden.
Third, to deal with difficulties in designing the chip, the author brings forward two top-level control strategies and related top-level system solutions for the chip, compares them in several aspects, such as robustness, extensibility and real-time processing ability, then draws a conclusion.
由于视频信号格式的多样性、处理算法的复杂性以及观众对画质的苛刻要求,视频格式转换芯片的研发面临着两方面技术难题:第一,开发兼顾主观效果和硬件开销的优秀视频格式转换算法;第二,设计高性能的VLSI实现方案。
在总结和学习现有技术的基础上,本文从视频格式转换算法研究入手,着重论述了核心算法模块的VLSI实现方案和芯片总体架构的设计方案,并分析了相应的仿真验证结果。主要贡献在于以下几方面:
第一,归纳总结了现有的视频格式转换算法,并在此基础上提出了一种运动自适应去隔行算法。
第二,针对运动自适应去隔行算法的特点,提出了基于运动量存储的数据调度方案和折叠复用式缓存结构,大幅降低了硬件开销、减轻了系统的运算负担。
第三,针对芯片设计难点,提出了两种总体控制策略及相应的芯片架构设计方案,并从鲁棒性、可扩展性和实时处理视频信号的能力等角度,分析对比两种方案的优劣,最终得出结论。
As one of the most important chips in DTV and DPTV, video format conversion chip has a huge commercial value. Its main function is converting different input video formats into a given one through digital signal processing flow. It comprises de-interlacing, frame rate up-conversion, scaling and many image enhancement processes.
Due to the diversity of input video formats, the complexity of processing algorithms and viewers’high requirements on image effect, it is necessary to overcome two difficulties to implement the chip: one is developing excellent video format conversion algorithms, which perfectly balance image effect and hardware expense; the other is designing high performance VLSI solutions.
After investigating existing technologies, the author starts with developing video format conversion algorithms, expatiates on the VLSI implementation of key-algorithm blocks and the top-level system design of the chip, then analyzes the simulation results. Main contributions of the dissertation are shown below.
First, sum up existing video format conversion algorithms; bring forward a motion-adaptive de-interlacing algorithm.
Second, due to the operation characteristics of the de-interlacing algorithm, a motion-value stored data transfer strategy and zigzag FIFO structure are proposed to reduce hardware expense and alleviate computational burden.
Third, to deal with difficulties in designing the chip, the author brings forward two top-level control strategies and related top-level system solutions for the chip, compares them in several aspects, such as robustness, extensibility and real-time processing ability, then draws a conclusion.
引文
[1] 张兆扬,数字电视原理,北京:科学技术出版社,1989:14~18
[2] Jerry Whitaker,数字电视技术:高清晰数字视频原理与应用(第三版)(曹晨,杨作梅译),电子工业出版社与麦格劳-希尔教育出版集团,2002:20~23
[3] 余兆明,数字电视和高清晰度电视,北京:人民邮电出版社,1997:6~8
[4] 唐良瑞,黄心渊,一种基于人眼视觉特性的图像压缩方法,数字视频,2000,38(8):977~981
[5] Dipl. Ing, Comparison between Median Filtering and Vertical Edge Controlled Interpolation for Flicker Reduction, IEEE Transactions on Consumer Electronics, Aug. 1989, 35(3):1020~1023
[6] 李丽欣,数字梳状滤波器,德州学院学报,2004,20(2):32~34
[7] SAA7110/7110A Product Specification, Philips Semiconductors, 2000
[8] G.D.Haan, E.B.Bellers, Deinterlacing – an Overview, Proc. of IEEE, Sep. 1998, 86(9): 1839~1857
[9] B.T. Choi, S.H. Lee, etc., New Frame Rate Up-conversion Using Bi-directional Motion Estimation, IEEE Trans. on Circuits and Systems for Video Technology, Aug. 2000, 46(3): 603~609
[10] 汪颖、陈涛等,视频图像缩放的设计及实现,电视技术,2004,No.6:36~38
[11] 聂祥飞,基于反锐化掩模法的图像增强研究,中国有线电视,2004,No.9:8~10
[12] WSC1115 Data Sheet, Weststar Semiconductor, 2004
[13] ITU-R BT.601-5
[14] G. Gupta, C. Chakrabatri, Architectures for Hierarchical and Other Block Matching Algorithms, IEEE Trans. Circ. and Syst. for Video Technol., Dec. 1995, 5(6):897~899
[15] 唐泽鹏、秦雷、朱秀昌等,运动估计算法分析,电视技术,2001,No.12:10~13
[16] R. Li, B. Zeng, and M. L. Liou, A New Three-step Search Algorithm for Block Motion Estimation, IEEE Trans. Circuits Syst. Video Technol., 1994, 4: 438~442
[17] Durand C.X., Faguy D, Rational Zoom of Bit Maps Using B-spline Interpolation in Computerized 2-D Animation, Computer Graphics Forum, 1990, 9: 27~37
[18] 孙庆杰,张晓鹏,吴恩华,一种基于 Bezier 插值曲面的图像放大方法,软件学报,1999,10(6):570~574
[19] Unser M., Aldroubi A, Eden M., Enlargement or Reduction of Digital Images with Minimum Loss of Information, IEEE Trans. Image Process, 1995, 4(3): 247~258
[20] Ramponi G., Warped Distance for Space-variant Linear Image Interpolation, IEEE Trans. Image Process, 1999, 8(5): 629~639
[21] Lehmann T. M., Gonner C., Spitzer K., Survey: Interpolation Methods in Medical Image Processing, IEEE Trans. Med. Imag., 1999, 18(11): 1049~1075
[22] 程佩青,数字信号处理,北京:清华大学出版社,1995:64~66
[23] John L. Hennessy, David A. Patterson, Computer Organization & Design the Hardware / Software Interface, Morgan Kaufmann, 2002. 434~448
[24] 黄琳、王龙、于年才,系统鲁棒性的若干问题背景、现状与挑战,控制理论与应用,1991,No. 8:11~29
[25] Vertex-2 Platform FPGA User Guide (Rev 1.5), Xilinx, Inc., 2002
[26] ISE 6.3i User Guide, Xilinx, Inc., 2005
[27] ModelSim 5.8SE User Guide, Mentor Graphics, 2005
[28] Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, Prentice Hall, 2003
[29] Single-port Block Memory Product Specification (v6.1), Xilinx, Inc., May 2004
[30] TMS320C3x User’s Guide, Texas Instruments, Inc., July 1997
[31] Synchronous DRAM MT48LC4M32B2 Data Sheet, Micron Technology, Inc., 2001
[32] A. Murat Tekalp, Digital Video Processing, Prentice Hall, 1998: 37~40
[33] R.B. Wittebrood and G. de Haan, Real-time Recursive Motion Segmentation of Video Data on a Programmable Device, IEEE Transactions on Consumer Electronics, Aug. 2001. 559~567
[2] Jerry Whitaker,数字电视技术:高清晰数字视频原理与应用(第三版)(曹晨,杨作梅译),电子工业出版社与麦格劳-希尔教育出版集团,2002:20~23
[3] 余兆明,数字电视和高清晰度电视,北京:人民邮电出版社,1997:6~8
[4] 唐良瑞,黄心渊,一种基于人眼视觉特性的图像压缩方法,数字视频,2000,38(8):977~981
[5] Dipl. Ing, Comparison between Median Filtering and Vertical Edge Controlled Interpolation for Flicker Reduction, IEEE Transactions on Consumer Electronics, Aug. 1989, 35(3):1020~1023
[6] 李丽欣,数字梳状滤波器,德州学院学报,2004,20(2):32~34
[7] SAA7110/7110A Product Specification, Philips Semiconductors, 2000
[8] G.D.Haan, E.B.Bellers, Deinterlacing – an Overview, Proc. of IEEE, Sep. 1998, 86(9): 1839~1857
[9] B.T. Choi, S.H. Lee, etc., New Frame Rate Up-conversion Using Bi-directional Motion Estimation, IEEE Trans. on Circuits and Systems for Video Technology, Aug. 2000, 46(3): 603~609
[10] 汪颖、陈涛等,视频图像缩放的设计及实现,电视技术,2004,No.6:36~38
[11] 聂祥飞,基于反锐化掩模法的图像增强研究,中国有线电视,2004,No.9:8~10
[12] WSC1115 Data Sheet, Weststar Semiconductor, 2004
[13] ITU-R BT.601-5
[14] G. Gupta, C. Chakrabatri, Architectures for Hierarchical and Other Block Matching Algorithms, IEEE Trans. Circ. and Syst. for Video Technol., Dec. 1995, 5(6):897~899
[15] 唐泽鹏、秦雷、朱秀昌等,运动估计算法分析,电视技术,2001,No.12:10~13
[16] R. Li, B. Zeng, and M. L. Liou, A New Three-step Search Algorithm for Block Motion Estimation, IEEE Trans. Circuits Syst. Video Technol., 1994, 4: 438~442
[17] Durand C.X., Faguy D, Rational Zoom of Bit Maps Using B-spline Interpolation in Computerized 2-D Animation, Computer Graphics Forum, 1990, 9: 27~37
[18] 孙庆杰,张晓鹏,吴恩华,一种基于 Bezier 插值曲面的图像放大方法,软件学报,1999,10(6):570~574
[19] Unser M., Aldroubi A, Eden M., Enlargement or Reduction of Digital Images with Minimum Loss of Information, IEEE Trans. Image Process, 1995, 4(3): 247~258
[20] Ramponi G., Warped Distance for Space-variant Linear Image Interpolation, IEEE Trans. Image Process, 1999, 8(5): 629~639
[21] Lehmann T. M., Gonner C., Spitzer K., Survey: Interpolation Methods in Medical Image Processing, IEEE Trans. Med. Imag., 1999, 18(11): 1049~1075
[22] 程佩青,数字信号处理,北京:清华大学出版社,1995:64~66
[23] John L. Hennessy, David A. Patterson, Computer Organization & Design the Hardware / Software Interface, Morgan Kaufmann, 2002. 434~448
[24] 黄琳、王龙、于年才,系统鲁棒性的若干问题背景、现状与挑战,控制理论与应用,1991,No. 8:11~29
[25] Vertex-2 Platform FPGA User Guide (Rev 1.5), Xilinx, Inc., 2002
[26] ISE 6.3i User Guide, Xilinx, Inc., 2005
[27] ModelSim 5.8SE User Guide, Mentor Graphics, 2005
[28] Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, Prentice Hall, 2003
[29] Single-port Block Memory Product Specification (v6.1), Xilinx, Inc., May 2004
[30] TMS320C3x User’s Guide, Texas Instruments, Inc., July 1997
[31] Synchronous DRAM MT48LC4M32B2 Data Sheet, Micron Technology, Inc., 2001
[32] A. Murat Tekalp, Digital Video Processing, Prentice Hall, 1998: 37~40
[33] R.B. Wittebrood and G. de Haan, Real-time Recursive Motion Segmentation of Video Data on a Programmable Device, IEEE Transactions on Consumer Electronics, Aug. 2001. 559~567