高性能32/33分频双模前置分频器设计
摘要
频率合成器是位于无线通信系统前端的重要部分。它的功能是将频率较低的参考信号转换成射频范围的标准本振信号。前置分频器位于射频锁相环的反馈部分。前置分频器的输入信号为锁相环的射频输出信号,输出信号为频率较低的锁相环反馈输入信号。由于工作频率范围在射频,前置分频器也是锁相环中功耗最大的部分之一。低功耗的前置分频器设计可以很大程度上降低整个锁相环的功率损耗。本文在总结了当前国内外低功耗射频CMOS双模前置分频器的发展现状和技术水平基础上,深入探讨了一种低功耗、射频CMOS双模前置分频器的设计。在射频CMOS集成电路设计中,本文的讨论焦点是高速和低功耗。
本文介绍了锁相环频率合成器的基本结构、分析了其工作过程和特性,讨论了前置分频器模拟型以及相位转换型结构的各自特点和优劣,采用具有差分对和尾电流特点的SCL结构设计了前置分频器所需的源耦合逻辑主从D触发器,因其具有自锁存功能,且比传统的D触发器所需的管子更少,这样在实现高速的同时,也减少了芯片面积和功耗,还降低了系统的噪声;分析了差分电路的差模传输特性,在分析传统型SCL-D-Latch锁存器的基础上对其进行了改进设计,输出极采用PMOS和NMOS互补耦合结构以使系统的时间常数减小,并提高整个电路的工作速度和获得较大的输出幅度。
基于TSMC0.18μm工艺,采用Cadence SpectreRF软件进行电路仿真。结果表明:该分频器的最高工作频率为4GHz,能够很好的实现32/33分频,并且整个电路的功耗仅为4.5mW。
The frequency synthesizer is an important RE front-end part in wireless communication. Its function is change the reference signal, which is low frequency input signal to RF standard LO signal. The frequency synthesizer is a PLL (Phase Locked Loop) in GHz range. The PLL in GHz range is one of the highest power dissipation parts in system. So the decrease of PLL power dissipation will have great effect on the whole system power dissipation. The Prescaler(PS) is a feedback block in RF PLL. The input signal of PS is in GHz range and its output signal is in low frequency range. The PS is one of the great power dissipation parts in PLL. So a low power dissipation PS is important to the PLL.
In this paper, the development of situation and technology level of low power CMOS RF prescaler are analyzed and summarized. Also, the theory and methods of high-speed and low power CMOS RF prescaler are expounded profoundly.In CMOS RFIC design,we focuses on the issue of low power. We complete the macro-structure by digital method .We use digital units such as D flip-flop, logic gats etc. Then analyze and simulate the circuit detail by analog method. SCL(Source Coupled Logic) has also been selected. In the lower frequency band, DFF with self-latch function were used. This structure not only has locked function but also less MOS transistor than M/S DFF. So it satisfies the command of lower power and noise. The whole system could realize high-speed, low-power, low-jitter.
This divider was simulated by Cadence SpectreRF based on TSMC0.18μm process. Results indicate that the divider could operated at 4GHz to realize 32/33 prescaler,and the power was only 4.5mW.
本文介绍了锁相环频率合成器的基本结构、分析了其工作过程和特性,讨论了前置分频器模拟型以及相位转换型结构的各自特点和优劣,采用具有差分对和尾电流特点的SCL结构设计了前置分频器所需的源耦合逻辑主从D触发器,因其具有自锁存功能,且比传统的D触发器所需的管子更少,这样在实现高速的同时,也减少了芯片面积和功耗,还降低了系统的噪声;分析了差分电路的差模传输特性,在分析传统型SCL-D-Latch锁存器的基础上对其进行了改进设计,输出极采用PMOS和NMOS互补耦合结构以使系统的时间常数减小,并提高整个电路的工作速度和获得较大的输出幅度。
基于TSMC0.18μm工艺,采用Cadence SpectreRF软件进行电路仿真。结果表明:该分频器的最高工作频率为4GHz,能够很好的实现32/33分频,并且整个电路的功耗仅为4.5mW。
The frequency synthesizer is an important RE front-end part in wireless communication. Its function is change the reference signal, which is low frequency input signal to RF standard LO signal. The frequency synthesizer is a PLL (Phase Locked Loop) in GHz range. The PLL in GHz range is one of the highest power dissipation parts in system. So the decrease of PLL power dissipation will have great effect on the whole system power dissipation. The Prescaler(PS) is a feedback block in RF PLL. The input signal of PS is in GHz range and its output signal is in low frequency range. The PS is one of the great power dissipation parts in PLL. So a low power dissipation PS is important to the PLL.
In this paper, the development of situation and technology level of low power CMOS RF prescaler are analyzed and summarized. Also, the theory and methods of high-speed and low power CMOS RF prescaler are expounded profoundly.In CMOS RFIC design,we focuses on the issue of low power. We complete the macro-structure by digital method .We use digital units such as D flip-flop, logic gats etc. Then analyze and simulate the circuit detail by analog method. SCL(Source Coupled Logic) has also been selected. In the lower frequency band, DFF with self-latch function were used. This structure not only has locked function but also less MOS transistor than M/S DFF. So it satisfies the command of lower power and noise. The whole system could realize high-speed, low-power, low-jitter.
This divider was simulated by Cadence SpectreRF based on TSMC0.18μm process. Results indicate that the divider could operated at 4GHz to realize 32/33 prescaler,and the power was only 4.5mW.
引文
[1] P. E.艾伦,D. R. 霍尔伯格.CMOS 模拟电路设计[M].北京:科学出版社,1995: 78-90.
[2] 朱正涌.半导体集成电路[M].北京:清华大学出版社,2001:40-100.
[3] 潘灏.低功耗射频 CMOS 双模前置分频器设计[D].安徽合肥:安徽大学电气院,2005:15-40.
[4] THOMAS H.LEE. CMOS 射频集成电路设计[D].北京 : 电子工业出版社, 2004:315-344.
[5] 包志华, 景为平. 3.75GHz 0.35μm CMOS1: 4 静态分频器集成电路设计[J]. 南京邮电学院学报(自然科学版) , 2001, 5(04): 56-58
[6] Larson L E. Integrated circuit technology options for RF IC’spresent status and future directions[J]. IEEE Journal of Solid-state Circuit, 1998, 33(3): 387-399.
[7] 王欢, 王志功, 冯军 等. 12-GHz 0.25μmCMOS 1/2 动态分频器[J]. 高技术通讯, 2003,6(08):45-47.
[8] Foroudi N, Kwasniewski TA. CMOS high speed dual-modulus frequency divider for RF frequency synthesis[J]. IEEE Journal of Solid-state Circuits, 1995,30(2):93-100.
[9] 陈作添, 吴烜, 唐守龙 等. 宽带低相位噪声锁相环型频率合成器的 CMOS实现[J]. 半导体学报, 2006, 8(10) :67-69
[10] 王永禄, 杨毓军, 周述涛. 一种超低功耗 5GHz 双模预置分频器[J]. 微电子学, 2006, 6(5): 38-40
[11] Larsson P. High-speed architecture for a programmable frequency divider and a dual-modulus prescaler[J]. IEEE Journal of Solid-state Circuits, 1996, 31(5): 744-748.
[12] 杨仿, 苏彦锋, 李宁 等. 一种应用于 GSM 接收机频率合成器的多模分频器. 微电子学, 2006, 8(3): 46-48.
[13] 张春晖,李永明,陈弘毅. 一种采用新触发器的高速 CMOS 前置分频器[J].半导体学报, 2001,8(06) :56-58.
[14] Lam C, Razavi B. A 2.6GHz/5.2GHz frequency synthesizer in 0.4um CMOS technology[J]. IEEE Journal of Solid-state Circuits, 2000, 35(5):788-789.
[15] Yang C Y, Dehng G K, Hsu J M, et al.New dynamic flip-flops for high-speed dual-modulus prescaler[J]. IEEE Journal of Solid-state Circuits, 1998, 33(10):1568-1572.
[16] 陈继伟, 石秉学.CMOS 射频集成电路:成果与展望[J].微电子学,2001,31(5): 323-328.
[17] Behzad Razavi. Design of Analog CMOS intgrated circuits[J]. IEEE Solid-State Circuits, 2003, 3(38): 570-578.
[18] Foroudi N, Kwasniewski T A. CMOS high speed dual-modulus frequency divider for RF frequency synthesis[J]. IEEE Journal of Solid-state Circuits, 1995, 30(2): 93-100.
[19] 杨文荣, 曹家麟等.一种适用于 RF 频率合成器的 CMOS 高速双模前置分频器[J].上海大学学报, 2005, 11(1):20-23
[20] 韩 波 , 唐 广 .2.4GHz 动 态 CMOS 分 频 器 的 设 计 [J]. 国 外 电 子 元 器件,2006,12(2):138-146.
[21] Craninckx J, Steyaert M. A 1.75 GHz 3 V dual modulus divider by 128/129 prescaler in 0.7μm CMOS[J]. IEEE Journal of Solid-state Circuits, 1996, 31(7): 890-897.
[22] 邝小飞.高速双模前置分频器的速度优化设计[J].EDA 技术交流, 2002, 27(10): 38-42.
[23] 池保勇, 石秉学, 王志华. 射频锁相环型频率合成器的 CMOS 实现[J]. 电子学报, 2004,8(11) :70-72.
[24] J.Navarro Soares, Jr, WAM Van Noije. A 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC)[J] . IEEE Journal of Solid-state Circuits, 1999,34(8): 97-102.
[25] P.Larsson. High-Speed Architecture for a programmable Frequency Divider and a Dual-Modulus Prescaler[J]. IEEE Journal of Solid-state Circuits, 1996, 5(l31): 744-748.
[26] 应建华, 颜学超, 彭颖. 基于新型 D 触发器的双模前置分频器[J]. 计算机与数字工程, 2005,5(3):81-83.
[27] 李骅, 衣晓峰, 洪志良. 一种相位开关型分频器电路的噪声分析[J]. 固体电子学研究与进展 , 2006,6(2):72-75.
[28] 袁 博 鲁 . 一 种 新 型 的 超 高 频 低 功 耗 预 置 分 频 器 结 构 [J]. 微 电 子 学 , 1997,5(3):35-38.
[29] 汪猛,丁瑞雪,杨银堂.一种 2.4G 的低功耗 BiCMOS 预置数分频器[J].微电子学与计算机,2006, 23(3): 169-171.
[30] C.S.Vaucher, I.Ferencic, M.Locher etl. A family of low-power truly modulus programmable dividers in standard 0.35μm CMOS technology[J]. IEEE Journalof Solid-state Circuits, 2000, 6(35): 1039-1045.
[31] Yuan J, Svenssor C. High-speed CMOS circuit technique[J]. IEEE Journal of Solid-state Circuits, 1989, 24(2): 62-70
[32] 张剑宇, 孙承绶, 来金梅等. 2.4GHz 频率合成器可编程分频器设计与实现[J].复旦学报(自然科学版), 2005, 5(1):68-70
[33] Yang J, Debng G, Hsu J, etal. New dynamic flip flops for high-speed dual-modulus prescaler[J]. IEEE Journal of Solid-state Circuits, 1998, 33(10): 62-70
[34] Chang B, Park J, Kin W. A 1.2 GHz CMOS dual modulus Prescaler Using New Dynamic D-type flip-flops[J]. IEEE Journal of Solid-state Circuits, 1996, 31(10): 749-752
[35] Hung Chih-Ming, Floyd B A, Park N, etal. Fully integrated 5.35 GHz CMOS VCOs and prescaler[J]. IEEE Trans Microwave Theory Tech, 2001, 44(1): 17-22
[2] 朱正涌.半导体集成电路[M].北京:清华大学出版社,2001:40-100.
[3] 潘灏.低功耗射频 CMOS 双模前置分频器设计[D].安徽合肥:安徽大学电气院,2005:15-40.
[4] THOMAS H.LEE. CMOS 射频集成电路设计[D].北京 : 电子工业出版社, 2004:315-344.
[5] 包志华, 景为平. 3.75GHz 0.35μm CMOS1: 4 静态分频器集成电路设计[J]. 南京邮电学院学报(自然科学版) , 2001, 5(04): 56-58
[6] Larson L E. Integrated circuit technology options for RF IC’spresent status and future directions[J]. IEEE Journal of Solid-state Circuit, 1998, 33(3): 387-399.
[7] 王欢, 王志功, 冯军 等. 12-GHz 0.25μmCMOS 1/2 动态分频器[J]. 高技术通讯, 2003,6(08):45-47.
[8] Foroudi N, Kwasniewski TA. CMOS high speed dual-modulus frequency divider for RF frequency synthesis[J]. IEEE Journal of Solid-state Circuits, 1995,30(2):93-100.
[9] 陈作添, 吴烜, 唐守龙 等. 宽带低相位噪声锁相环型频率合成器的 CMOS实现[J]. 半导体学报, 2006, 8(10) :67-69
[10] 王永禄, 杨毓军, 周述涛. 一种超低功耗 5GHz 双模预置分频器[J]. 微电子学, 2006, 6(5): 38-40
[11] Larsson P. High-speed architecture for a programmable frequency divider and a dual-modulus prescaler[J]. IEEE Journal of Solid-state Circuits, 1996, 31(5): 744-748.
[12] 杨仿, 苏彦锋, 李宁 等. 一种应用于 GSM 接收机频率合成器的多模分频器. 微电子学, 2006, 8(3): 46-48.
[13] 张春晖,李永明,陈弘毅. 一种采用新触发器的高速 CMOS 前置分频器[J].半导体学报, 2001,8(06) :56-58.
[14] Lam C, Razavi B. A 2.6GHz/5.2GHz frequency synthesizer in 0.4um CMOS technology[J]. IEEE Journal of Solid-state Circuits, 2000, 35(5):788-789.
[15] Yang C Y, Dehng G K, Hsu J M, et al.New dynamic flip-flops for high-speed dual-modulus prescaler[J]. IEEE Journal of Solid-state Circuits, 1998, 33(10):1568-1572.
[16] 陈继伟, 石秉学.CMOS 射频集成电路:成果与展望[J].微电子学,2001,31(5): 323-328.
[17] Behzad Razavi. Design of Analog CMOS intgrated circuits[J]. IEEE Solid-State Circuits, 2003, 3(38): 570-578.
[18] Foroudi N, Kwasniewski T A. CMOS high speed dual-modulus frequency divider for RF frequency synthesis[J]. IEEE Journal of Solid-state Circuits, 1995, 30(2): 93-100.
[19] 杨文荣, 曹家麟等.一种适用于 RF 频率合成器的 CMOS 高速双模前置分频器[J].上海大学学报, 2005, 11(1):20-23
[20] 韩 波 , 唐 广 .2.4GHz 动 态 CMOS 分 频 器 的 设 计 [J]. 国 外 电 子 元 器件,2006,12(2):138-146.
[21] Craninckx J, Steyaert M. A 1.75 GHz 3 V dual modulus divider by 128/129 prescaler in 0.7μm CMOS[J]. IEEE Journal of Solid-state Circuits, 1996, 31(7): 890-897.
[22] 邝小飞.高速双模前置分频器的速度优化设计[J].EDA 技术交流, 2002, 27(10): 38-42.
[23] 池保勇, 石秉学, 王志华. 射频锁相环型频率合成器的 CMOS 实现[J]. 电子学报, 2004,8(11) :70-72.
[24] J.Navarro Soares, Jr, WAM Van Noije. A 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC)[J] . IEEE Journal of Solid-state Circuits, 1999,34(8): 97-102.
[25] P.Larsson. High-Speed Architecture for a programmable Frequency Divider and a Dual-Modulus Prescaler[J]. IEEE Journal of Solid-state Circuits, 1996, 5(l31): 744-748.
[26] 应建华, 颜学超, 彭颖. 基于新型 D 触发器的双模前置分频器[J]. 计算机与数字工程, 2005,5(3):81-83.
[27] 李骅, 衣晓峰, 洪志良. 一种相位开关型分频器电路的噪声分析[J]. 固体电子学研究与进展 , 2006,6(2):72-75.
[28] 袁 博 鲁 . 一 种 新 型 的 超 高 频 低 功 耗 预 置 分 频 器 结 构 [J]. 微 电 子 学 , 1997,5(3):35-38.
[29] 汪猛,丁瑞雪,杨银堂.一种 2.4G 的低功耗 BiCMOS 预置数分频器[J].微电子学与计算机,2006, 23(3): 169-171.
[30] C.S.Vaucher, I.Ferencic, M.Locher etl. A family of low-power truly modulus programmable dividers in standard 0.35μm CMOS technology[J]. IEEE Journalof Solid-state Circuits, 2000, 6(35): 1039-1045.
[31] Yuan J, Svenssor C. High-speed CMOS circuit technique[J]. IEEE Journal of Solid-state Circuits, 1989, 24(2): 62-70
[32] 张剑宇, 孙承绶, 来金梅等. 2.4GHz 频率合成器可编程分频器设计与实现[J].复旦学报(自然科学版), 2005, 5(1):68-70
[33] Yang J, Debng G, Hsu J, etal. New dynamic flip flops for high-speed dual-modulus prescaler[J]. IEEE Journal of Solid-state Circuits, 1998, 33(10): 62-70
[34] Chang B, Park J, Kin W. A 1.2 GHz CMOS dual modulus Prescaler Using New Dynamic D-type flip-flops[J]. IEEE Journal of Solid-state Circuits, 1996, 31(10): 749-752
[35] Hung Chih-Ming, Floyd B A, Park N, etal. Fully integrated 5.35 GHz CMOS VCOs and prescaler[J]. IEEE Trans Microwave Theory Tech, 2001, 44(1): 17-22