TD-SCDMA分频器的研究与设计
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摘要
随着3G的到来,通信系统及通信行业产生了很大变化,TD-SCDMA作为3G标准之一已经开始应用。手机终端中的射频芯片是TD发展的一项重要瓶颈。本文首先分析了射频芯片中重要模块收发信机的结构,通过对含中频收发信机与零中频的收发信机的比较,确定使用零中频收发信机结构,并对收发信机的主要参数进行了分析。
分析了锁相环原理,以及基于锁相环的频率合成原理。通过负反馈上分频器结构变化,产生不同的分频方式。分别研究了固定整数频率合成器、含双模分频器的频率合成器,以及含小数分频的频率合成器,分析了鉴相器、VCO、分频器对频率合成器整体性能的影响,并利用Matlab对TD-SCDMA锁相单环频率合成器进行了系统仿真。
分析了LC振荡器的主要性能参数和基本原理,并考虑了MOS管寄生参数对振荡器的影响。总结了VCO的设计方法,选择了互补型交叉耦合的LC振荡器结构,并对MOS管尺寸以及片外谐振网络的电容和电感进行了设计,通过Cadence公司的模拟电路仿真软件Spectre进行仿真验证。
介绍了鉴相鉴频器的工作原理和主要性能指标,给出了常用的几种PFD结构,包括预充电式、普通边沿触发式、TSPC动态结构和差分型边沿触发PFD。重点讨论了SCL结构的反相器和锁存器的特点和设计方法,它的优点是噪声低、增益大和转换速率高,非常适合于射频集成电路。
针对低功耗射频小数分频器结构进行重点分析,主要功耗和相位噪声来自于高频部分。分析分频器类型,综合考虑低功耗,功能设计等多方面因素,不再选取传统的数字逻辑结构双模分频器,而是改用更为先进的相位转换型双模分频器。分析相位转换器通过各路信号相位切换的方法将N/N+1双模切换移至较低工作频率,从而降低功耗。同时提出相位转换器在工作中会产生陷落毛刺的问题,如不能有效控制将影响电路功能。通过具体分析陷落毛刺产生的原因是由于各路信号相位失配所造成,两路切换信号没有找到合适的切换点。针对这种情况,提出了增加一个相位转换模块,由后一路信号上升沿驱动相位切换模块,在不增加太多设计和功耗的情况下较好地解决了该问题。通过对分频器相位噪声和功耗的分析,分频器相位噪声和功耗主要来自于第一级射频固定二分频器,确定该模块设计是降低功耗的关键。提出将注入锁定原理应用在固定二分频器上的可能性,将固定二分频器视为环形振荡器,通过合理设置该振荡器自由振荡频率,达到信号最大摆幅,通过信号振荡的方式降低功耗。采用CML结构电路设计模拟射频电路,分析CML电路低功耗,抗干扰特性,适合射频电路设计。设计射频固定二分频器,相位切换器,异步分频链,MASH型Delta-Sigma小数调制器,输出Buffer。分频器中部分模块工作在GHz以上,整个分频器可以实现5.056-5.750小数分频。
As the arrival of3G, communication system and communication industry produced very big change, TD-SCDMA3G has been used as one of the standard. The TD-RFchip is a bottleneck of TD-mobile. We firstly analyzes the RF chip module transceiver and receiver structure, with intermediate frequency transceiver and zero intermediate frequency transceiver comparison, determine the use of zero intermediate frequency transceiver and reciver structure, and the transceiver of the main parameters are analysed.
The phase lock loop frequency synthesizer principle was analyzed. There are different divid with different type feedback divider. The integrator frequency synthesizer, dual-mode frequency synthesizer and fractional frequency synthesizer was analyzed separately. There are some discuss on performance influence with PFD, VCO and divider. The whole TD-SCDMA frequency synthesizer system performance was simulated by Matlab.
The parameters and basic principle of LC oscillator were analyzed, and the influence of the MOS parasitical parameters to oscillator was considered. We summarize the VCO design approach, and the complementary cross coupled LC VCO is chosen, the MOS size and the resonance network out of the chip is designed. Then, the VCO circuit simulation was implemented by Spectre which is the analog circuit simulation tool of Cadence.
The principle and specification of phase frequency detectors(PFD) was analyzed. The structure of PFD, such as precharge PFD, common edge trigger PFD, TSPC dynamic structure PFD and SCL structure PFD was introduced. The characteristic and design approach of SCL inverter and latch was emphases discussed. The advantage is low noise, high gain and slew rate, which is very suitable for RFIC.
Aiming the low power RF decimal frequency divider structure are analyzed in detail, the main power consumption and phase noise from high frequency part. Analysis of frequency divider type, considering the low power consumption, the function design and other factors, no longer choose the traditional digital logic structure dual modulus divider, but switched to more advanced phase conversion type dual modulus divider. Phase converter through the signal phase switching method N/N+1switching to lower working frequency, thereby reducing power consumption. At the same time the forward phase converter at work will collapse the glitch issue. if not effectively control,The circuit will not work. Through the concrete analysis of collapse burr produced is due to signal the phase mismatch caused by the switching signal, the two did not find a suitable switching point. In view of this situation, use the Rising edge of second signal to the drive phase switching module, without adding too much design and the power consumption of the case to solve the problem better. The divider phase noise and power consumption analysis, frequency divider phase noise and power consumption are mainly from the first RF fixed two dividers, determines the module design is to reduce the power consumption of the key. The injection locking principle applied in the fixed two divider on the likelihood.The fixed two divider is looked as a ring oscillator, by reasonably setting the oscillator frequency of free oscillations, achieve maximum swing through the signal, signal oscillation mode to reduce power consumption. The structure of CML circuit is suitable for RF circuit design for low power and RF frequency. The design of RF fixed two frequency divider, phase switcher, asynchronous divider chain, MASH Delta-Sigma decimal modulator, the output Buffer. Divider module working in GHz above, the divider can be achieved5.056-5.750decimal frequency divider.
分析了锁相环原理,以及基于锁相环的频率合成原理。通过负反馈上分频器结构变化,产生不同的分频方式。分别研究了固定整数频率合成器、含双模分频器的频率合成器,以及含小数分频的频率合成器,分析了鉴相器、VCO、分频器对频率合成器整体性能的影响,并利用Matlab对TD-SCDMA锁相单环频率合成器进行了系统仿真。
分析了LC振荡器的主要性能参数和基本原理,并考虑了MOS管寄生参数对振荡器的影响。总结了VCO的设计方法,选择了互补型交叉耦合的LC振荡器结构,并对MOS管尺寸以及片外谐振网络的电容和电感进行了设计,通过Cadence公司的模拟电路仿真软件Spectre进行仿真验证。
介绍了鉴相鉴频器的工作原理和主要性能指标,给出了常用的几种PFD结构,包括预充电式、普通边沿触发式、TSPC动态结构和差分型边沿触发PFD。重点讨论了SCL结构的反相器和锁存器的特点和设计方法,它的优点是噪声低、增益大和转换速率高,非常适合于射频集成电路。
针对低功耗射频小数分频器结构进行重点分析,主要功耗和相位噪声来自于高频部分。分析分频器类型,综合考虑低功耗,功能设计等多方面因素,不再选取传统的数字逻辑结构双模分频器,而是改用更为先进的相位转换型双模分频器。分析相位转换器通过各路信号相位切换的方法将N/N+1双模切换移至较低工作频率,从而降低功耗。同时提出相位转换器在工作中会产生陷落毛刺的问题,如不能有效控制将影响电路功能。通过具体分析陷落毛刺产生的原因是由于各路信号相位失配所造成,两路切换信号没有找到合适的切换点。针对这种情况,提出了增加一个相位转换模块,由后一路信号上升沿驱动相位切换模块,在不增加太多设计和功耗的情况下较好地解决了该问题。通过对分频器相位噪声和功耗的分析,分频器相位噪声和功耗主要来自于第一级射频固定二分频器,确定该模块设计是降低功耗的关键。提出将注入锁定原理应用在固定二分频器上的可能性,将固定二分频器视为环形振荡器,通过合理设置该振荡器自由振荡频率,达到信号最大摆幅,通过信号振荡的方式降低功耗。采用CML结构电路设计模拟射频电路,分析CML电路低功耗,抗干扰特性,适合射频电路设计。设计射频固定二分频器,相位切换器,异步分频链,MASH型Delta-Sigma小数调制器,输出Buffer。分频器中部分模块工作在GHz以上,整个分频器可以实现5.056-5.750小数分频。
As the arrival of3G, communication system and communication industry produced very big change, TD-SCDMA3G has been used as one of the standard. The TD-RFchip is a bottleneck of TD-mobile. We firstly analyzes the RF chip module transceiver and receiver structure, with intermediate frequency transceiver and zero intermediate frequency transceiver comparison, determine the use of zero intermediate frequency transceiver and reciver structure, and the transceiver of the main parameters are analysed.
The phase lock loop frequency synthesizer principle was analyzed. There are different divid with different type feedback divider. The integrator frequency synthesizer, dual-mode frequency synthesizer and fractional frequency synthesizer was analyzed separately. There are some discuss on performance influence with PFD, VCO and divider. The whole TD-SCDMA frequency synthesizer system performance was simulated by Matlab.
The parameters and basic principle of LC oscillator were analyzed, and the influence of the MOS parasitical parameters to oscillator was considered. We summarize the VCO design approach, and the complementary cross coupled LC VCO is chosen, the MOS size and the resonance network out of the chip is designed. Then, the VCO circuit simulation was implemented by Spectre which is the analog circuit simulation tool of Cadence.
The principle and specification of phase frequency detectors(PFD) was analyzed. The structure of PFD, such as precharge PFD, common edge trigger PFD, TSPC dynamic structure PFD and SCL structure PFD was introduced. The characteristic and design approach of SCL inverter and latch was emphases discussed. The advantage is low noise, high gain and slew rate, which is very suitable for RFIC.
Aiming the low power RF decimal frequency divider structure are analyzed in detail, the main power consumption and phase noise from high frequency part. Analysis of frequency divider type, considering the low power consumption, the function design and other factors, no longer choose the traditional digital logic structure dual modulus divider, but switched to more advanced phase conversion type dual modulus divider. Phase converter through the signal phase switching method N/N+1switching to lower working frequency, thereby reducing power consumption. At the same time the forward phase converter at work will collapse the glitch issue. if not effectively control,The circuit will not work. Through the concrete analysis of collapse burr produced is due to signal the phase mismatch caused by the switching signal, the two did not find a suitable switching point. In view of this situation, use the Rising edge of second signal to the drive phase switching module, without adding too much design and the power consumption of the case to solve the problem better. The divider phase noise and power consumption analysis, frequency divider phase noise and power consumption are mainly from the first RF fixed two dividers, determines the module design is to reduce the power consumption of the key. The injection locking principle applied in the fixed two divider on the likelihood.The fixed two divider is looked as a ring oscillator, by reasonably setting the oscillator frequency of free oscillations, achieve maximum swing through the signal, signal oscillation mode to reduce power consumption. The structure of CML circuit is suitable for RF circuit design for low power and RF frequency. The design of RF fixed two frequency divider, phase switcher, asynchronous divider chain, MASH Delta-Sigma decimal modulator, the output Buffer. Divider module working in GHz above, the divider can be achieved5.056-5.750decimal frequency divider.
引文
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