基于CORDIC的离散三角变换快速算法及其实现研究
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摘要
离散三角变换（Discrete Trigonometic Transform, DTT）在信息处理，尤其是视频、图像处理领域具有非常重要的地位和应用，其快速算法及硬件实现一直是信息处理领域的研究热点。新视频压缩标准H.265/HEVC发布后，传统的典型点数DTT已不能满足实际应用要求，大点数（尤其是2n点）、可变点数的快速算法将成为该领域的研究热点。
在视频、图像处理领域，精确计算DTT的硬件实现方式已基本成熟，采用近似计算成为提高其计算速度的另一有效途径。随着使用者对图像品质、处理速度要求不断提高，采用一种编码方式已不能满足应用要求。视频、图像压缩编码正向多正交变换混合编码方向发展，设计出能实现多种正交变换且性能优良的通用架构（Unified architecture）是亟待解决的问题。
本文针对以上研究热点问题，对大点数（2n点）DTT的快速算法及其基于改进型非重叠CORDIC的硬件实现以及离散正交变换的通用架构展开研究，主要研究工作包括：
1、研究了以CORDIC作为变换核函数的任意2n点DTT快速算法。首先，通过奇偶分解推导出了以CORDIC作为变换核函数的任意2n点DCT-II和DST-II的快速算法，并给出了规律一致的信号流图；然后，根据正交变换的对偶原理得到了DCT-III和DST-III的快速算法及其信号流图，从而提出了一种新型的基于CORDIC的基-2DTT快速算法。与现有算法比较，该算法在硬件复杂度、可扩展性、流水线设计、模块化设计等性能指标上优于同类算法，且具有以下突出特点：适用于任意2n点的DTT；既有较低的算法复杂度又易于VLSI硬件实现；算法中CORDIC的旋转角度为等差数列；具有规则的蝶形运算结构和统一的缩放因子，易于实现流水线设计；支持原位运算等。
2、研究了基于非重叠CORDIC处理单元的DTT硬件实现方法。首先，针对传统非重叠CORDIC算法中迭代次数与计算精度相互制约的问题，提出了一种改进型非重叠CORDIC（MCORDIC），以牺牲极少精度为代价将迭代次数减少了50%；然后，根据所提出的算法中CORDIC的旋转角度为等差数列这一特点，采用复用设计和模块化设计思想，大幅度减少了计算DTT所需的CORDIC运算单元的数量和类型，理论上任意2n点的DTT仅需要一种类型CORDIC；在此基础上提出了一种新型DTT脉动阵列设计方法，基于该方法设计的脉动阵列在电路延迟、吞吐率、流水线操作及硬件复杂度等性能指标上优于其他类似架构，并解决了由于存在不同类型的基本运算单元（PE）而导致的计算时序不同步以及PE中存在多种算术运算等问题。
3、以所提出的快速算法为研究基础，对四种类型DTT之间的内在关系进行了探讨。利用相同点数的DTT具有相同的CORDIC运算单元这一特点，通过控制信号流向来实现不同类型DTT的计算，从而提出了一种基于CORDIC的DTT通用架构设计方法。所提出的方法适用于任意2n点DTT，可实现四种DTT的任意组合的通用架构，并且具有以下优点：具有统一的变换核函数，控制电路简单，硬件复用率高。利用该方法设计了具有代表性的几种通用架构，所设计的架构在硬件复杂度、控制复杂度、吞吐率、可扩展性、模块化程度、流水线设计等性能指标上优于现有通用架构。此外，还给出了DWHT/DCT-II和Haar-DWT/DCT-II通用架构的设计方法。
4、在Haar-DWT/DCT-II通用架构的基础上，研究了基于图像内容的压缩编码硬件实现架构。该架构以图像的JND值为判断依据有选择的进行图像压缩编码。为解决JND计算复杂度高、难于硬件实现的问题，提出了一种基于Haar-DWT的近似计算JND算法，该算法虽然只得到JND的近似解，却大幅度降低了计算复杂度。设计了可实现两种工作模式（近似计算或非近似计算）的可重构DCT-II架构。研究了基于图像内容压缩编码的控制方案、工作模式选取的参考位置和JND阈值的选取方法。实验结果表明该压缩编码架构切实可行。所设计的压缩编码硬件实现架构中没有复杂的算术运算，计算复杂度非常低，因此非常易于VLSI硬件实现。
本文提出了一种新型的以CORDIC作为变换核函数的DTT快速算法，为研究DTT快速算法提供了新的研究思路和方法。研究的近似计算DTT的VLSI实现方式及其通用架构可以满足视频、图像压缩领域目前的需求，并符合未来该领域的发展方向。正如FFT的提出使得DFT在实际应用中得到飞跃性的发展，具有类似FFT特点的DTT快速算法也将使得DTT得到更广泛的应用。论文所研究内容既具有理论研究的前瞻性又具有现实的应用价值。
Discrete trigonometric transforms (DTTs) play a very important role in information processing, especially for video and image processing. Therefore, their fast algorithms and VLSI hardware implementations have been hot research field. After the new video compression standard H.265/HEVC published, conventional fast algorithms of the DTTs have been unable to meet the application requirements, large-point (especially for2n-points) and variable-point fast algorithms will become research hot.
In video and image processing applications, the hardware implementation architectures for accurately calculating the DTTs have been mature. Approximate calculating instead of accurate calculating will become another way to improve the computing speed. Using a single compression coding cannot meet people's increasing demands in video and image processing. Therefore, developing the hybrid compression coding methods and their corespording unified-architectures for a variety of orthogonal transforms are urgent problem.
For the above hot research problems, the research work will focus on the large point (e.g.,2n-points) fast algorithms of the DTTs, the unfolded CORDIC based approximation implementation for DTT computation and the unified architectures of the DTTs.
The major contribution of the work includes:
1. The CORDIC-based radix-2fast algorithms of the DTTs are studied. In this paper, the CORDIC algorithm is used as the transform kernel function and the fast algorithms for any2n-point DCT-II and DST-II are developed using odd-even decomposition method. On this basis, any2n-point DCT-III and DST-III fast algorithms and their signal-flows are deduced according to the principle of duality of the orthogonal transforms. Thus, new CORDIC-based radix-2fast algorithms of the DTTs are proposed. The proposed fast algorithms are better than the existing algorithms in hardware complexity, scalability, pipelinablity and modularity. Furthermore, the proposed algorithms also have some distinguish advantages, such as suitable for any2n-point and various types of DTTs, low hardware complexity and suitable for VLSI implementation, arithmetic-sequence rotation angles of the CORDICs, uniform scaling factor and regular data flow, suitable for pipelineability and supporting in-place operation and so on.
2. The hardware implementation for the proposed fast algorithms of the DTTs are studied. Firstly, in order to solve the problem between the iterations and the computation precision in the traditional non-overlap CORDIC algorithm, an improved non-overlap CORDIC algorithm (MCORDIC) is developed. This improved algorithm can reduce the iteration number of the unfolded CORDIC by50%at a little cost of accuracy. Secondly, since the rotation angles of the CORDIC in proposed algorithms are arithmetic sequence, the required number and types of the CORDIC can be significantly reduced by using modular design and reusable design. Theoretically speaking, any2n-point DTT can be achieved using only one type of CORDIC. Then an novel approach for designing the systolic array of the DTTs is developed. The proposed systolic array is superior to other similar structures in lantency, throughput, pipelinable and hardware complexity. Besides, this design approach can be used to solve the traditional problems of the DTT systolic arrays. Moreover, using row-column decomposition we propose a hardware utilization efficiency2-D DCT-II/DCT-III structure.
3. The intrinsic relationship among proposed CORDIC-based DTTs is used to deduce a universal design approach for the DTT computation by taking full advantage of the nature of trigonometric functions. This approach uses the characteristic, which is that the same point DTTs have identical CORDIC cells, to achieve the computation of different DTTs by controlling dataflow. This design approach is suitable for any2n-point DTTs and any combination among four kinds of DTTs. Moreover, the proposed approach not only have unique transform kernel function, simple control circuit, but also has higher hardware reusing rate. Afterwards, several representative unified architectures are designed. The proposed unified architectures of the DTTs are superior to the existing unified architectures in hardware complexity, control complexity, throughput, scalability, modularity and pipelinability. In addition, we also develop the DWHT/DCT-II and Haar-DWT/DCT-II unified architecture design approach.
4. The architecture for data-dependent compression coding is studied based on the Haar-DWT/DCT-II unified architecture. The JND is used as the threshold for selecting the compressing modes. To solve problems of the conventional JND algorithm, a approximated JND based on Haar-DWT is proposed. Though the proposed JND algorithm only obtain the approximated value of the JND, it sharply reduces the arithmetic complexity. Reuseable DCT-II architecture can be used to work in two oporating modes (approximate calculation mode and accurate calculation mode). Then, the control scheme is studied, and the referenced position and the JND threshold value of operate modes are slectected based on a lot of experiments. The proposed architecture for data-based compression coding is approved. The proposed architecture has very low hardware complexity without complicated arithmetic elements, so it is very suitable for the VLSI implementation.
This paper proposes fast algorithms of the DTTs that use the CORDIC as kernel transfer function, which provides novel research ideas and methods for researching the fast algorithms of the DTT. In video, image compression field, the proposed alogorihms and architectures meet the requirements of the application and future development direction. As the Cooley-Tukey FFT puts forward the DFT in practical applications, the DTTs will be more widely used in the field of digital signal processing due to the fast algorithms that have the similar characteristics with the FFT. Therefore, these studies not only have theoretical prospective, but also have the practical application value.
在视频、图像处理领域，精确计算DTT的硬件实现方式已基本成熟，采用近似计算成为提高其计算速度的另一有效途径。随着使用者对图像品质、处理速度要求不断提高，采用一种编码方式已不能满足应用要求。视频、图像压缩编码正向多正交变换混合编码方向发展，设计出能实现多种正交变换且性能优良的通用架构（Unified architecture）是亟待解决的问题。
本文针对以上研究热点问题，对大点数（2n点）DTT的快速算法及其基于改进型非重叠CORDIC的硬件实现以及离散正交变换的通用架构展开研究，主要研究工作包括：
1、研究了以CORDIC作为变换核函数的任意2n点DTT快速算法。首先，通过奇偶分解推导出了以CORDIC作为变换核函数的任意2n点DCT-II和DST-II的快速算法，并给出了规律一致的信号流图；然后，根据正交变换的对偶原理得到了DCT-III和DST-III的快速算法及其信号流图，从而提出了一种新型的基于CORDIC的基-2DTT快速算法。与现有算法比较，该算法在硬件复杂度、可扩展性、流水线设计、模块化设计等性能指标上优于同类算法，且具有以下突出特点：适用于任意2n点的DTT；既有较低的算法复杂度又易于VLSI硬件实现；算法中CORDIC的旋转角度为等差数列；具有规则的蝶形运算结构和统一的缩放因子，易于实现流水线设计；支持原位运算等。
2、研究了基于非重叠CORDIC处理单元的DTT硬件实现方法。首先，针对传统非重叠CORDIC算法中迭代次数与计算精度相互制约的问题，提出了一种改进型非重叠CORDIC（MCORDIC），以牺牲极少精度为代价将迭代次数减少了50%；然后，根据所提出的算法中CORDIC的旋转角度为等差数列这一特点，采用复用设计和模块化设计思想，大幅度减少了计算DTT所需的CORDIC运算单元的数量和类型，理论上任意2n点的DTT仅需要一种类型CORDIC；在此基础上提出了一种新型DTT脉动阵列设计方法，基于该方法设计的脉动阵列在电路延迟、吞吐率、流水线操作及硬件复杂度等性能指标上优于其他类似架构，并解决了由于存在不同类型的基本运算单元（PE）而导致的计算时序不同步以及PE中存在多种算术运算等问题。
3、以所提出的快速算法为研究基础，对四种类型DTT之间的内在关系进行了探讨。利用相同点数的DTT具有相同的CORDIC运算单元这一特点，通过控制信号流向来实现不同类型DTT的计算，从而提出了一种基于CORDIC的DTT通用架构设计方法。所提出的方法适用于任意2n点DTT，可实现四种DTT的任意组合的通用架构，并且具有以下优点：具有统一的变换核函数，控制电路简单，硬件复用率高。利用该方法设计了具有代表性的几种通用架构，所设计的架构在硬件复杂度、控制复杂度、吞吐率、可扩展性、模块化程度、流水线设计等性能指标上优于现有通用架构。此外，还给出了DWHT/DCT-II和Haar-DWT/DCT-II通用架构的设计方法。
4、在Haar-DWT/DCT-II通用架构的基础上，研究了基于图像内容的压缩编码硬件实现架构。该架构以图像的JND值为判断依据有选择的进行图像压缩编码。为解决JND计算复杂度高、难于硬件实现的问题，提出了一种基于Haar-DWT的近似计算JND算法，该算法虽然只得到JND的近似解，却大幅度降低了计算复杂度。设计了可实现两种工作模式（近似计算或非近似计算）的可重构DCT-II架构。研究了基于图像内容压缩编码的控制方案、工作模式选取的参考位置和JND阈值的选取方法。实验结果表明该压缩编码架构切实可行。所设计的压缩编码硬件实现架构中没有复杂的算术运算，计算复杂度非常低，因此非常易于VLSI硬件实现。
本文提出了一种新型的以CORDIC作为变换核函数的DTT快速算法，为研究DTT快速算法提供了新的研究思路和方法。研究的近似计算DTT的VLSI实现方式及其通用架构可以满足视频、图像压缩领域目前的需求，并符合未来该领域的发展方向。正如FFT的提出使得DFT在实际应用中得到飞跃性的发展，具有类似FFT特点的DTT快速算法也将使得DTT得到更广泛的应用。论文所研究内容既具有理论研究的前瞻性又具有现实的应用价值。
Discrete trigonometric transforms (DTTs) play a very important role in information processing, especially for video and image processing. Therefore, their fast algorithms and VLSI hardware implementations have been hot research field. After the new video compression standard H.265/HEVC published, conventional fast algorithms of the DTTs have been unable to meet the application requirements, large-point (especially for2n-points) and variable-point fast algorithms will become research hot.
In video and image processing applications, the hardware implementation architectures for accurately calculating the DTTs have been mature. Approximate calculating instead of accurate calculating will become another way to improve the computing speed. Using a single compression coding cannot meet people's increasing demands in video and image processing. Therefore, developing the hybrid compression coding methods and their corespording unified-architectures for a variety of orthogonal transforms are urgent problem.
For the above hot research problems, the research work will focus on the large point (e.g.,2n-points) fast algorithms of the DTTs, the unfolded CORDIC based approximation implementation for DTT computation and the unified architectures of the DTTs.
The major contribution of the work includes:
1. The CORDIC-based radix-2fast algorithms of the DTTs are studied. In this paper, the CORDIC algorithm is used as the transform kernel function and the fast algorithms for any2n-point DCT-II and DST-II are developed using odd-even decomposition method. On this basis, any2n-point DCT-III and DST-III fast algorithms and their signal-flows are deduced according to the principle of duality of the orthogonal transforms. Thus, new CORDIC-based radix-2fast algorithms of the DTTs are proposed. The proposed fast algorithms are better than the existing algorithms in hardware complexity, scalability, pipelinablity and modularity. Furthermore, the proposed algorithms also have some distinguish advantages, such as suitable for any2n-point and various types of DTTs, low hardware complexity and suitable for VLSI implementation, arithmetic-sequence rotation angles of the CORDICs, uniform scaling factor and regular data flow, suitable for pipelineability and supporting in-place operation and so on.
2. The hardware implementation for the proposed fast algorithms of the DTTs are studied. Firstly, in order to solve the problem between the iterations and the computation precision in the traditional non-overlap CORDIC algorithm, an improved non-overlap CORDIC algorithm (MCORDIC) is developed. This improved algorithm can reduce the iteration number of the unfolded CORDIC by50%at a little cost of accuracy. Secondly, since the rotation angles of the CORDIC in proposed algorithms are arithmetic sequence, the required number and types of the CORDIC can be significantly reduced by using modular design and reusable design. Theoretically speaking, any2n-point DTT can be achieved using only one type of CORDIC. Then an novel approach for designing the systolic array of the DTTs is developed. The proposed systolic array is superior to other similar structures in lantency, throughput, pipelinable and hardware complexity. Besides, this design approach can be used to solve the traditional problems of the DTT systolic arrays. Moreover, using row-column decomposition we propose a hardware utilization efficiency2-D DCT-II/DCT-III structure.
3. The intrinsic relationship among proposed CORDIC-based DTTs is used to deduce a universal design approach for the DTT computation by taking full advantage of the nature of trigonometric functions. This approach uses the characteristic, which is that the same point DTTs have identical CORDIC cells, to achieve the computation of different DTTs by controlling dataflow. This design approach is suitable for any2n-point DTTs and any combination among four kinds of DTTs. Moreover, the proposed approach not only have unique transform kernel function, simple control circuit, but also has higher hardware reusing rate. Afterwards, several representative unified architectures are designed. The proposed unified architectures of the DTTs are superior to the existing unified architectures in hardware complexity, control complexity, throughput, scalability, modularity and pipelinability. In addition, we also develop the DWHT/DCT-II and Haar-DWT/DCT-II unified architecture design approach.
4. The architecture for data-dependent compression coding is studied based on the Haar-DWT/DCT-II unified architecture. The JND is used as the threshold for selecting the compressing modes. To solve problems of the conventional JND algorithm, a approximated JND based on Haar-DWT is proposed. Though the proposed JND algorithm only obtain the approximated value of the JND, it sharply reduces the arithmetic complexity. Reuseable DCT-II architecture can be used to work in two oporating modes (approximate calculation mode and accurate calculation mode). Then, the control scheme is studied, and the referenced position and the JND threshold value of operate modes are slectected based on a lot of experiments. The proposed architecture for data-based compression coding is approved. The proposed architecture has very low hardware complexity without complicated arithmetic elements, so it is very suitable for the VLSI implementation.
This paper proposes fast algorithms of the DTTs that use the CORDIC as kernel transfer function, which provides novel research ideas and methods for researching the fast algorithms of the DTT. In video, image compression field, the proposed alogorihms and architectures meet the requirements of the application and future development direction. As the Cooley-Tukey FFT puts forward the DFT in practical applications, the DTTs will be more widely used in the field of digital signal processing due to the fast algorithms that have the similar characteristics with the FFT. Therefore, these studies not only have theoretical prospective, but also have the practical application value.
引文
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