相干布居数囚禁原子钟性能研究
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摘要
相干布居数囚禁(Coherent Population Trapping, CPT)原子钟具有体积小、功耗低、长期频率稳定度较好等特点,可广泛用于微小卫星、水下通讯设备、通信基站、导弹等领域。以改善CPT原子钟的性能,减小其体积和功耗为目标,论文对CPT原子钟的各组成部分性能展开研究和优化,工作主要涉及CPT原子钟的伺服电路设计、信号检测电路优化、锁频环路优化和物理系统优化四部分,成果包括：
1.完成CPT原子钟伺服电路的数字化设计和实现。设计出高度数字化的伺服电路,并通过现场可编程门阵列实现。减小了原子钟电路的体积和功耗,降低了温度漂移,提高了抗干扰能力,并方便了各种智能化操作的执行。该工作还为设计伺服电路的专用集成芯片打下基础。
2.改进信号检测电路,包括光检电路、滤波器和相敏解调电路。改进了光检放大电路,既提高了信号检测的精度,又扩大了动态范围。设计了数字滤波器代替模拟滤波器,提高了短期频率稳定度,降低了功耗；与传统数字滤波器相比,所设计的数字滤波器所占用的逻辑资源大幅度减少。设计并实现了两种对相敏解调电路的优化方案。这两种方案完全省去了数字滤波器,在保持短期频率稳定度基本不变的同时,使设计大为简化,对数字伺服的主控芯片功能要求降低,能大幅降低功耗,适用于对低功耗有特殊要求的原子钟。
3.优化锁频环路,改进锁频控制器、频率扫描方式并优化环路参数。设计了多种变步长锁频控制器,克服了传统锁频控制器具有多个平衡点、存在稳态误差、纠偏速度和短期频率稳定度不能兼容等缺点。通过算法实现了对受到振动和冲击等情况造成的频率偏差进行识别和校正,提高了变步长锁频控制器在拟合区之外和受到外界干扰时恢复正常工作状态的能力。通过改进锁频控制器的结构,消除了晶振频率漂移速率变化引起的频率误差,提高了原子钟频率的长期稳定性。对锁频环路积分时间的影响进行分析,得出了小型CPT原子钟和微型CPT原子钟适用的不同控制速率,并提高了短期频率稳定度。通过改变锁频环路的频率扫描方式,提高了CPT原子钟的频率复现性,并使输出频率精确可调。
4.改进物理系统,提高原子钟性能。设计研制出用于垂直腔面发射半导体激光器的精密温控电路。研究了吸收泡中不同缓冲气体配比时原子钟的温度频移,通过调节配比、改变吸收泡工作温度,抑制了温度频移。通过计算和实验得出了零温度频移点和缓冲气体配比的关系,据此可根据吸收泡的工作温度选取最佳配比。对C场线圈结构进行改进,提高了吸收泡内磁场的均匀性和稳定性。
Passive coherent population trapping (CPT) atomic clocks can be widely used in microsatellites, submarine communication devices, telecommunication stations, missile guidance, etc., due to its small scale, low power dissipation and relatively good long-term frequency stability. This work focused on the research and improvement of components and performances of CPT atomic clocks. The aim is to get better frequency stability, smaller size and lower power dissipation, so as to improve the property and expand the application of CPT atomic clocks. The work involves the design of servo circuit, and the improvement of signal detecting circuit, frequency locking loop and physical package. Significant results are as follows.
1. The digital servo of CPT atomic clocks is designed and realized by using a field programmable gates array (FPGA). The highly digitalized servo minimized the size and power dissipation of the atomic clock, decreased the total temperature drift of devices, enhanced the anti-jamming ability, and supplied a convenient environment to implement intelligent operations. Besides, the design provided a scheme easily to be transformed into application specific integrated circuit (ASIC) for miniature CPT atomic clock.
2. The signal detection circuit, including the optical detection circuit, the filters, and the phase-sensitivity demodulation circuit is improved,. The improved optical detection circuit covered both wide dynamic range and high sensitivity. We designed a digital filter to replace the original analog one, which improved the short-term stability and decreased the power dissipation. The logic resource required by the digital filter is highly saved by advancing its structure, compared to the traditional digital filter. We also developed two kinds of phase-sensitivity demodulation schemes which need no filters. Though the short-term stability slightly decreased, the selection or design of main control chip is simplified, so the power dissipation is potential to be highly decreased. Therefore they are especially fit for the applications require extremely low power dissipation.
3. The frequency locking loop is optimized by means of improving frequency locker, frequency scanning method and parameters fo the loop. We developed several variable-step frequency lockers to replace the old ones, which had the shortages of multiple stationary points, stead-state error, and lack of balance between correction speed and short-term stability. Algorithms are designed to recognize and handle circumstances that the clock is suffering vibration or shock. The stead-state error caused by the inconstant frequency drift speed of oscillator is also eliminated by changing the locker's structure, so that the long-term stability is improved. We also analyzed the influence of integration time of the frequency locking loop, indentified best control speeds for small size and miniature CPT atomic clocks, relatively, and improved the short-term stability. The frequency retrace is also improved by changing the frequency scanning method, and the frequency accuracy is simultaneously enhanced.
4. The structure of physical package is developed and the performance of the atomic clock is improved. We designed a special precise temperature-control system for vertical-cavity surface-emitting lasers (VCSEL). We also suppressed the temperature-frequency drift by studying the drift in different buffer gases ratios, modulating the ratio, and changing the operation temperature of the vapor cell. The work enables people to modulate the buffer gases ratio into best point according to the operation temperature the cell required, by the way of calculating the relation between inversion temperature and ratio. The work on C-field coil structure improved the uniformity and stability of magnetic field in the cell.
1.完成CPT原子钟伺服电路的数字化设计和实现。设计出高度数字化的伺服电路,并通过现场可编程门阵列实现。减小了原子钟电路的体积和功耗,降低了温度漂移,提高了抗干扰能力,并方便了各种智能化操作的执行。该工作还为设计伺服电路的专用集成芯片打下基础。
2.改进信号检测电路,包括光检电路、滤波器和相敏解调电路。改进了光检放大电路,既提高了信号检测的精度,又扩大了动态范围。设计了数字滤波器代替模拟滤波器,提高了短期频率稳定度,降低了功耗；与传统数字滤波器相比,所设计的数字滤波器所占用的逻辑资源大幅度减少。设计并实现了两种对相敏解调电路的优化方案。这两种方案完全省去了数字滤波器,在保持短期频率稳定度基本不变的同时,使设计大为简化,对数字伺服的主控芯片功能要求降低,能大幅降低功耗,适用于对低功耗有特殊要求的原子钟。
3.优化锁频环路,改进锁频控制器、频率扫描方式并优化环路参数。设计了多种变步长锁频控制器,克服了传统锁频控制器具有多个平衡点、存在稳态误差、纠偏速度和短期频率稳定度不能兼容等缺点。通过算法实现了对受到振动和冲击等情况造成的频率偏差进行识别和校正,提高了变步长锁频控制器在拟合区之外和受到外界干扰时恢复正常工作状态的能力。通过改进锁频控制器的结构,消除了晶振频率漂移速率变化引起的频率误差,提高了原子钟频率的长期稳定性。对锁频环路积分时间的影响进行分析,得出了小型CPT原子钟和微型CPT原子钟适用的不同控制速率,并提高了短期频率稳定度。通过改变锁频环路的频率扫描方式,提高了CPT原子钟的频率复现性,并使输出频率精确可调。
4.改进物理系统,提高原子钟性能。设计研制出用于垂直腔面发射半导体激光器的精密温控电路。研究了吸收泡中不同缓冲气体配比时原子钟的温度频移,通过调节配比、改变吸收泡工作温度,抑制了温度频移。通过计算和实验得出了零温度频移点和缓冲气体配比的关系,据此可根据吸收泡的工作温度选取最佳配比。对C场线圈结构进行改进,提高了吸收泡内磁场的均匀性和稳定性。
Passive coherent population trapping (CPT) atomic clocks can be widely used in microsatellites, submarine communication devices, telecommunication stations, missile guidance, etc., due to its small scale, low power dissipation and relatively good long-term frequency stability. This work focused on the research and improvement of components and performances of CPT atomic clocks. The aim is to get better frequency stability, smaller size and lower power dissipation, so as to improve the property and expand the application of CPT atomic clocks. The work involves the design of servo circuit, and the improvement of signal detecting circuit, frequency locking loop and physical package. Significant results are as follows.
1. The digital servo of CPT atomic clocks is designed and realized by using a field programmable gates array (FPGA). The highly digitalized servo minimized the size and power dissipation of the atomic clock, decreased the total temperature drift of devices, enhanced the anti-jamming ability, and supplied a convenient environment to implement intelligent operations. Besides, the design provided a scheme easily to be transformed into application specific integrated circuit (ASIC) for miniature CPT atomic clock.
2. The signal detection circuit, including the optical detection circuit, the filters, and the phase-sensitivity demodulation circuit is improved,. The improved optical detection circuit covered both wide dynamic range and high sensitivity. We designed a digital filter to replace the original analog one, which improved the short-term stability and decreased the power dissipation. The logic resource required by the digital filter is highly saved by advancing its structure, compared to the traditional digital filter. We also developed two kinds of phase-sensitivity demodulation schemes which need no filters. Though the short-term stability slightly decreased, the selection or design of main control chip is simplified, so the power dissipation is potential to be highly decreased. Therefore they are especially fit for the applications require extremely low power dissipation.
3. The frequency locking loop is optimized by means of improving frequency locker, frequency scanning method and parameters fo the loop. We developed several variable-step frequency lockers to replace the old ones, which had the shortages of multiple stationary points, stead-state error, and lack of balance between correction speed and short-term stability. Algorithms are designed to recognize and handle circumstances that the clock is suffering vibration or shock. The stead-state error caused by the inconstant frequency drift speed of oscillator is also eliminated by changing the locker's structure, so that the long-term stability is improved. We also analyzed the influence of integration time of the frequency locking loop, indentified best control speeds for small size and miniature CPT atomic clocks, relatively, and improved the short-term stability. The frequency retrace is also improved by changing the frequency scanning method, and the frequency accuracy is simultaneously enhanced.
4. The structure of physical package is developed and the performance of the atomic clock is improved. We designed a special precise temperature-control system for vertical-cavity surface-emitting lasers (VCSEL). We also suppressed the temperature-frequency drift by studying the drift in different buffer gases ratios, modulating the ratio, and changing the operation temperature of the vapor cell. The work enables people to modulate the buffer gases ratio into best point according to the operation temperature the cell required, by the way of calculating the relation between inversion temperature and ratio. The work on C-field coil structure improved the uniformity and stability of magnetic field in the cell.
引文
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