图形化SOI射频功率器件研究
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摘要
迅速发展的无线通讯技术推动射频集成电路向着高速、低功耗和更高集成度的方向发展,这时,传统的GaAs和体硅衬底平台将面临散热和功率耗散等棘手的问题。在这种情况下关于新的衬底材料的研究应运而生。另一方面,由于SOI(Silicon-on-Insulator)技术具有更好的隔离性能、理想的亚阈值特性和较低的功率消耗等特点,日益成为半导体行业发展的主流技术。但是,SOI技术面临浮体效应和自加热效应。
而采用埋氧层是间断的图形化SOI衬底是解决浮体效应和自加热效应的最简单的方法。鉴于此,本文对图形化SOI衬底上的射频功率器件LDMOSFET进行了系统研究。
本文提出了沟道下方开硅窗口的图形化SOI LDMOSFET结构,并且进行了工艺和电学性能仿真。采用工艺模拟软件TSUPREM4与器件模拟软件MEDICI对工艺过程和器件结构进行了优化,而且对器件的电学性能进行了仿真。新结构呈现良好的性能:器件温度降低,没有负的微分电导现象出现,输出特性曲线平滑;2GHz时,小信号增益为11dB;截止频率和最大振荡频率分别达到10GHz和40GHz。
利用软件L-edit进行了版图设计,与常规SOI CMOS工艺相比,主要增加了二块模板:其一是为了制备图形化SOI衬底,其二是定义漂移区。同时,结合TSUPREM4仿真结果,设计了与常规1μm SOI CMOS工艺兼容的工艺流程。
采用低剂量掩膜注氧隔离技术准备了低缺陷的图形化SOI衬底,在此衬底上同时制备了图形化SOI、体连接SOI和体硅LDMOSFET。采用open-short技术去除了pads对器件S参数的影响。建立了拓扑结构,进行参数提取,建立了小信号等效电路模型。测试分析结果表明,沟道下方埋氧层断开的图形化SOI LDMOSFET的开态输出特性曲线平滑、无曲翘现象,开态和关态击穿电压可分别达到8V和13V。
The continuing growth of mobile communications markets is motivating a steady evolution of radio frequency integrated circuits (RFIC's), and the explosion of interest in high integrated-density, high speed and low power-consumed RFIC is driving the research of novel substrate platforms for the replacement of conventional GaAs or bulk silicon technology, which will reach their physical limits. On the other hand, SOI (Silicon-on-Insulator) is becoming mainstream technology in sub-micron semiconductor technology due to its completely dielectric isolation and ideal sub-threshold slope, as well as low power-consumption. However, SOI technology has to face the problems of floating body effects and self-heating effects.Patterned SOI technology is the simplest way to overcome floating body effects and self-heating effects. In this thesis, the application of patterned SOI (PSOI) technology to RF power device was investigated systematically.PSOI LDMOS structure with a silicon window underneath p body was proposed, and TSUPREM4 and MEDICI simulation were presented. The proposed structure showed excellent electrical performance including ideal output characteristics immunity of kink effect and self-heating effect, the small signal gain reaching to 1 ldB at 2GHz, and the cut off frequency and the maximal oscillating frequency up to 10GHz and 40GHz respectively.Masks and flowing process were designed with the help of simulation results. Minimal changes were introduced to the process in order to demonstrate potential compatibility with conventional lum SOI CMOS technology. There were two principal modifications, one was to prepare patterned SOI substrate, the other was to define n- drift region.
The proposed structures were fabricated on PSOI substrates prepared by selective masked SIMOX technology. Body contact SOI LDMOSFETs and bulk counterparts were also integrated in the same die to show the flexibility of PSOI technology. PSOI LDMOSFET exhibited good DC electrical performance. The output curves were flat, showing no kink effects and self-heating effects. The on-state breakdown voltage of 8V and the off-state breakdown voltage of 13V were achieved. The leakage current was about one order lower than that of bulk counterpart. RF characterization was performed using coplanar wave-guide probes, and the calibration to the probe pads was obtained through two-step de-embedding technology. The small signal gain could reach to 6dB at 1GHz, and cut off frequency up to 8GHz. The small signal equivalent circuit model was established for the further investigation on power amplifier applications.In addition, the body contact technology usually adopted by power devices was improved, where body contact regions were formed by p body implantation, that is, source region was selectively implanted by n+ in order to conserve some p type regions. SOI LDMOSFETs fabricated with this body contact technology showed no kink effects when gate finger length was 10um or 20um, but kink effects appeared at the gate finger length of 50u.m.At last, high k dielectric films on SOI substrates for the replacement of conventional gate dielectric of SiO2 was studied. Post deposition anneal (PDA) can effectively reduce traps density, make surface smooth, but lead to the growth of SiO2 at the interface. Hf silicate or Hf silicide were not found at the interface.
而采用埋氧层是间断的图形化SOI衬底是解决浮体效应和自加热效应的最简单的方法。鉴于此,本文对图形化SOI衬底上的射频功率器件LDMOSFET进行了系统研究。
本文提出了沟道下方开硅窗口的图形化SOI LDMOSFET结构,并且进行了工艺和电学性能仿真。采用工艺模拟软件TSUPREM4与器件模拟软件MEDICI对工艺过程和器件结构进行了优化,而且对器件的电学性能进行了仿真。新结构呈现良好的性能:器件温度降低,没有负的微分电导现象出现,输出特性曲线平滑;2GHz时,小信号增益为11dB;截止频率和最大振荡频率分别达到10GHz和40GHz。
利用软件L-edit进行了版图设计,与常规SOI CMOS工艺相比,主要增加了二块模板:其一是为了制备图形化SOI衬底,其二是定义漂移区。同时,结合TSUPREM4仿真结果,设计了与常规1μm SOI CMOS工艺兼容的工艺流程。
采用低剂量掩膜注氧隔离技术准备了低缺陷的图形化SOI衬底,在此衬底上同时制备了图形化SOI、体连接SOI和体硅LDMOSFET。采用open-short技术去除了pads对器件S参数的影响。建立了拓扑结构,进行参数提取,建立了小信号等效电路模型。测试分析结果表明,沟道下方埋氧层断开的图形化SOI LDMOSFET的开态输出特性曲线平滑、无曲翘现象,开态和关态击穿电压可分别达到8V和13V。
The continuing growth of mobile communications markets is motivating a steady evolution of radio frequency integrated circuits (RFIC's), and the explosion of interest in high integrated-density, high speed and low power-consumed RFIC is driving the research of novel substrate platforms for the replacement of conventional GaAs or bulk silicon technology, which will reach their physical limits. On the other hand, SOI (Silicon-on-Insulator) is becoming mainstream technology in sub-micron semiconductor technology due to its completely dielectric isolation and ideal sub-threshold slope, as well as low power-consumption. However, SOI technology has to face the problems of floating body effects and self-heating effects.Patterned SOI technology is the simplest way to overcome floating body effects and self-heating effects. In this thesis, the application of patterned SOI (PSOI) technology to RF power device was investigated systematically.PSOI LDMOS structure with a silicon window underneath p body was proposed, and TSUPREM4 and MEDICI simulation were presented. The proposed structure showed excellent electrical performance including ideal output characteristics immunity of kink effect and self-heating effect, the small signal gain reaching to 1 ldB at 2GHz, and the cut off frequency and the maximal oscillating frequency up to 10GHz and 40GHz respectively.Masks and flowing process were designed with the help of simulation results. Minimal changes were introduced to the process in order to demonstrate potential compatibility with conventional lum SOI CMOS technology. There were two principal modifications, one was to prepare patterned SOI substrate, the other was to define n- drift region.
The proposed structures were fabricated on PSOI substrates prepared by selective masked SIMOX technology. Body contact SOI LDMOSFETs and bulk counterparts were also integrated in the same die to show the flexibility of PSOI technology. PSOI LDMOSFET exhibited good DC electrical performance. The output curves were flat, showing no kink effects and self-heating effects. The on-state breakdown voltage of 8V and the off-state breakdown voltage of 13V were achieved. The leakage current was about one order lower than that of bulk counterpart. RF characterization was performed using coplanar wave-guide probes, and the calibration to the probe pads was obtained through two-step de-embedding technology. The small signal gain could reach to 6dB at 1GHz, and cut off frequency up to 8GHz. The small signal equivalent circuit model was established for the further investigation on power amplifier applications.In addition, the body contact technology usually adopted by power devices was improved, where body contact regions were formed by p body implantation, that is, source region was selectively implanted by n+ in order to conserve some p type regions. SOI LDMOSFETs fabricated with this body contact technology showed no kink effects when gate finger length was 10um or 20um, but kink effects appeared at the gate finger length of 50u.m.At last, high k dielectric films on SOI substrates for the replacement of conventional gate dielectric of SiO2 was studied. Post deposition anneal (PDA) can effectively reduce traps density, make surface smooth, but lead to the growth of SiO2 at the interface. Hf silicate or Hf silicide were not found at the interface.
引文
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