低压差分信号系统的设计
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摘要
低压差分信号(简称:LVDS)由于其高速度、低摆幅、低噪声、低电磁干扰、低功耗等优点,广泛的应用于各种对数据需求量大、传输速度高的设备或系统集成芯片(SOC)中,并日益成为当前接口电路技术中的一个重要研究领域。本文基于HJTC 0.18μmCMOS数模混合工艺技术,设计系统电路。
本论文的研究工作主要包括三个方面的内容:LVDS系统结构的研究,LVDS基本模块的实现和LVDS系统仿真。
系统结构部分主要讲述LVDS的技术参数、基本工作原理、体系结构及发射电路的设计,并根据系统结构将LVDS发射电路分为五大模块:数据接收、直流平衡、锁相环、7位串行化器及驱动器。其中重点介绍带隙基准电路、锁相环、7位串行化器和驱动器等电路的设计。
带隙基准电路的设计首先讲述其技术指标及原理,根据原理设计了本芯片需要的高速度带隙基准电流源,并给出了电路的仿真过程及结果。锁相环电路主要用来产生7相位时钟信号,即:输入参考时钟信号频率范围为32.5MHz～112MHz,输出7路时钟信号频率均与参考频率相同,但每一路信号的高低电位占空比均为1:7;其电路设计从数学建模开始,用matlab仿真得到了系统的线性参数,根据此参数具体设计压控振荡器(VCO)、鉴频/鉴相器(PFD)、电荷泵(CP)、低通滤波器(LPF)、分频器及电压调整器等电路,然后进行系统仿真,给出仿真结果。7位串行化器为多路复用结构,主要利用7相位时钟信号对数据信号进行7倍频,其具有高速度、高精度等特点。LVDS驱动电路首先介绍传统驱动电路,由于在长距离传输过程中会遇到衰减、干扰等问题,所以在传统驱动电路的基础上设计出的驱动器具有预加重功能。
设计完上述的五大模块后,进行系统优化,并给出优化后的仿真结果,结果表明电路能够达到设计的指标。
Low Voltage Differential Signaling(LVDS) can be widely used in all kinds of data on demand and high-speed transmission equipment, because it has many good characteristics. This paper based on HJTC 0.18μm mixed digital-analog technology.
The main study in this paper includes the following three aspects.The study of LVDS system architecture, circuit design, LVDS system simulation.
System architecture mainly concentrates technical parameters, basic principle, architecture and driver circuit, which is dvided into five parts: date reception, DC-balance, PLL, 7-bit serializer, driver circuit. And this paper focuses on bandgap reference circuit, PLL, 7-bit (serializer), driver circuit design.
Bandgap reference circuit: first, describing the technical specifications and principle, then, according to the theory and design of the chip to meet the needs of hign-speed bandgap current source, last, giving the circuit simulation process and the outcome. PLL is used to produce 7-phase clock signal, that is, the frequency range of input reference clock is 32.5MHz~112MHz, and 7-phase output clock signal with the same frequency, but the level of signal is 1:7. the circuit design from the beginning of mathematical modeling, using MATLAB simulation gets linear parameters of the system, then according to the parameters to design voltage controlled oscillator (VCO), frequency/ phase detector(PFD), charge pump(CP), a low-pass filter(LPF), divider and regulator, at last, PLL system-level simulation results are given. Data serializer with multi-stage multiplexers main using of the 7-phase clock signal multiplie the signal, with its high-speed, high-precisin features. Driver circuit divided into traditional LVDS divider and pre-emphasis LVDS divider, and pre-emphasis LVDS divider can solve the long-distance signal transmission with the attenuation and interference.
After finished the five modular designs, the entire system has been optimized. The simulation results show that the optimized circuit can achieve good indicators.
本论文的研究工作主要包括三个方面的内容:LVDS系统结构的研究,LVDS基本模块的实现和LVDS系统仿真。
系统结构部分主要讲述LVDS的技术参数、基本工作原理、体系结构及发射电路的设计,并根据系统结构将LVDS发射电路分为五大模块:数据接收、直流平衡、锁相环、7位串行化器及驱动器。其中重点介绍带隙基准电路、锁相环、7位串行化器和驱动器等电路的设计。
带隙基准电路的设计首先讲述其技术指标及原理,根据原理设计了本芯片需要的高速度带隙基准电流源,并给出了电路的仿真过程及结果。锁相环电路主要用来产生7相位时钟信号,即:输入参考时钟信号频率范围为32.5MHz～112MHz,输出7路时钟信号频率均与参考频率相同,但每一路信号的高低电位占空比均为1:7;其电路设计从数学建模开始,用matlab仿真得到了系统的线性参数,根据此参数具体设计压控振荡器(VCO)、鉴频/鉴相器(PFD)、电荷泵(CP)、低通滤波器(LPF)、分频器及电压调整器等电路,然后进行系统仿真,给出仿真结果。7位串行化器为多路复用结构,主要利用7相位时钟信号对数据信号进行7倍频,其具有高速度、高精度等特点。LVDS驱动电路首先介绍传统驱动电路,由于在长距离传输过程中会遇到衰减、干扰等问题,所以在传统驱动电路的基础上设计出的驱动器具有预加重功能。
设计完上述的五大模块后,进行系统优化,并给出优化后的仿真结果,结果表明电路能够达到设计的指标。
Low Voltage Differential Signaling(LVDS) can be widely used in all kinds of data on demand and high-speed transmission equipment, because it has many good characteristics. This paper based on HJTC 0.18μm mixed digital-analog technology.
The main study in this paper includes the following three aspects.The study of LVDS system architecture, circuit design, LVDS system simulation.
System architecture mainly concentrates technical parameters, basic principle, architecture and driver circuit, which is dvided into five parts: date reception, DC-balance, PLL, 7-bit serializer, driver circuit. And this paper focuses on bandgap reference circuit, PLL, 7-bit (serializer), driver circuit design.
Bandgap reference circuit: first, describing the technical specifications and principle, then, according to the theory and design of the chip to meet the needs of hign-speed bandgap current source, last, giving the circuit simulation process and the outcome. PLL is used to produce 7-phase clock signal, that is, the frequency range of input reference clock is 32.5MHz~112MHz, and 7-phase output clock signal with the same frequency, but the level of signal is 1:7. the circuit design from the beginning of mathematical modeling, using MATLAB simulation gets linear parameters of the system, then according to the parameters to design voltage controlled oscillator (VCO), frequency/ phase detector(PFD), charge pump(CP), a low-pass filter(LPF), divider and regulator, at last, PLL system-level simulation results are given. Data serializer with multi-stage multiplexers main using of the 7-phase clock signal multiplie the signal, with its high-speed, high-precisin features. Driver circuit divided into traditional LVDS divider and pre-emphasis LVDS divider, and pre-emphasis LVDS divider can solve the long-distance signal transmission with the attenuation and interference.
After finished the five modular designs, the entire system has been optimized. The simulation results show that the optimized circuit can achieve good indicators.
引文
[1]王胜,王新宇. LVDS技术及其在高速系统中的应用.遥测遥控, 2005, 26(4): 41~46
[2]赵忠文,曾峦,熊伟. LVDS技术分析和应用设计.装备指挥技术学院学报, 2001, 12(6): 89~93
[3]布明恩,杨文荣,张启平. 8位LVDS串行器的设计研究.微计算机信息, 2005, 21(1): 103~104
[4]马彦,冯勇. LVDS技术研究.电子计算机, 2002, Sum No.154: 20~23
[5] LVDS Owner’s. Manual, National Semiconductor Corp., 1997
[6] Jacob Reese.单端PECL与差分PECL的互连.电子产品世界, 2001, (10): 37~39.
[7]刘祥远,陈书明. LVDS高速I/O接口单元的设计研究.计算机工程与科学, 2001, 23(4): 52~56
[8]杨毅. MLVDS标准介绍及德州仪器SN 65MLVDS200系列.德州仪器(上海)有限公司
[9] LVDS Owner’s Manual. National Semiconductor Corp. 3rd Edition, spring 2004
[10] Mingdeng Chen, Jose Silva-Martinez, Michael Nix, Moises E. Robinson. Low-Voltage Low-Power LVDS Drivers. IEEE Journal of solid-state circuits, 2005, 40(2): 472~479
[11]宋正勋,谭宝华.低压差分信号技术.长春光学精密机械学院学报, 2000, 23(2): 33~36
[12]何捷,朱臻.一种具有温度补偿、高电源抑制比的带隙基准源.复旦学报(自然科学版), 2001, 40(1): 86~90
[13]孙顺根,吴晓波.一种高精度CMOS能隙基准电压源.微电子学, 2003, 33(2): 157~159
[14] Kujik. K. E. A precision reference voltage source. IEEE J. Solid-state Circuits, 1973, 8(3): 222~226
[15] Manku T., Wang Y. Temperature-independent output voltage generated by threshold voltage of an NMOS transistor. IEE Electronics Letters, 1995, 31(12): 935~936
[16] Tham K-M, Nagaraj K. A Low Supply Voltage Hige PSRR Voltage Reference in CMOS process. IEEE J. Solid-state Circuits, 1995, 30(2): 31~35
[17] Gianluca Giustolisi, Gaetano Palumbo. A detailed analysis of power-supplly noise attenuation in bandgap voltage references. Circuits and systemsⅠ: Fundanmental Theory and Appolications, IEEE Transaction on, 2003, 50(2): 185~197
[18]毕查德·拉扎维.模拟CMOS集成电路设计.陈贵灿,程军,张瑞智等.西安:西安交通大学出版社, 2003. 312~319
[19]刘韬,徐志伟.一种高电源抑制比CMOS能隙基准电压源.微电子学, 1999, 29(2): 128~131
[20]王福昌,鲁昆生.锁相技术.武昌:华中理工大学出版社, 1997. 10~30
[21] F. M. Gardner. Charge-Pump Phase-Locked Loops. IEEE Trans. Comm., 1980, vol. COM– 28: 1894~1858
[22] Roberto Pelliconi, David Iezzi, Andrea Baroni, et al. Power Efficient Charge Pump in Deep Submicron Standard CMOS Technology, IEEE Journal of Solid-State Circuits, 38(6), 2003: 1068~1071
[23] MansuriM, YangC. Jitter optimization based on phase-locked loop design parameters, IEEE J Sol Sta Circ, 2002, 37(11): 1375~1382
[24] Roland E. Best. Phase-locked loops design, simulation, and application. 5th北京:清华大学出版社, 2003. 19~23
[25]姜梅,刘三清,李乃平,陈钊.用于电荷泵锁相环的无源滤波器的设计.微电子学, 2003, 33(4): 339~343
[26] Benyong Zhang, Phillip E. Allen, Jeff M. Huard. A Fast Switching PLL Frequency Synthesizer With an On-Chip Passive Discrete-Time Loop Filter in 0.25-μm CMOS, IEEE Journal of Solid-State Circuits, 2003, 38(6): 855~865
[27] Yuping Toh, John A. McNeill. Single-Ended to Differential Converter for Multiple-Stage Single-Ended Ring Oscillators. IEEE Journal of Solid-State Circuits, 2003, 38(1): 141~145
[28]谢海情,曾健平,刘嘉晗,叶英. CMOS集成压控振荡器设计.宇航计测技术, 2006, 26(2): 47~50
[29] Manop Thamsirianunt, Tadeusz A. Kwasniewski. CMOS VCO’s for PLL Frequency Synthesis in GHz Digital Mobile Radio Communications. IEEE Journal of Solid-State Circuits, 1997, 32(10): 1511~1524
[30] Emad Hegazi, Asad A. Abidi. Varactor Characteristics, Oscillator Tuning Curves, and AM-FM Conversion. IEEE Journal of Solid-State Circuits, 2003, 38(6): 1033~1039
[31] M.-J. Edward Lee, William J. Dally Trey Greer et al.. Jitter Transfer Characteristics of Delay-Locked Loops-Theories and Design Techniques, IEEE Journal of Solid-State Circuits, 2003, 38(4): 614~621
[32] RazaviB. A study of phase noise in CMOS oscillators. IEEE J Sol Sta Circ, 1996; 31(3): 331~343
[33]宋屾,焦淑红,胡尔富.时钟抖动和相位噪声关系的研究.应用科技, 2006, 33(4): 1~6
[34] Ishibe M., Otaka S., Takeda J. ect. High Speed CMOS I/O Buffer Circuits. IEEE Journal of Solid State Circuit, 1992, 27(4):706~711
[35] Meng-Tzer Wong. A 2.5Gbps CMOS Serial Link Transceiver Design. 2002
[36] Kenpainen Stephen. BLVDS和GLVDS技术分析.电子产品世界, 2002, (3): 51~55
[37] Cole, C.B., Warwick, T.P. High speed digital transceivers: A challenge for manufacturing. Test Conference, 1999. Proceedings. International, 1999: 211~215
[38] Jun Cao, Momtaz, A, Vakilian, K., Green, M. OC-192 receiver in standard 0.18μm CMOS. Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International , 2002, 1: 250~464
[39] Jaeseo Lee, Jae-Won Lim, Sung-Jun Song. Design and implementation of CMOS LVDS 2.5 Gb/s transmitter and 1.3 Gb/s receiver for optical interconnections. 2001, 4(6-9): 702~705
[40] Benedetto, J.M, Oliver, A. High-speed data transmission for spaceborne applications. Radiation Effects Data Workshop, 2001: 67~71
[41] Davor Glisic. LVDS预加重功能可以加强电缆性能及降低系统成本.电子工程专辑(技术文库), 2005年05月23日
[2]赵忠文,曾峦,熊伟. LVDS技术分析和应用设计.装备指挥技术学院学报, 2001, 12(6): 89~93
[3]布明恩,杨文荣,张启平. 8位LVDS串行器的设计研究.微计算机信息, 2005, 21(1): 103~104
[4]马彦,冯勇. LVDS技术研究.电子计算机, 2002, Sum No.154: 20~23
[5] LVDS Owner’s. Manual, National Semiconductor Corp., 1997
[6] Jacob Reese.单端PECL与差分PECL的互连.电子产品世界, 2001, (10): 37~39.
[7]刘祥远,陈书明. LVDS高速I/O接口单元的设计研究.计算机工程与科学, 2001, 23(4): 52~56
[8]杨毅. MLVDS标准介绍及德州仪器SN 65MLVDS200系列.德州仪器(上海)有限公司
[9] LVDS Owner’s Manual. National Semiconductor Corp. 3rd Edition, spring 2004
[10] Mingdeng Chen, Jose Silva-Martinez, Michael Nix, Moises E. Robinson. Low-Voltage Low-Power LVDS Drivers. IEEE Journal of solid-state circuits, 2005, 40(2): 472~479
[11]宋正勋,谭宝华.低压差分信号技术.长春光学精密机械学院学报, 2000, 23(2): 33~36
[12]何捷,朱臻.一种具有温度补偿、高电源抑制比的带隙基准源.复旦学报(自然科学版), 2001, 40(1): 86~90
[13]孙顺根,吴晓波.一种高精度CMOS能隙基准电压源.微电子学, 2003, 33(2): 157~159
[14] Kujik. K. E. A precision reference voltage source. IEEE J. Solid-state Circuits, 1973, 8(3): 222~226
[15] Manku T., Wang Y. Temperature-independent output voltage generated by threshold voltage of an NMOS transistor. IEE Electronics Letters, 1995, 31(12): 935~936
[16] Tham K-M, Nagaraj K. A Low Supply Voltage Hige PSRR Voltage Reference in CMOS process. IEEE J. Solid-state Circuits, 1995, 30(2): 31~35
[17] Gianluca Giustolisi, Gaetano Palumbo. A detailed analysis of power-supplly noise attenuation in bandgap voltage references. Circuits and systemsⅠ: Fundanmental Theory and Appolications, IEEE Transaction on, 2003, 50(2): 185~197
[18]毕查德·拉扎维.模拟CMOS集成电路设计.陈贵灿,程军,张瑞智等.西安:西安交通大学出版社, 2003. 312~319
[19]刘韬,徐志伟.一种高电源抑制比CMOS能隙基准电压源.微电子学, 1999, 29(2): 128~131
[20]王福昌,鲁昆生.锁相技术.武昌:华中理工大学出版社, 1997. 10~30
[21] F. M. Gardner. Charge-Pump Phase-Locked Loops. IEEE Trans. Comm., 1980, vol. COM– 28: 1894~1858
[22] Roberto Pelliconi, David Iezzi, Andrea Baroni, et al. Power Efficient Charge Pump in Deep Submicron Standard CMOS Technology, IEEE Journal of Solid-State Circuits, 38(6), 2003: 1068~1071
[23] MansuriM, YangC. Jitter optimization based on phase-locked loop design parameters, IEEE J Sol Sta Circ, 2002, 37(11): 1375~1382
[24] Roland E. Best. Phase-locked loops design, simulation, and application. 5th北京:清华大学出版社, 2003. 19~23
[25]姜梅,刘三清,李乃平,陈钊.用于电荷泵锁相环的无源滤波器的设计.微电子学, 2003, 33(4): 339~343
[26] Benyong Zhang, Phillip E. Allen, Jeff M. Huard. A Fast Switching PLL Frequency Synthesizer With an On-Chip Passive Discrete-Time Loop Filter in 0.25-μm CMOS, IEEE Journal of Solid-State Circuits, 2003, 38(6): 855~865
[27] Yuping Toh, John A. McNeill. Single-Ended to Differential Converter for Multiple-Stage Single-Ended Ring Oscillators. IEEE Journal of Solid-State Circuits, 2003, 38(1): 141~145
[28]谢海情,曾健平,刘嘉晗,叶英. CMOS集成压控振荡器设计.宇航计测技术, 2006, 26(2): 47~50
[29] Manop Thamsirianunt, Tadeusz A. Kwasniewski. CMOS VCO’s for PLL Frequency Synthesis in GHz Digital Mobile Radio Communications. IEEE Journal of Solid-State Circuits, 1997, 32(10): 1511~1524
[30] Emad Hegazi, Asad A. Abidi. Varactor Characteristics, Oscillator Tuning Curves, and AM-FM Conversion. IEEE Journal of Solid-State Circuits, 2003, 38(6): 1033~1039
[31] M.-J. Edward Lee, William J. Dally Trey Greer et al.. Jitter Transfer Characteristics of Delay-Locked Loops-Theories and Design Techniques, IEEE Journal of Solid-State Circuits, 2003, 38(4): 614~621
[32] RazaviB. A study of phase noise in CMOS oscillators. IEEE J Sol Sta Circ, 1996; 31(3): 331~343
[33]宋屾,焦淑红,胡尔富.时钟抖动和相位噪声关系的研究.应用科技, 2006, 33(4): 1~6
[34] Ishibe M., Otaka S., Takeda J. ect. High Speed CMOS I/O Buffer Circuits. IEEE Journal of Solid State Circuit, 1992, 27(4):706~711
[35] Meng-Tzer Wong. A 2.5Gbps CMOS Serial Link Transceiver Design. 2002
[36] Kenpainen Stephen. BLVDS和GLVDS技术分析.电子产品世界, 2002, (3): 51~55
[37] Cole, C.B., Warwick, T.P. High speed digital transceivers: A challenge for manufacturing. Test Conference, 1999. Proceedings. International, 1999: 211~215
[38] Jun Cao, Momtaz, A, Vakilian, K., Green, M. OC-192 receiver in standard 0.18μm CMOS. Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International , 2002, 1: 250~464
[39] Jaeseo Lee, Jae-Won Lim, Sung-Jun Song. Design and implementation of CMOS LVDS 2.5 Gb/s transmitter and 1.3 Gb/s receiver for optical interconnections. 2001, 4(6-9): 702~705
[40] Benedetto, J.M, Oliver, A. High-speed data transmission for spaceborne applications. Radiation Effects Data Workshop, 2001: 67~71
[41] Davor Glisic. LVDS预加重功能可以加强电缆性能及降低系统成本.电子工程专辑(技术文库), 2005年05月23日