电荷泵锁相环的设计及其相位噪声优化
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摘要
本文首先简述了锁相环的历史、发展与应用,紧接着论述了电荷泵锁相环的基本原理,并对锁相环的相位噪声的相关理论进行了介绍和对比,最后本论文设计了一个三阶电荷泵锁相环电路,并对该锁相环进行了详细的模拟。该锁相环主要用于LVDS中的时钟产生模块,其输出频率为10MHz到160MHz,采用了七级延迟单元,由于它的七个输出相位差固定,因而可以用于高速LVDS中。
设计中采用了自顶向下的方法,对电荷泵锁相环电路采用的设计思路是:从系统级开始研究,并逐步过渡到晶体管级的模块设计。首先,对电荷泵锁相环采用连续时间近似和线性近似得出了一个线性连续的相位域传输函数模型。同时为了验证所设计的电荷泵锁相环,本文建立了包括电荷泵锁相环非线性本质和离散时间特性的行为模型,并且进行了仿真验证。其次,在确定了模块的指标后,利用HJTC的0.18μm Mixed-Mode and RFCMOS工艺,对每一个模块进行了详细的设计与模拟,包括压控振荡器(VCO)、鉴频鉴相器(PFD)、电荷泵(Charge Pump)、低通滤波器(LPF),并且提出了两种方法对VCO的相位噪声进行优化。最后,将模块组合成为系统后,分析了系统在不同的工艺、温度和电源电压下的工作情况,从模拟结果可以看出,各个模块以及整体锁相环电路的设计均达到了设计要求。
本论文的研究成果对于锁相环电路的系统设计与模块设计,包括相位噪声的分析与模拟均有很好的指导意义和参考价值。
The paper describes the history, development and application in briefly, then, analyzes the basic principle of the charge pump PLL. It also introduces and compares some theories of PLL’s phase noise. The paper gives a design of third order CPPLL and analogs it in detail. This PLL referred there is used in LVDS clocks, whose output frequency is from 10MHz to160MHz. It can be used in high speed LVDS system because the inter VCO has 7 order delay cell with 7 phases output stand
The design method of Top to Down is used, which is from the system level design of charge pump PLL to the transistor level design of each block in PLL. Firstly, we get a linear continuous phase domain transfer function model by regard the charge pump PLL as a continuous and linear system. In the meantime, In order to prove the charge-pump phase-locked loops at the system level, the paper establishes a behavioral model in simulink. The behavioral model includes nonlinearity and discrete-time nature of charge-pump phase-locked loops, and then the behavioral model is used to simulate charge-pump phase-locked loops at the system level. Secondly, after each block's specification is decided, detailed design and simulation of these blocks are completed including Voltage Controlled Oscillator (VCO), Phase Frequency Detector (PFD), Charge Pump, Low Pass Filter (LPF), based on the 0.18μm Mixed-Mode and RFCMOS process technology of HJTC. In the meantime, two methods are used to improve the phase noise of VCO. Finally, the charge pump PLL system consisted by these blocks is simulated under different process, temperature and power voltage. From the simulation results, each block and the whole PLL system have obtained the design specifications.
The achievement of this paper will provide lots of useful guides and references on the design of system and module level in PLL circuit also include the analysis and simulation of phase noise.
设计中采用了自顶向下的方法,对电荷泵锁相环电路采用的设计思路是:从系统级开始研究,并逐步过渡到晶体管级的模块设计。首先,对电荷泵锁相环采用连续时间近似和线性近似得出了一个线性连续的相位域传输函数模型。同时为了验证所设计的电荷泵锁相环,本文建立了包括电荷泵锁相环非线性本质和离散时间特性的行为模型,并且进行了仿真验证。其次,在确定了模块的指标后,利用HJTC的0.18μm Mixed-Mode and RFCMOS工艺,对每一个模块进行了详细的设计与模拟,包括压控振荡器(VCO)、鉴频鉴相器(PFD)、电荷泵(Charge Pump)、低通滤波器(LPF),并且提出了两种方法对VCO的相位噪声进行优化。最后,将模块组合成为系统后,分析了系统在不同的工艺、温度和电源电压下的工作情况,从模拟结果可以看出,各个模块以及整体锁相环电路的设计均达到了设计要求。
本论文的研究成果对于锁相环电路的系统设计与模块设计,包括相位噪声的分析与模拟均有很好的指导意义和参考价值。
The paper describes the history, development and application in briefly, then, analyzes the basic principle of the charge pump PLL. It also introduces and compares some theories of PLL’s phase noise. The paper gives a design of third order CPPLL and analogs it in detail. This PLL referred there is used in LVDS clocks, whose output frequency is from 10MHz to160MHz. It can be used in high speed LVDS system because the inter VCO has 7 order delay cell with 7 phases output stand
The design method of Top to Down is used, which is from the system level design of charge pump PLL to the transistor level design of each block in PLL. Firstly, we get a linear continuous phase domain transfer function model by regard the charge pump PLL as a continuous and linear system. In the meantime, In order to prove the charge-pump phase-locked loops at the system level, the paper establishes a behavioral model in simulink. The behavioral model includes nonlinearity and discrete-time nature of charge-pump phase-locked loops, and then the behavioral model is used to simulate charge-pump phase-locked loops at the system level. Secondly, after each block's specification is decided, detailed design and simulation of these blocks are completed including Voltage Controlled Oscillator (VCO), Phase Frequency Detector (PFD), Charge Pump, Low Pass Filter (LPF), based on the 0.18μm Mixed-Mode and RFCMOS process technology of HJTC. In the meantime, two methods are used to improve the phase noise of VCO. Finally, the charge pump PLL system consisted by these blocks is simulated under different process, temperature and power voltage. From the simulation results, each block and the whole PLL system have obtained the design specifications.
The achievement of this paper will provide lots of useful guides and references on the design of system and module level in PLL circuit also include the analysis and simulation of phase noise.
引文
[1] Liu Sujian, Yang Weiming, Chen Jianxin, et al. A Fractional-N CMOS DPLL with Self-Calibration. Chinese Journal of Semiconductor, 2005(11): 2085-2090
[2]习靖.锁相环路的稳定性研究.无线电通信技术, 2002, 28(1): P55-56
[3] Klarreich Erica. Huygens's clocks revisited. American Scientist, 2002(1): 5-9
[4] Behzad Razavi. A study of phase noise in CMOS oscillators. IEEE JOURNAL OF SOLID-STSTE CIRCUITS, 1996,31(3): 331-343
[5] Ali Hajimiri, Thomas H. Lee. A general theory of phase noise in electrical oscillators. IEEE JOURNAL OF SOLID-STSTE CIRCUITS, 1998,33(2): 179-194
[6] Floyd M. Gardner. Phase lock Techniques, 2nd Edition. New York: John Wiley, 1979: 11-18
[7]王庆生,陆栋材.频率合成技术.通信对抗, 2005, 2: 3-10
[8] Behzad Razavi.模拟CMO S集成电路设计.陈贵灿,程军,张瑞智等译.西安:西安交通大学出版社, 2003: 165-177
[9]张涛.锁相环频率合成器的建模、设计与实现: [博士学位论文].保存地点:华中科技大学图书馆,2006: 28-35
[10] Herzel F., Razavi B. A study of oscillator fitter due to supply and substrate noise. IEEE Transactions on Circuits and Systems-Part II: Analog and Digital Signal Processing, 1999, 46(1): 56-62
[11] Edward Lee M. J., William J. Dally Trey Greer et al. Jitter Transfer Characteristics of Delay-Locked Loops-Theories and Design Techniques. IEEE Journal of Solid-State Circuits, 2003, 38(4): 614-621
[12]宋屾,焦淑红,胡尔富.时钟抖动和相位噪声关系的研究.应用科技,2006, 33(4): 1-6
[13] Razavi B., Lee K F, Yan R. A 3-GHz 25mW CMOS Phase Locked Loop. Dig Tech papers, 1994, 35(1): 131-132
[14]李广侠.相位预置式快速位同步锁相环.北京:军事通讯出版社, 1985: 123-125
[15] Z X Zhang, H Du, M S Lee. A 360MHz 3V CMOS PLL with 1V Peak-Peak PowerNoise Tolerance. IEEE, 1996, 27(3): 134-135
[16] Hui Wang, Richard Nottenburg. A 1 Gb/s CMOS Clock and Data Recovery Circuit. IEEE Solid-State Circuits, 1999, 16(5): 354-357
[17] Nai-Chen Cheng .On-Chip Low Jitter Clock Generation: [Master Thesis]. TaiWan: Cheng Tung University, 2005: 39-41
[18]葛乃成,程浩忠,吕干云.基于Matlab Simulink仿真的电能质量检测.供用电, 2004, 21 (6): 29-32
[19] Cicero S. Vaucher. An Adaptive PLL Tuning System Architecture Combining High Spectral Purity and Fast Settling Time. IEEE J. Solid-State Circuits, 2000(4): 490-502
[20] Cursharan Reehal. A Digital Frequency Synthesizer Using Phase Locked Loop Technique: [Bachelor Thesis]. Ohio State, America : the Ohio State University, 1998: 64-66
[21]陈文焕.电荷泵锁相环的基础研究: [硕士学位论文].成都:电子科技大学图书馆, 2005: 52-57
[22]余志平,周润德译. CMOS射频集成电路设计,北京:电子工业出版社, 2006: 505-517
[23]王博,郭林. CMOS环形振荡器的噪声分析.微电子学, 2003, 33(3): 221-223
[24] Enam S. K. A 300-MHz CMOS voltage-controlled ring oscillator. IEEE JOURNAL OF SOLID-STSTE CIRCUITS, 1990, 25(5): 312-315
[25] Chan-Hong Park, Beomsup Kim. A Low Noise 900MHz VCO in 0.6um CMOS. IEEE JOURNAL OF SOLID-STSTE CIRCUITS, 1999, 34(5): 586-591
[26]张涛,邹雪城,刘力等.低噪声CMOS环型压控振荡器的设计.微电子学. 2004, 21(7): 164-167
[27]胡二虎,汪东旭.一种频率稳定的集成CMOS环形振荡器.微电子学, 2003, 33(3): 259-261
[28]潘莎,赵辉,任俊彦. 1.8GHz相位噪声优化的差分压控振荡器.微电子学, 2003, 33(5): 390-394
[29]沈乐丰.一种用于锁相环的压控振荡器的设计: [硕士学位论文].武汉:华中科技大学电子系资料室, 2004: 15-19
[30] Liang Dai. Design of High-Performance VCOS for Communications: [Doctor Thesis]. Minnesota State, America: Minnesota University, 2002: 81-85
[31]王涛.高速低噪声锁相时钟恢复电路研究: [博士学位论文].上海:复旦大学图书馆, 2004年: 42-47
[32] Phillip E. Allen, Douglas R. Holberg. CMOS Analog Circuit Design, 2nd edition Oxford University Press, Inc, 2002: 383-386
[33] Weixin Kong. Low Phase Noise Design Techniques For Phase Locked Loop Based Integrated RF Frequency Synthesizers: [Doctor Thesis].Maryland State, America: the University of Maryland, 2005: 64-79
[34] Ishibe M., Otaka S., Takeda J. et al. High Speed CMOS I/O Buffer Circuits. IEEE Journal of Solid State Circuit, 1992, 27(4): 706-711.
[35] Roberto Pelliconi, David Iezzi, Andrea Baroni, et al. Power Efficient Charge Pump in Deep Submicron Standard CMOS Technology. IEEE Journal of Solid-State Circuits, 2003, 38(6):1068-1071.
[36]李桂华,王钊,孙仲林等.一种高速低功耗低相位抖动CMOS锁相环.微电子学, 2001, 31(5): 379-382
[37] Moisiadis Y., Bouras I., A. Arapoyanni. A CMOS charge pump for low voltage operation. IEEE Int. Symp. Circuit and Systems, 2000, 5: 577-580
[38]韩兴成,黄震,李兴仁等.电荷泵电路的分析、设计和提高性能的研究.固体电子学研究与进展, 1999, 19(3): 305-313
[39] Best R E. Phase-locked loops design, simulation, and application, 5th Edition. McGraw-Hill Co, Inc 2003:231-240
[40]姜梅,刘三清,李乃平等.用于电荷泵锁相环的无源滤波器的设计.微电子学, 2003, 33(4): 339-343.
[2]习靖.锁相环路的稳定性研究.无线电通信技术, 2002, 28(1): P55-56
[3] Klarreich Erica. Huygens's clocks revisited. American Scientist, 2002(1): 5-9
[4] Behzad Razavi. A study of phase noise in CMOS oscillators. IEEE JOURNAL OF SOLID-STSTE CIRCUITS, 1996,31(3): 331-343
[5] Ali Hajimiri, Thomas H. Lee. A general theory of phase noise in electrical oscillators. IEEE JOURNAL OF SOLID-STSTE CIRCUITS, 1998,33(2): 179-194
[6] Floyd M. Gardner. Phase lock Techniques, 2nd Edition. New York: John Wiley, 1979: 11-18
[7]王庆生,陆栋材.频率合成技术.通信对抗, 2005, 2: 3-10
[8] Behzad Razavi.模拟CMO S集成电路设计.陈贵灿,程军,张瑞智等译.西安:西安交通大学出版社, 2003: 165-177
[9]张涛.锁相环频率合成器的建模、设计与实现: [博士学位论文].保存地点:华中科技大学图书馆,2006: 28-35
[10] Herzel F., Razavi B. A study of oscillator fitter due to supply and substrate noise. IEEE Transactions on Circuits and Systems-Part II: Analog and Digital Signal Processing, 1999, 46(1): 56-62
[11] Edward Lee M. J., William J. Dally Trey Greer et al. Jitter Transfer Characteristics of Delay-Locked Loops-Theories and Design Techniques. IEEE Journal of Solid-State Circuits, 2003, 38(4): 614-621
[12]宋屾,焦淑红,胡尔富.时钟抖动和相位噪声关系的研究.应用科技,2006, 33(4): 1-6
[13] Razavi B., Lee K F, Yan R. A 3-GHz 25mW CMOS Phase Locked Loop. Dig Tech papers, 1994, 35(1): 131-132
[14]李广侠.相位预置式快速位同步锁相环.北京:军事通讯出版社, 1985: 123-125
[15] Z X Zhang, H Du, M S Lee. A 360MHz 3V CMOS PLL with 1V Peak-Peak PowerNoise Tolerance. IEEE, 1996, 27(3): 134-135
[16] Hui Wang, Richard Nottenburg. A 1 Gb/s CMOS Clock and Data Recovery Circuit. IEEE Solid-State Circuits, 1999, 16(5): 354-357
[17] Nai-Chen Cheng .On-Chip Low Jitter Clock Generation: [Master Thesis]. TaiWan: Cheng Tung University, 2005: 39-41
[18]葛乃成,程浩忠,吕干云.基于Matlab Simulink仿真的电能质量检测.供用电, 2004, 21 (6): 29-32
[19] Cicero S. Vaucher. An Adaptive PLL Tuning System Architecture Combining High Spectral Purity and Fast Settling Time. IEEE J. Solid-State Circuits, 2000(4): 490-502
[20] Cursharan Reehal. A Digital Frequency Synthesizer Using Phase Locked Loop Technique: [Bachelor Thesis]. Ohio State, America : the Ohio State University, 1998: 64-66
[21]陈文焕.电荷泵锁相环的基础研究: [硕士学位论文].成都:电子科技大学图书馆, 2005: 52-57
[22]余志平,周润德译. CMOS射频集成电路设计,北京:电子工业出版社, 2006: 505-517
[23]王博,郭林. CMOS环形振荡器的噪声分析.微电子学, 2003, 33(3): 221-223
[24] Enam S. K. A 300-MHz CMOS voltage-controlled ring oscillator. IEEE JOURNAL OF SOLID-STSTE CIRCUITS, 1990, 25(5): 312-315
[25] Chan-Hong Park, Beomsup Kim. A Low Noise 900MHz VCO in 0.6um CMOS. IEEE JOURNAL OF SOLID-STSTE CIRCUITS, 1999, 34(5): 586-591
[26]张涛,邹雪城,刘力等.低噪声CMOS环型压控振荡器的设计.微电子学. 2004, 21(7): 164-167
[27]胡二虎,汪东旭.一种频率稳定的集成CMOS环形振荡器.微电子学, 2003, 33(3): 259-261
[28]潘莎,赵辉,任俊彦. 1.8GHz相位噪声优化的差分压控振荡器.微电子学, 2003, 33(5): 390-394
[29]沈乐丰.一种用于锁相环的压控振荡器的设计: [硕士学位论文].武汉:华中科技大学电子系资料室, 2004: 15-19
[30] Liang Dai. Design of High-Performance VCOS for Communications: [Doctor Thesis]. Minnesota State, America: Minnesota University, 2002: 81-85
[31]王涛.高速低噪声锁相时钟恢复电路研究: [博士学位论文].上海:复旦大学图书馆, 2004年: 42-47
[32] Phillip E. Allen, Douglas R. Holberg. CMOS Analog Circuit Design, 2nd edition Oxford University Press, Inc, 2002: 383-386
[33] Weixin Kong. Low Phase Noise Design Techniques For Phase Locked Loop Based Integrated RF Frequency Synthesizers: [Doctor Thesis].Maryland State, America: the University of Maryland, 2005: 64-79
[34] Ishibe M., Otaka S., Takeda J. et al. High Speed CMOS I/O Buffer Circuits. IEEE Journal of Solid State Circuit, 1992, 27(4): 706-711.
[35] Roberto Pelliconi, David Iezzi, Andrea Baroni, et al. Power Efficient Charge Pump in Deep Submicron Standard CMOS Technology. IEEE Journal of Solid-State Circuits, 2003, 38(6):1068-1071.
[36]李桂华,王钊,孙仲林等.一种高速低功耗低相位抖动CMOS锁相环.微电子学, 2001, 31(5): 379-382
[37] Moisiadis Y., Bouras I., A. Arapoyanni. A CMOS charge pump for low voltage operation. IEEE Int. Symp. Circuit and Systems, 2000, 5: 577-580
[38]韩兴成,黄震,李兴仁等.电荷泵电路的分析、设计和提高性能的研究.固体电子学研究与进展, 1999, 19(3): 305-313
[39] Best R E. Phase-locked loops design, simulation, and application, 5th Edition. McGraw-Hill Co, Inc 2003:231-240
[40]姜梅,刘三清,李乃平等.用于电荷泵锁相环的无源滤波器的设计.微电子学, 2003, 33(4): 339-343.