硅快速深刻蚀技术的研究
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摘要
随着MEMS技术中硅基高深宽比微细结构和3-D封装中穿透硅通孔技术的应用,硅的感应耦合等离子体(ICP)刻蚀技术成为国内外研究的热点。本文采用中科院微电子研究中心ICP-98A高密度等离子体刻蚀机,研究了不同工艺参数对硅刻蚀速率的影响,获得较好的硅快速刻蚀工艺;通过对掩蔽层图形化的工艺、掩蔽层材料对硅的刻蚀选择比、交替复合深刻蚀技术中的单步保护层淀积工艺以及硅的各向异性刻蚀工艺等研究,实现了硅基通孔结构。
本文研究了硅快速刻蚀技术和硅深刻蚀技术。首先通过大量的实验得出不同工艺参数,如射频功率、气体流量、自偏压以及不同掺杂气体等对硅刻蚀速率的影响,得到了硅快速刻蚀的工艺参数。其次对适用于ICP-98A高密度等离子体刻蚀机的硅深刻蚀技术进行了研究。设计并通过实验得出基于腐蚀和剥离技术的掩蔽层薄膜图形化工艺;通过研究SiO_2、MgO和Al在SF_6中的刻蚀速率以及对硅的刻蚀选择比,得出硅对MgO的刻蚀选择比大于1000:1,适于在硅深刻蚀中作为掩蔽层材料。本文采用交替复合深刻蚀技术实现硅的深刻蚀,分别研究了CF_4、C_4F_8和O_2作为钝化气体的保护层沉积工艺和采用SF_6和CF_4、SF_6和C_4F_8、SF_6和O_2对硅进行各向异性刻蚀的工艺,根据测试结果,选用SF_6和O_2作为刻蚀和钝化气体进行交替复合深刻蚀。在此工艺研究的基础上,对工艺流程进行了优化,综合考虑刻蚀速率、侧壁垂直度、深宽比等因素,提出了分阶段采用不同刻蚀工艺的方法,最终实现深度为420μm,深宽比为4:1,侧壁垂直度达88.2°的硅基通孔结构。
通过本论文的研究,获得了一组较好的适用于国产手动等离子体刻蚀设备的硅深刻蚀工艺参数。
With the application of silicon high aspect ratio micro-structure on MEMS technology and through-silicon via hole on 3-D packages technology, inductively coupled plasma (ICP) etching technique for silicon has become a hot research topic in civil and overseas. In this article, the influence of different process parameters for silicon etching rate have been studied by ICP-98A high-density inductively coupled plasma etcher, which produced by the Microelectronics Research Center, Chinese Academy of Sciences. Finally, the optimal parameters of high-speed etching silicon can be obtained. Through the following research, including the patterning process of mask, the selectivity of mask materials for silicon, the deposition process of passivation layer and the process of silicon anisotropic etching in Time Multiplexed Deep Etching (TMDE), the through-silicon via hole has been achieved.
The high-speed etching technology and deep-etching technique for silicon have been researched in this article. Firstly, the influence of process parameters on the silicon etching rate, such as RF power, gas flow, self-bias and the different doping gases, have been obtained. By comparing the above results, the optimal process parameters of high-speed etching for silicon have been identified. Secondly, the deep-etching technique for silicon which is suit for ICP-98A high-density inductively coupled plasma etcher has been studied. The patterning process parameters of mask, which based on the corrosion and lift-off technique, have been studied. Researching on the etching rate and the selectivity of SiO_2, MgO and Al for silicon, the selectivity of silicon for MgO is greater than 1000:1. So MgO is selected as a high quality mask material in silicon deep-etching. TMDE technology has been chosen for silicon deep-etching. The deposition process of passivation layer using CF_4, C_4F_8 and O_2, and the process of silicon anisotropic etching using SF_6 and CF_4, SF_6 and C_4F_8, SF_6 and O_2 have been studied respectively. Testing results show that TMDE for silicon can be realized by selecting SF_6 and O_2 as the etching and passivation gases respectively. Considering different factors, such as etching rate, sidewall verticality and aspect ratio and so on, the approach using different etching process in different stages is presented. On the basis of process researching, the process has been optimized. The through-silicon via hole, the depth of 420μm, the aspect ratio of 4:1, the sidewall verticality of 88.2°, has been achieved.
In this article, a set of optimal process parameters suiting for domestically manual plasma etcher have been obtained.
本文研究了硅快速刻蚀技术和硅深刻蚀技术。首先通过大量的实验得出不同工艺参数,如射频功率、气体流量、自偏压以及不同掺杂气体等对硅刻蚀速率的影响,得到了硅快速刻蚀的工艺参数。其次对适用于ICP-98A高密度等离子体刻蚀机的硅深刻蚀技术进行了研究。设计并通过实验得出基于腐蚀和剥离技术的掩蔽层薄膜图形化工艺;通过研究SiO_2、MgO和Al在SF_6中的刻蚀速率以及对硅的刻蚀选择比,得出硅对MgO的刻蚀选择比大于1000:1,适于在硅深刻蚀中作为掩蔽层材料。本文采用交替复合深刻蚀技术实现硅的深刻蚀,分别研究了CF_4、C_4F_8和O_2作为钝化气体的保护层沉积工艺和采用SF_6和CF_4、SF_6和C_4F_8、SF_6和O_2对硅进行各向异性刻蚀的工艺,根据测试结果,选用SF_6和O_2作为刻蚀和钝化气体进行交替复合深刻蚀。在此工艺研究的基础上,对工艺流程进行了优化,综合考虑刻蚀速率、侧壁垂直度、深宽比等因素,提出了分阶段采用不同刻蚀工艺的方法,最终实现深度为420μm,深宽比为4:1,侧壁垂直度达88.2°的硅基通孔结构。
通过本论文的研究,获得了一组较好的适用于国产手动等离子体刻蚀设备的硅深刻蚀工艺参数。
With the application of silicon high aspect ratio micro-structure on MEMS technology and through-silicon via hole on 3-D packages technology, inductively coupled plasma (ICP) etching technique for silicon has become a hot research topic in civil and overseas. In this article, the influence of different process parameters for silicon etching rate have been studied by ICP-98A high-density inductively coupled plasma etcher, which produced by the Microelectronics Research Center, Chinese Academy of Sciences. Finally, the optimal parameters of high-speed etching silicon can be obtained. Through the following research, including the patterning process of mask, the selectivity of mask materials for silicon, the deposition process of passivation layer and the process of silicon anisotropic etching in Time Multiplexed Deep Etching (TMDE), the through-silicon via hole has been achieved.
The high-speed etching technology and deep-etching technique for silicon have been researched in this article. Firstly, the influence of process parameters on the silicon etching rate, such as RF power, gas flow, self-bias and the different doping gases, have been obtained. By comparing the above results, the optimal process parameters of high-speed etching for silicon have been identified. Secondly, the deep-etching technique for silicon which is suit for ICP-98A high-density inductively coupled plasma etcher has been studied. The patterning process parameters of mask, which based on the corrosion and lift-off technique, have been studied. Researching on the etching rate and the selectivity of SiO_2, MgO and Al for silicon, the selectivity of silicon for MgO is greater than 1000:1. So MgO is selected as a high quality mask material in silicon deep-etching. TMDE technology has been chosen for silicon deep-etching. The deposition process of passivation layer using CF_4, C_4F_8 and O_2, and the process of silicon anisotropic etching using SF_6 and CF_4, SF_6 and C_4F_8, SF_6 and O_2 have been studied respectively. Testing results show that TMDE for silicon can be realized by selecting SF_6 and O_2 as the etching and passivation gases respectively. Considering different factors, such as etching rate, sidewall verticality and aspect ratio and so on, the approach using different etching process in different stages is presented. On the basis of process researching, the process has been optimized. The through-silicon via hole, the depth of 420μm, the aspect ratio of 4:1, the sidewall verticality of 88.2°, has been achieved.
In this article, a set of optimal process parameters suiting for domestically manual plasma etcher have been obtained.
引文
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[4]亚微纳技术公司.一种用于制造基于穿透硅通孔的三维集成电路之综合制成法.科学网论坛[EB/OL][2008-07-04].http://www.sciencenet.cn/bbs/showpost.aspx?id=24782.
[5]Jan Provoost,Deniz Sabuncuoglu Tezcan,Bart Swinnen,Eric Beyne.用于3D WLP和3D SIC的穿透硅通孔技术[J].集成电路应用,2008,6(7):45-47.
[6]赵智昊,陈俊芳,黄钊洪,等.CCl_2F_2等离子体干法刻蚀InSb-In薄膜的研究[J].传感器技术,2003,4(5):8-10.
[7]曹正军.MEMS后处理中体硅腐蚀的芯片保护[D].南京:东南大学,2006.3:12-23.
[8]张鉴.MEMS加工中电感耦合等离子体(ICP)刻蚀硅片的模型与模拟[D].南京:东南大学,2006.12.15-27.
[9] Xu Ying,Sun Hongbo,Ye Jiayi,et al.Fabrication and Direct Transmission Measurement of High-aspect-ratio Two-dimensional Silicon-based Photoniccrystal Chips[J].Electrochem,2001,18(10): 15-21.
[10] Zhou Libing,Liu wen,Wu Guoyang.Optimization of Plasma Etching Parameters and Mask for Silica Optical Waveguides[J].Chinese Journal of Semiconductors,2005,26(6):412-419.
[11]李效白.等离子体微细加工技术的新进展[J].真空科学术,2000,20(3):179-186.
[12]王阳元,武国英,郝一龙,等.硅基MEMS加工技术及其标准工艺研究[J].电子学报,2002,30(11):1576-1584.
[13]钱振型主编.固体电子学中的等离子体技术[M].北京:电子工业出社,1987.67-89.
[14] Wang L,Nichelatti A,Schellevis H,et al.Highaspect ratio through-wafer interconnections for 3D-microsystems[A].Proc 16th IEEE International MEMS Conference [C].Kyoto(Japan):IEEE,2003.206-213.
[15]江刺正喜.MEMS最新的技术动向与应用展望[J].电子材料,2002,10(5):18-21.
[16]张威,张大成,王阳元.MEMS概况及发展趋势[J].微纳米电子技术,2002(1):22-27.
[17] Chen K S,Ayon A A,Zhang X,et,al.Effect of Process Parameters on the Surface Morphology and Mechanical Performance of Silicon Structures After Deep Reactive Ion Etching(DRIE)[J].Journal of Microelectro Mechanical Systems,2002,11(3):264-275.
[18]程美乔.Si在SF_6中反应离子刻蚀及其研究[J].微细加工技术,1995,6(1):15-19.
[19]付永启.二元光学元件的刻蚀技术[J].光学技术,1996(增刊):8-12.
[20]施敏.半导体器件.王阳元译[C].北京:科学出版社,1975:45-68.
[21]朱泳,闫桂珍,王成伟,等.高深宽比深隔离槽的刻蚀技术研究[J].微纳电子技术,2003,(7/8):113-115.
[22]温梁,汪家友,刘道广,等.MEMS器件制造工艺中的高深宽比硅干法刻蚀技术[J].微纳电子技术,2004,(4):31-34.
[23]陈晓南,杨培林,庞宣明,等.等离子体刻蚀中工艺参数对刻蚀速率影响的研究[J].西安交通大学学报,2004,38(5):546-547.
[24]卓敏,贾世星,朱健,等.用于微惯性器件的ICP刻蚀工艺技术[J].传感技术学报,2006,19(5):1381-1383.
[25]王旭迪,张永胜,胡焕林,等.深高宽比微结构的干法刻蚀[J].真空,2004,41(5):32-34.
[26]徐惠宇,朱荻.国外高深宽比微细结构制造技术的发展[J].传感器技术,2004,23(12):4-13.
[27]樊中朝,余金中,陈少武.ICP刻蚀技术及其在光电子器件制作中的应用[J].微细加工技术,2003,22(2):21-28.
[28]赵晓锋,王丙利,李斌,温殿忠.采用MEMS制作悬臂梁结构设计模拟与制作工艺研究[J].传感器技术.2004,23(7):90-92.
[29] Ivo W .Range Low Dry Etching-based Silicon Micro-ma-chining for MEMS[J].Vacuum,2001,6(2) :279-291.
[30] Paul A K, Rangelow I W.Fabrication of High Aspect Ratio Structures Using Chlorine Gas Ghopping Technique[J].Mi-croelectronic Engineering,1997,35(4):79-82.
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