反应离子刻蚀在穿透硅通孔封装技术中的应用研究
摘要
随着社会的发展,人们需要体积更小,功耗更低,成本也更低的IC(Integrated Circuit,集成电路)产品。正是这种旺盛的需求极大推动了半导体IC封装技术的发展。传统的IC二维封装方式,是以引线键合方式将各个芯片连接起来。因此,信息传输经过了额外的通道,传输距离较大,一定程度上使信号被延迟。传统的IC三维封装是将芯片垂直地堆叠排列,但仍以引线键合方式连接各个芯片,同样存在信息传输路径较长的不足。相比于传统的IC二维和三维封装方式,利用TSV技术实现的三维封装方式,不再进行引线键合,有效缩短了信息传输路径,加快了芯片与芯片,芯片与外连接部分之间的数据传输速度,有效减少了信息在传递过程中的延迟和损失。在封装面积不变的情况下,TSV技术可以使封装产品具有更高的结构密度,因此可实现更多的功能,拥有更好的性能,成本也能更低廉。
为了实现IC器件的TSV(Through Silicon Via,穿透硅通孔)晶圆级封装,需要完成几个重要工艺技术的开发。这其中包括:晶圆减薄,粘接技术,TSV的形成与金属化,电隔离层的制作等。TSV的形成是其中很关键的一个工序。考虑到成本,精度控制等因素,一般倾向于使用干法刻蚀来制作TSV。刻蚀过程比较复杂,不同的三维IC中通孔的分布位置、密度和尺寸(包括孔深和孔径)是不同的。通孔技术需要能满足对轮廓形状的控制(包括控制倾斜度、形状、粗糙度、过刻蚀等),同时又要求工艺能具有可靠性、实用性和重复性,最后,成本也要能被合理控制。
本论文的目的是通过对反应离子刻蚀技术的研究,使之应用于IC器件TSV晶圆级封装技术中。在研究中,封装步骤为,首先以粘接技术在晶圆上覆盖一保护层;然后将晶圆从硅面减薄至要求的厚度;用反应离子刻蚀的方式再从硅面制作出TSV;区域覆盖绝缘层;之后,在晶圆上形成再分布金属化线路层;最后以划片方式将晶圆分割成单独的封装芯片。
实验中,利用反应离子刻蚀方式实现TSV,通过SEM(Scanning Electron Microscope,扫描电镜)机对通孔的形貌进行分析,从而得到了包括气体流量、压力、功率、时间的最优化参数。最终,在得到了最优化的刻蚀工艺参数后,通过刻蚀方式,实现了TSV的制作。实验证明,采用此刻蚀工艺,配合使用其他相关制作工艺,能够完成TSV晶圆级封装。随机选取样品进行检测,结果符合要求。
With the development of society,semiconductor chips face constant pressure for improved functionality,higher performance,lower power consumption,lower cost while still decreasing their size. This demand enormously impels the development of semiconductor IC packaging technology. Driven by the need for improved performance and the reduction of timing delays and signal loss,through silicon via (TSV) interconnects used in 3-D package have been developed to replace the long interconnects found in 2-D package structures. Compared with conventional 2-D wire bonding chips,3-D TSV chips reduce the distance through which information on a chip is transported. They also allow more channels or pathways for that information to flow. Moreover,TSV packaging technology can provide a packaged product with higher structure density , more functionality,higher performance and lower cost.
To achieve the IC device with TSV wafer level package,some important technologies should be developed, including wafer thinning,bonding,via etching,via filling,metallization and deposition of diffusion barrier. Among them, TSV is a very key process. Considered factors of the cost,precision control and so on,dry process is generally used to fabricate TSV. Etching process is complicated. The via position,density and size (including depth and diameter) are totally different in all kinds of 3-D IC chips. Through via technology should satisfy control requirement of outline,including tilt,shape,roughness,over-cut,and so on. The reliability,usability and duplication should be satisfied. Also, the cost should be controlled well.
This thesis is to research the reactive ion etching (RIE) and make it to be applied in the IC device with TSV wafer level package. In the package, first,alignment and bonding a protective plate on a silicon. Then the silicon is thinned to a required thickness. A through silicon via is gotten by reactive ion etching. An isolation layer is covered on the silicon surface. Finally,a redistribution layer is made on the wafer and single chips are separated by dicing.
In the experiments,TSV is achieved by RIE. The shape is analyzed by SEM cross section. Such parameters as gas flow,pressure,power and time are optimized. Results show that the IC device with TSV is achieved by RIE. The IC device with TSV wafer level package can be achieved by the optimization of etching parameters with other related process.
为了实现IC器件的TSV(Through Silicon Via,穿透硅通孔)晶圆级封装,需要完成几个重要工艺技术的开发。这其中包括:晶圆减薄,粘接技术,TSV的形成与金属化,电隔离层的制作等。TSV的形成是其中很关键的一个工序。考虑到成本,精度控制等因素,一般倾向于使用干法刻蚀来制作TSV。刻蚀过程比较复杂,不同的三维IC中通孔的分布位置、密度和尺寸(包括孔深和孔径)是不同的。通孔技术需要能满足对轮廓形状的控制(包括控制倾斜度、形状、粗糙度、过刻蚀等),同时又要求工艺能具有可靠性、实用性和重复性,最后,成本也要能被合理控制。
本论文的目的是通过对反应离子刻蚀技术的研究,使之应用于IC器件TSV晶圆级封装技术中。在研究中,封装步骤为,首先以粘接技术在晶圆上覆盖一保护层;然后将晶圆从硅面减薄至要求的厚度;用反应离子刻蚀的方式再从硅面制作出TSV;区域覆盖绝缘层;之后,在晶圆上形成再分布金属化线路层;最后以划片方式将晶圆分割成单独的封装芯片。
实验中,利用反应离子刻蚀方式实现TSV,通过SEM(Scanning Electron Microscope,扫描电镜)机对通孔的形貌进行分析,从而得到了包括气体流量、压力、功率、时间的最优化参数。最终,在得到了最优化的刻蚀工艺参数后,通过刻蚀方式,实现了TSV的制作。实验证明,采用此刻蚀工艺,配合使用其他相关制作工艺,能够完成TSV晶圆级封装。随机选取样品进行检测,结果符合要求。
With the development of society,semiconductor chips face constant pressure for improved functionality,higher performance,lower power consumption,lower cost while still decreasing their size. This demand enormously impels the development of semiconductor IC packaging technology. Driven by the need for improved performance and the reduction of timing delays and signal loss,through silicon via (TSV) interconnects used in 3-D package have been developed to replace the long interconnects found in 2-D package structures. Compared with conventional 2-D wire bonding chips,3-D TSV chips reduce the distance through which information on a chip is transported. They also allow more channels or pathways for that information to flow. Moreover,TSV packaging technology can provide a packaged product with higher structure density , more functionality,higher performance and lower cost.
To achieve the IC device with TSV wafer level package,some important technologies should be developed, including wafer thinning,bonding,via etching,via filling,metallization and deposition of diffusion barrier. Among them, TSV is a very key process. Considered factors of the cost,precision control and so on,dry process is generally used to fabricate TSV. Etching process is complicated. The via position,density and size (including depth and diameter) are totally different in all kinds of 3-D IC chips. Through via technology should satisfy control requirement of outline,including tilt,shape,roughness,over-cut,and so on. The reliability,usability and duplication should be satisfied. Also, the cost should be controlled well.
This thesis is to research the reactive ion etching (RIE) and make it to be applied in the IC device with TSV wafer level package. In the package, first,alignment and bonding a protective plate on a silicon. Then the silicon is thinned to a required thickness. A through silicon via is gotten by reactive ion etching. An isolation layer is covered on the silicon surface. Finally,a redistribution layer is made on the wafer and single chips are separated by dicing.
In the experiments,TSV is achieved by RIE. The shape is analyzed by SEM cross section. Such parameters as gas flow,pressure,power and time are optimized. Results show that the IC device with TSV is achieved by RIE. The IC device with TSV wafer level package can be achieved by the optimization of etching parameters with other related process.
引文
1. S. A. CAMPBELL. The Science and Engineering of Microelectronic Fabrication [M].Beijing: Publishing House of Electronics Industry: 614
2. B. Kim. EMC-3D Consortium Targets Cost-Effective TSV Interconnects [J]. Semiconductor International,2007,30(2):7.
3. P. Garrou,E. Vardaman. 3-D Integration at the Wafer Level[R]. USA: TechSearch International Inc.2006:
4. T. Fukushima,Y. Yamada,H. Kikuchi,T. Tanaka,et al. Ultimate Super Chip Integration[R]. USA:International Conf. on Electronic Packaging (ICEP),2006:
5. P .Garrou. Posturing & Positioning in 3-D ICs [J]. Semiconductor International,2007,30(4):88.
6. T. Pandhumsoporn, et al. High-Etch-Rate Deep Anisotropic Plasma Etching of Silicon for MEMS Fabrication [J]. Proc. SPIE,1998,3328: 93.
7. F. Larmer,A. Schilp. Method of Anisotropically Etching Silicon [P]. U.S. Patent No. 5501893,1994.
8. M.Puech,J Thevenoud,J.Gruffat.先通孔和后通孔方法制作TSV的DRIE发展[R].Alcatel Micro Machining Systems,2006:
9. S. Spiesshoefer. Z. Rahman,G. Vangara. Process integration for through-silicon vias [J]. American Vacuum Society. 2005,23(4)
10. Y .Yoneda. Proceedings of the SEMI Technology Symposium [R]. Japan: Super CSP.1998:
11. Inomata C R,Ogawa H,Ishikawa K,et al. Infrared spectroscopy study of chemical oxides formed by a sequence of RCA standard cleaning treatments[J]. J Electroche Soc,1996,143 (9): 2995.
12.戴忠玲,毛明,王友年.等离子体刻蚀工艺的物理基础[J].物理学和高新技术,2006,35(8):693-698.
13.李群庆,张立辉,陈墨,等.纳米级电子束光刻技术及ICP深刻蚀工艺技术的研究[J].技术科学,2009,39(6): 1047-1053.
14.姜政,丁桂甫,汪红.微加工厚光刻胶掩膜电镀工艺研究[J].电镀与涂饰,2005(7): 16-17.
15.刘世杰,杜惊雷,肖啸.光刻中驻波效应的影响分析[J]。微电子技术,2004,41(2):52-54.
16.肖啸.后烘对驻波效应的影响分析[J].乐山师范学院报,2004,19(12):14-16
17.来五星,轩建平,史铁林.微制造光刻工艺中光刻胶性能的比较[J].半导体技术,2004,29(11):58-60.
18.刘明,陈宝钦,王云翔,等.纳米级电子束直写曝光的基础工艺[J].半导体学报,2003,24(增刊): 226-228
19. R. L egtenberg,et al. Electrochem [J]. Soc.,1995,142 (6):2020- 2027.
20.黄钟加,余志成. RIE蚀刻硅与氮化硅之参数分析[R]。台湾:南区微机电中心机台操作参数设定专题成果报告,2004:
21.陈晓南,杨培林,庞宣明.等离子体刻蚀中工艺参数对刻蚀速率影响的研究[J].西安交通大学学报,2004,38(5):546-547.
22.陈峥,汤庭鳌,邹斯洵.Sol-Gel法制备的铁电薄膜和Pt/Ti下电极的反应离子刻蚀技术[J].半导体学报,1997,20 (2):172-176.
23.樊中朝,于金中,陈少武.ICP刻蚀参数对SOI脊形波导侧壁粗糙度的影响[J].半导体学报,2004,25(11):1500-1503.
2. B. Kim. EMC-3D Consortium Targets Cost-Effective TSV Interconnects [J]. Semiconductor International,2007,30(2):7.
3. P. Garrou,E. Vardaman. 3-D Integration at the Wafer Level[R]. USA: TechSearch International Inc.2006:
4. T. Fukushima,Y. Yamada,H. Kikuchi,T. Tanaka,et al. Ultimate Super Chip Integration[R]. USA:International Conf. on Electronic Packaging (ICEP),2006:
5. P .Garrou. Posturing & Positioning in 3-D ICs [J]. Semiconductor International,2007,30(4):88.
6. T. Pandhumsoporn, et al. High-Etch-Rate Deep Anisotropic Plasma Etching of Silicon for MEMS Fabrication [J]. Proc. SPIE,1998,3328: 93.
7. F. Larmer,A. Schilp. Method of Anisotropically Etching Silicon [P]. U.S. Patent No. 5501893,1994.
8. M.Puech,J Thevenoud,J.Gruffat.先通孔和后通孔方法制作TSV的DRIE发展[R].Alcatel Micro Machining Systems,2006:
9. S. Spiesshoefer. Z. Rahman,G. Vangara. Process integration for through-silicon vias [J]. American Vacuum Society. 2005,23(4)
10. Y .Yoneda. Proceedings of the SEMI Technology Symposium [R]. Japan: Super CSP.1998:
11. Inomata C R,Ogawa H,Ishikawa K,et al. Infrared spectroscopy study of chemical oxides formed by a sequence of RCA standard cleaning treatments[J]. J Electroche Soc,1996,143 (9): 2995.
12.戴忠玲,毛明,王友年.等离子体刻蚀工艺的物理基础[J].物理学和高新技术,2006,35(8):693-698.
13.李群庆,张立辉,陈墨,等.纳米级电子束光刻技术及ICP深刻蚀工艺技术的研究[J].技术科学,2009,39(6): 1047-1053.
14.姜政,丁桂甫,汪红.微加工厚光刻胶掩膜电镀工艺研究[J].电镀与涂饰,2005(7): 16-17.
15.刘世杰,杜惊雷,肖啸.光刻中驻波效应的影响分析[J]。微电子技术,2004,41(2):52-54.
16.肖啸.后烘对驻波效应的影响分析[J].乐山师范学院报,2004,19(12):14-16
17.来五星,轩建平,史铁林.微制造光刻工艺中光刻胶性能的比较[J].半导体技术,2004,29(11):58-60.
18.刘明,陈宝钦,王云翔,等.纳米级电子束直写曝光的基础工艺[J].半导体学报,2003,24(增刊): 226-228
19. R. L egtenberg,et al. Electrochem [J]. Soc.,1995,142 (6):2020- 2027.
20.黄钟加,余志成. RIE蚀刻硅与氮化硅之参数分析[R]。台湾:南区微机电中心机台操作参数设定专题成果报告,2004:
21.陈晓南,杨培林,庞宣明.等离子体刻蚀中工艺参数对刻蚀速率影响的研究[J].西安交通大学学报,2004,38(5):546-547.
22.陈峥,汤庭鳌,邹斯洵.Sol-Gel法制备的铁电薄膜和Pt/Ti下电极的反应离子刻蚀技术[J].半导体学报,1997,20 (2):172-176.
23.樊中朝,于金中,陈少武.ICP刻蚀参数对SOI脊形波导侧壁粗糙度的影响[J].半导体学报,2004,25(11):1500-1503.