视频格式转换芯片中数据存储系统的设计与实现
摘要
随着数字电视技术的日趋成熟,模拟电视向着数字电视转变已成为必然趋势,其中视频格式转换技术起到了非常重要的作用,并蕴涵着巨大的市场价值。它的主要功能是通过数字视频信号处理将不同格式的视频输入信号转换成特定格式的输出信号。视频处理过程包括去隔行、帧频提升、分辨率提升及各种画质增强等。因此,海量数据的存储与搬移成为视频格式转换专用芯片设计中的核心问题之一,数据存储系统的优劣将直接影响到整个芯片的性能。
本文从数据流调度和存取机制入手,对整个数据存储系统的实时性进行了系统的分析,并在此基础上对视频格式转换专用芯片中数据存储系统进行了研究与设计实现。重点设计了外部存储器(SDRAM)控制核,在对SDRAM存储器的工作参数分析的前提下,着重讨论了SDRAM控制器自顶向下(Top-Down)的设计方法,子模块的划分与设计,代码编写与优化、读写操作时序分析,功能仿真,逻辑综合以及FPGA调试策略,设计了一种具有高适用性的SDRAM控制器。该控制器具有标准的IP核的接口和多种可配置寄存器,可与其他模块通过简单的握手信号,完成数据的读写控制,具有很高扩展性和移植性。
在完成设计的基础上,本文还介绍了SDRAM控制核和整个数据存储系统的测试验证,通过对SDRAM的单独测试和视频格式转换专用芯片整体测试,证明SDRAM控制器和存储系统完全能够达到视频格式转换专用芯片的数据处理要求。实际测试中,SDRAM控制器的工作频率达到了100MHz。
As digital video technique becomes more and more widely used, the trend that analog video signal will be substituted by digital video signal is inevitable. In this interim, the video processing IC has quite a practical value and market prospect. Its main purpose is to transfer video input signals of different forms to video output signals of specific standard forms by the way of DSP. Its main functions are de-interlacing, frame rate up-conversion, scaling, quality improvement and etc. How to process and move the enormous data is one of the main problems we deal with.
This thesis focuses on design and realization of the data cache system in our video processing IC. Due to the importance of the data control and write-and-read mechanism, much introduction and analysis will be put on those parts. At the same time, the real-time performance of the data cache system will also be discussed. With some critical advantages, such as small area, low cost, high speed and large volume, SDRAM becomes the ideal external memory for the video processing IC. As the basic unit, SDRAM has the responsibility of storing all the data in the video processing procedure. Therefore, the designing and debugging of the SDRAM controller is quite an important job. After carefully studying the operation of SDRAM, in this article, I focus on the design and PCB level debugging of the SDRAM controller, which include HDL coding, write-and-read timing analysis and testing. The SDRAM controller I made, which has an adaptable ability and can easily be extended to various systems, adopts handshake signals and can be directly used as an IP core.
A top-down design procedure was used in the design process. Design regulation, module dividing, function simulation and synthesis are also discussed in the article. The whole device has been tested and used in the video processing system. The result perfectly met the design demand. In FPGA test, SDRAM controller is working at the frequency of 100MHz.
本文从数据流调度和存取机制入手,对整个数据存储系统的实时性进行了系统的分析,并在此基础上对视频格式转换专用芯片中数据存储系统进行了研究与设计实现。重点设计了外部存储器(SDRAM)控制核,在对SDRAM存储器的工作参数分析的前提下,着重讨论了SDRAM控制器自顶向下(Top-Down)的设计方法,子模块的划分与设计,代码编写与优化、读写操作时序分析,功能仿真,逻辑综合以及FPGA调试策略,设计了一种具有高适用性的SDRAM控制器。该控制器具有标准的IP核的接口和多种可配置寄存器,可与其他模块通过简单的握手信号,完成数据的读写控制,具有很高扩展性和移植性。
在完成设计的基础上,本文还介绍了SDRAM控制核和整个数据存储系统的测试验证,通过对SDRAM的单独测试和视频格式转换专用芯片整体测试,证明SDRAM控制器和存储系统完全能够达到视频格式转换专用芯片的数据处理要求。实际测试中,SDRAM控制器的工作频率达到了100MHz。
As digital video technique becomes more and more widely used, the trend that analog video signal will be substituted by digital video signal is inevitable. In this interim, the video processing IC has quite a practical value and market prospect. Its main purpose is to transfer video input signals of different forms to video output signals of specific standard forms by the way of DSP. Its main functions are de-interlacing, frame rate up-conversion, scaling, quality improvement and etc. How to process and move the enormous data is one of the main problems we deal with.
This thesis focuses on design and realization of the data cache system in our video processing IC. Due to the importance of the data control and write-and-read mechanism, much introduction and analysis will be put on those parts. At the same time, the real-time performance of the data cache system will also be discussed. With some critical advantages, such as small area, low cost, high speed and large volume, SDRAM becomes the ideal external memory for the video processing IC. As the basic unit, SDRAM has the responsibility of storing all the data in the video processing procedure. Therefore, the designing and debugging of the SDRAM controller is quite an important job. After carefully studying the operation of SDRAM, in this article, I focus on the design and PCB level debugging of the SDRAM controller, which include HDL coding, write-and-read timing analysis and testing. The SDRAM controller I made, which has an adaptable ability and can easily be extended to various systems, adopts handshake signals and can be directly used as an IP core.
A top-down design procedure was used in the design process. Design regulation, module dividing, function simulation and synthesis are also discussed in the article. The whole device has been tested and used in the video processing system. The result perfectly met the design demand. In FPGA test, SDRAM controller is working at the frequency of 100MHz.
引文
[1] 王诚, 薛小刚, 钟信潮, FPGA/CPLD 设计工具—Xilinx ISE 5.X 使用详解,北京;北京邮电大学出版社,2003 Jerry Whitaker,数字电视技术:高清晰数字视频原理与应用(第三版)(曹晨,杨作梅译),电子工业出版社与麦格劳-希尔教育出版集团,2002
[2] 张兆扬,数字电视原理,北京:科学技术出版社,1989:14~18
[3] 郑志航主编,数字电视原理与应用,中国广播电视出版社,2001
[4] Wayne Wolf, Modern VLSI Design, Prentice Hall PTR, 2003
[5] 朱志刚,石定机,数字图像处理,北京;电子工业出版社,2002
[6] 朱秀昌,刘峰,胡栋,数字图像处理与图像通信,北京;北京邮电大学出版社,2002
[7] 邱绪环,乐匋，徐孟侠，张风超，数字电视原理与应用，北京；电子工业出版社,2000
[8] 王明臣,姜秀华,张永辉,数字电视与高清晰度电视,北京;中国广播电视出版社,2005
[9] 张雅绮,李锵译,Verilog HDL 高级数字设计,北京;电子工业出版社,2005
[10] 沈东,王峰,余松煜,HDTV SOC 系统中 SDRAM 控制器的设计,微计算机信息,2006 年第 22 卷第 5-2 期
[11] 梁骏,徐红,基于 FPGA 与 SDRAM 的数字电视信号采集系统的设计与实现,通信与计算机,2004
[12] Xilinx DRAM CONTROLLER Reference Design,Xilinx, 2004
[13] Lattice DRAM CONTROLLER Reference Design, Lattice, 2004
[14]IMPORTANT_key points for controller design.pdf, Samsung, www.samsung.com
[15] Micron SDR SDRAM datasheet, www.micron.com
[16] Nanya SDR SDRAM datasheet, www.nanya.com
[17] Micron DDR SDRAM datasheet, www.micron.com
[18] Nanya DDR SDRAM datasheet, www.nanya.com
[19] Elpda DDR SDRAM datasheet, www.elpda.com
[20] Guide to HDL Coding Style for Synthesis, Synopsys Inc, 2004
[21] 夏宇闻,复杂数字电路与系统的 Verilog HDL 设计技术,北京;北京航空航大学出版社,1998
[22] 任艳颖,王彬,IC 设计基础,西安;西安电子科技大学出版社,2003
[23] Design Compiler Reference Manual,Synopsys Inc,2004 张雅绮,李锵译,Verilog HDL 高级数字设计,北京;电子工业出版社,2005
[24] Clifford E. Cummings and Peter Alfke, “Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons,” SNUG2002 (Synopsys Users Group Conference, San Jose, CA, 2002) User Papers,March 2002, Section TB2, 3rd paper.
[25] Virtex-II Platform FPGAs Complete Data Sheet DS031(v3.3),Xilinx,2004
[26] Virtex-II Platform FPGAs User Guide UG002,Xilinx,2004
[2] 张兆扬,数字电视原理,北京:科学技术出版社,1989:14~18
[3] 郑志航主编,数字电视原理与应用,中国广播电视出版社,2001
[4] Wayne Wolf, Modern VLSI Design, Prentice Hall PTR, 2003
[5] 朱志刚,石定机,数字图像处理,北京;电子工业出版社,2002
[6] 朱秀昌,刘峰,胡栋,数字图像处理与图像通信,北京;北京邮电大学出版社,2002
[7] 邱绪环,乐匋，徐孟侠，张风超，数字电视原理与应用，北京；电子工业出版社,2000
[8] 王明臣,姜秀华,张永辉,数字电视与高清晰度电视,北京;中国广播电视出版社,2005
[9] 张雅绮,李锵译,Verilog HDL 高级数字设计,北京;电子工业出版社,2005
[10] 沈东,王峰,余松煜,HDTV SOC 系统中 SDRAM 控制器的设计,微计算机信息,2006 年第 22 卷第 5-2 期
[11] 梁骏,徐红,基于 FPGA 与 SDRAM 的数字电视信号采集系统的设计与实现,通信与计算机,2004
[12] Xilinx DRAM CONTROLLER Reference Design,Xilinx, 2004
[13] Lattice DRAM CONTROLLER Reference Design, Lattice, 2004
[14]IMPORTANT_key points for controller design.pdf, Samsung, www.samsung.com
[15] Micron SDR SDRAM datasheet, www.micron.com
[16] Nanya SDR SDRAM datasheet, www.nanya.com
[17] Micron DDR SDRAM datasheet, www.micron.com
[18] Nanya DDR SDRAM datasheet, www.nanya.com
[19] Elpda DDR SDRAM datasheet, www.elpda.com
[20] Guide to HDL Coding Style for Synthesis, Synopsys Inc, 2004
[21] 夏宇闻,复杂数字电路与系统的 Verilog HDL 设计技术,北京;北京航空航大学出版社,1998
[22] 任艳颖,王彬,IC 设计基础,西安;西安电子科技大学出版社,2003
[23] Design Compiler Reference Manual,Synopsys Inc,2004 张雅绮,李锵译,Verilog HDL 高级数字设计,北京;电子工业出版社,2005
[24] Clifford E. Cummings and Peter Alfke, “Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons,” SNUG2002 (Synopsys Users Group Conference, San Jose, CA, 2002) User Papers,March 2002, Section TB2, 3rd paper.
[25] Virtex-II Platform FPGAs Complete Data Sheet DS031(v3.3),Xilinx,2004
[26] Virtex-II Platform FPGAs User Guide UG002,Xilinx,2004