基于随机测试的SoC系统级验证方法研究
|
摘要
根据摩尔定理，芯片的集成度每18至24个月翻一倍。集成度的提高使得生产出来的芯片产品面积更小、速度更快。在第三方IP(Intellectual Property)的支持下，微电子学的发展促使了在单一芯片上能够包含多种功能模块，这种芯片就被称为片上系统(System-on-Chip，SoC)。
从专用芯片(Application Specific Integrated Circuit，ASIC)过渡到片上系统，虽然在单一芯片上包含的功能越来越多，但同时对片上系统进行验证所带来的挑战也越来越大。当芯片的规模变得很庞大时，传统的验证方法已经无能为力。在寄存器传输级(Register Transfer Level，RTL)进行验证时，由于使用硬件仿真器所导致的仿真速度很低，且验证耗时很大。此外，由于寄存器传输级验证缺乏对软／硬件并行开发的支持，不利于快速进行软／硬件协同验证。
为了克服传统验证方法的局限性，本文提出了新的SoC验证方法——基于随机测试的SoC系统级验证方法。该方法源于新的验证思想，即在SoC设计的更早期发现更多的功能性设计错误。
论文的开始介绍了SoC系统级验证方法学和有关随机测试的理论，这两方面是进行论文研究的背景知识。新的SoC验证方法是在上述两方面知识的基础上提出的。
在本文的研究中，采用基于SystemC和SCV(SystemC Verification Standard)验证库的方法来创建系统级的测试平台。具体地说，在系统级验证中所使用的测试平台是采用SystemC 2.0描述的，系统级测试平台中测试向量的生成是根据SCV验证库的三种随机化机制：直接随机化、带权重的随机化和带约束的随机化。
新的验证方法可以在SoC系统级验证平台上执行，这一平台是在Sun Blade2000工作站上通过集成编译、连接和调试工具、安装SystemC库和SCV验证库构建而成的。论文中的SoC系统级验证平台是WHU SLD 1.0的一部分，WHUSLD 1.0是在研究SoC软／硬件协同设计和协同验证这一国家863项目过程中开发出来的工具原型。
通过对4×4包交换芯片的系统级模型进行一系列的验证实验，证实了基于随机测试的SoC系统级验证方法是可行的。论文具体阐述了如何创建系统级测试平台、如何对测试平台和被验证对象(Design Under Verification，DUV)进行绑定、如何根据SCV验证库的三种随机测试向量生成方法生成测试激励。针对4×4包交换芯片系统级模型不同方面的功能，论文完成了4个验证实验：通过对实验结果进行分析，反过来对论文中所提出的新的SoC验证方法进行了评估。结论表明，本文提出的验证方法能够有效地完成SoC系统级验证。
According to Moore's Law, the number of transistors per chip doubles every 18 to 24 months. The escalation in gate count has enabled the electronics industry to make major strides in producing smaller and faster consumer and communication products. The development of microelectronics makes these products contain multiple functions on a single IC (Integrated circuit), supported by various custom-designed and third-party Intellectual Property (IP). These single chip systems are called SoC (System-on-Chip).
Although the advance from ASIC (Application Specific Integrated Circuit) to SoC can provide more and more functionality for a single chip, it presents enormous verification challenges for SoC designs. The traditional verification methods become less and less powerful as the scale and complexity increase. During RTL (Register Transfer Level) verification, the using of HDL (Hardware Description Language) software simulators has been proven to be inefficient and more time-consuming. In additional, these approaches lack the parallelism needed to rapidly verify the interaction between hardware and software blocks in a SoC design.
In order to deal with the above limitations during the conventional verification, a new verification methodology for SoCs, methodology of SoC system level verification based on random testing, is proposed and established in the dissertation. On one hand, the new verification methodology is derived from the criteria: find more functional errors in the earlier SoC design cycles compared with register transfer level. On the other hand, the new verification methodology has deployed a feasible technique that can address the verification bottleneck for SoC design.
The methodology of SoC system level verification and the theory of random testing are introduced directly at the start of this dissertation, which are the background for researches in the thesis. In fact, the new SoC verification methodology is brought forward based on knowledge in the above two aspects.
Apart from the basic knowledge, the research of creating testbench for system level verification is on the basis of SystemC and SystemC Verification Standard (SCV). Specifically, testbench for system level verification according to the new methodology is described using SystemC 2.0. Moreover, test cases for the system level testbench is generated according to three different mechanisms of randomisation based on SystemC Verification Standard specification, which consist of direct randomisation, weighted randomisation and constrained randomisation typically used in verification.
The new verification approach can be implemented on the platform of SoC system level verification, which is constructed by integrating compiling, linking and debugging tools and installing SystemC and SystemC Verification Standard libraries on a Sun Blade 2000 workstation. Actually the platform is a part of WHU SLD 1.0 that is the tool prototype for SoC system level design developed in a National 863 Project about researches on SoC hardware/software co-design and co-verification.
The methodology of SoC system level verification based on random testing is demonstrated on a series of experiments, which implement functional verifications on system level models of 4 X 4 package switch. The thesis sets forth in detail how to create system level testbench for the verification, how to bind the testbench and the
Design Under Verification (DUV) and how to generate test stimuli in accordance with three types of randomization in SystemC Verification Standard. Through analysing results of four different experiments that verified different functions provided with the system level model of 4 X 4 package switch, the new verification method put forward in this dissertation has been evaluated contrarily. The results have indicated that the method proposed in the paper can be used to fulfill SoC system level verification efficiently.
从专用芯片(Application Specific Integrated Circuit，ASIC)过渡到片上系统，虽然在单一芯片上包含的功能越来越多，但同时对片上系统进行验证所带来的挑战也越来越大。当芯片的规模变得很庞大时，传统的验证方法已经无能为力。在寄存器传输级(Register Transfer Level，RTL)进行验证时，由于使用硬件仿真器所导致的仿真速度很低，且验证耗时很大。此外，由于寄存器传输级验证缺乏对软／硬件并行开发的支持，不利于快速进行软／硬件协同验证。
为了克服传统验证方法的局限性，本文提出了新的SoC验证方法——基于随机测试的SoC系统级验证方法。该方法源于新的验证思想，即在SoC设计的更早期发现更多的功能性设计错误。
论文的开始介绍了SoC系统级验证方法学和有关随机测试的理论，这两方面是进行论文研究的背景知识。新的SoC验证方法是在上述两方面知识的基础上提出的。
在本文的研究中，采用基于SystemC和SCV(SystemC Verification Standard)验证库的方法来创建系统级的测试平台。具体地说，在系统级验证中所使用的测试平台是采用SystemC 2.0描述的，系统级测试平台中测试向量的生成是根据SCV验证库的三种随机化机制：直接随机化、带权重的随机化和带约束的随机化。
新的验证方法可以在SoC系统级验证平台上执行，这一平台是在Sun Blade2000工作站上通过集成编译、连接和调试工具、安装SystemC库和SCV验证库构建而成的。论文中的SoC系统级验证平台是WHU SLD 1.0的一部分，WHUSLD 1.0是在研究SoC软／硬件协同设计和协同验证这一国家863项目过程中开发出来的工具原型。
通过对4×4包交换芯片的系统级模型进行一系列的验证实验，证实了基于随机测试的SoC系统级验证方法是可行的。论文具体阐述了如何创建系统级测试平台、如何对测试平台和被验证对象(Design Under Verification，DUV)进行绑定、如何根据SCV验证库的三种随机测试向量生成方法生成测试激励。针对4×4包交换芯片系统级模型不同方面的功能，论文完成了4个验证实验：通过对实验结果进行分析，反过来对论文中所提出的新的SoC验证方法进行了评估。结论表明，本文提出的验证方法能够有效地完成SoC系统级验证。
According to Moore's Law, the number of transistors per chip doubles every 18 to 24 months. The escalation in gate count has enabled the electronics industry to make major strides in producing smaller and faster consumer and communication products. The development of microelectronics makes these products contain multiple functions on a single IC (Integrated circuit), supported by various custom-designed and third-party Intellectual Property (IP). These single chip systems are called SoC (System-on-Chip).
Although the advance from ASIC (Application Specific Integrated Circuit) to SoC can provide more and more functionality for a single chip, it presents enormous verification challenges for SoC designs. The traditional verification methods become less and less powerful as the scale and complexity increase. During RTL (Register Transfer Level) verification, the using of HDL (Hardware Description Language) software simulators has been proven to be inefficient and more time-consuming. In additional, these approaches lack the parallelism needed to rapidly verify the interaction between hardware and software blocks in a SoC design.
In order to deal with the above limitations during the conventional verification, a new verification methodology for SoCs, methodology of SoC system level verification based on random testing, is proposed and established in the dissertation. On one hand, the new verification methodology is derived from the criteria: find more functional errors in the earlier SoC design cycles compared with register transfer level. On the other hand, the new verification methodology has deployed a feasible technique that can address the verification bottleneck for SoC design.
The methodology of SoC system level verification and the theory of random testing are introduced directly at the start of this dissertation, which are the background for researches in the thesis. In fact, the new SoC verification methodology is brought forward based on knowledge in the above two aspects.
Apart from the basic knowledge, the research of creating testbench for system level verification is on the basis of SystemC and SystemC Verification Standard (SCV). Specifically, testbench for system level verification according to the new methodology is described using SystemC 2.0. Moreover, test cases for the system level testbench is generated according to three different mechanisms of randomisation based on SystemC Verification Standard specification, which consist of direct randomisation, weighted randomisation and constrained randomisation typically used in verification.
The new verification approach can be implemented on the platform of SoC system level verification, which is constructed by integrating compiling, linking and debugging tools and installing SystemC and SystemC Verification Standard libraries on a Sun Blade 2000 workstation. Actually the platform is a part of WHU SLD 1.0 that is the tool prototype for SoC system level design developed in a National 863 Project about researches on SoC hardware/software co-design and co-verification.
The methodology of SoC system level verification based on random testing is demonstrated on a series of experiments, which implement functional verifications on system level models of 4 X 4 package switch. The thesis sets forth in detail how to create system level testbench for the verification, how to bind the testbench and the
Design Under Verification (DUV) and how to generate test stimuli in accordance with three types of randomization in SystemC Verification Standard. Through analysing results of four different experiments that verified different functions provided with the system level model of 4 X 4 package switch, the new verification method put forward in this dissertation has been evaluated contrarily. The results have indicated that the method proposed in the paper can be used to fulfill SoC system level verification efficiently.
引文
[1] K. Suzuki, A. Sangiovanni-Vincentelli. Efficient Software Performance Estimation Methods for Hardware/Software Codesign Proc. of the 33rd annual conference on Design automation conference, pp. 605-610, Las Vegas, Nevada, United States, 1996.
[2] P. Chauhan, E. Clarke, Y. Lu, and D. Wang. Verifying IP core based System on Chip designs. Proc. of the IEEE ASIC conference, pp.206-211, Washington DC, USA, September 1999.
[3] Cadence. THE UNIFIED VERIFICATION METHODOLOGY. http://www.cadence.com, 2003.
[4] A. Silburt, I. Perryman, J. Bergeron, S. Nichols, M. Dufresne, and G. Ward. Accelerating concurrent hardware design with behavioural modelling and system simulation, Proc. of the 32nd ACM/IEEE conference on Design automation conference, pp.528-533, San Francisco, California, United States, Jun. 1995.
[5] J. Connell, B. Johnson. Early Hardware/Software Integration Using SystemC 2.0. Class 552, ESC, pp. 67-71, San Francisco, United States, 2002.
[6] P. Rashinkar, P. Paterson, and L. Singh. System-on-a-chip Verification: Methodology and Techniques. Kluwer Academic Publishers, 2001.
[7] D. Geist, G. Biran, T. Arons, M. Slavkin, Y. Nustov, M. Farkas, and K. Holtz. A Methodology For the Verification of a System on Chip. Proc. of the 36th Conference on Design Automation, pp. 115-120, New Orleans, LA, USA, ACM Press, 1999.
[8] A. Higashi, K. Tamaki, and T. Sasaki. Verification Methodology for a complex System-on-a-Chip. FUJITSU Sci. Tech. J., 36, 1, UDC 621.3.049.771. 14.001.63, June 2000.
[9] B. Cassagnol, S. Weber, D. Kloper, S. Gupta, B. Bautz, and E. J-Ahmadi. Codesigning a complete system on a chip with behavioral models. Integrated system design, pp.12-16, Eedesign Press, November 1998.
[10] M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiovanni-Vincentelli. Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. Proc. of the 38th conference on Design automation, pp. 667-672, Las Vegas, Nevada, United States, June 2001.
[11] G. Siwinski. System-On-Chip Verification Methodology. http://klabs.org/richcontent/MAPLDCon03/abstracts/siwinski_a.pdf, 2003.
[12] A. Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, M. Molcho, and G. Shurek. Test program generation for functional verification of powerpc processors in IBM. Proc. of Design Automation Conference, pp. 345-351, New York, United States, 1995.
[13] T.W. Albrecht, J. Notbauer, and S. HW/SW Coverification performance estimation and benchmark for a 24 Embedded RISC core design Rohringer. Proc. of the 35th annual conference on Design automation conference San Francisco, pp. 808-811, California, United States, 1998.
[14] ARM Co., Ltd. AMBA~(TM) Specification (Rev2.0). http://www.arm. com, 2002.
[15] Cadence. TRANSACTION-LEVEL MODELS: AN OVERVIEW IN THE CONTEXT OF THE UNIFIED VERIFICATION METHODOLOGY. http://www.cadence.com, 2003.
[16] Cadence. Creating a Functional Virtual Prototype. http://www.cadence.com, 2003.
[17] Cadence. DSP and Communication Design and Verification: USING CADENCE INCISIVE-SPW TO CREATE AND VALIDATE YOUR DESIGN. http://www.cadence.com, 2003.
[18] Cadence. Creating Analogue Behavioural Models. VERILOG-AMS ANALOG MODELING. http://www.cadence.com, 2003.
[19] L. Séméria. G. D. Micheli. Synthesis of pointers in application of pointer analysis to the behavioral synthesis from C. Proc. of the International Conference on Computer-Aided Design ICCAD'98, pp.321-326, San Jose, California, USA, Nov. 1998.
[20] A. Chandra, V. Iyengar, D.Jameson, R. Jawalkelar, I. Nair, B. Rosen, M. Mullen, J. Yoon, R. Armoni, D. Geist, and Y. Wolfsthal. A test Case Generator for Architecture Verification. IEEE Transactions on VLSI Systems, Vol. 6, No. 6, pp. 59-64, 1995.
[21] Synopsys Inc. General manager's column verification avenue. The Synopsys technical bulletin for design and verification engineers, Vol.3, issue 2, http://www.synopsys.com/news/pubs/veritb/ q203/veri_vol3_issl.pdf, May 2003.
[22] Cadence. Reusing Functional Virtual Prototype (FVP) Components in a Testbench: CREATING RESPONSE CHECKERS USING TRANSACTIONAL-LEVEL MODELS (TLMs). http://www.cadence.com, 2003.
[23] K. Keutzer. Hardware/software co-simulation. Proc. of the 31st annual
conference on Design automation conference, pp. 439-440, San Diego, California, United States, 1994.
[24] Cadence. Accelerated Transaction Based Co-simulation. http://www.cadence.com, 2003.
[25] L. Séméria, A. Ghosh. Methodology for hardware/software co-verification in C/C++. Proc. of the 2000 conference on Asia and South Pacific design automation, pp. 405-408, Yokohama, Japan, 2000.
[26] S. Liao, S. Tjiang, and R. Gupta. An efficient implementation of reactivity for modeling hardware in the scenic design environment. Proc. Of ACM IEEE Design Automation Conference, pp. 70-75, Anaheim, California, USA, 1997.
[27] G. Post, A. Muller, and T. Grotker. A system-level co-verification environment for ATM hardware design. Proc. of the conference on Design, automation and test. pp. 424-428, Paris, France, 1998.
[28] P.A. Hsiuing.Formal Synthesis and Code Generation of Embedded Real-Time Software. Proc. Of the ACM/IEEE 9th International Symposium on Hardware/Software Codesign, pp. 208-213, Copenhagen, Denmark, ACM Press, New York, USA, April 2001.
[29] L.A. Cortés. A Petri Net based Modeling and Verification Technique for Real-Time Embedded Systems. Department of Computer and Information Science, School of Engineering, Linkping universitet, Sweden, 2001.
[30] Synopsys Inc. Simulation Technology for Complex SoC Design Verification. http://www.synopsis.com/products/simulation/scirocco/scirocco_wp.html, 2000.
[31] P. Paulin, C. Pilkington, and E. Bensoudane. A System-Level Exploration Platform for Network Processors. Proc. of IEEE Design & Test of Computers, Vol. 18, No. 6, pp. 17-26, 2002.
[32] A. Fin, F. Fummi. A Web-CAD methodology for IP-Core analysis and simulation. Proc. of ACM/IEEE Design Automation Conference, pp.597-600, New Orleans, Louisiana, USA, pp. 16-20, Jun.2000.
[33] V. Singhal, J. Higgins. Compliance Verification for SoC and IP Interfaces. Proc. Of DesignCon 2002, pp. 59-61, California, USA, January 2002.
[34] E.M. Rudnick, J. H. Patel, G. S. Greenstein, and T. M. Niermann. A genetic algorithm framework for test generation. IEEE Transaction on Computer-Aided Design, Vol. 16, No. 9, pp. 1034-1044, Sept. 1997.
[35] S. Ntafos. On Random and Partition Testing. Proc. of ISSTA-98 in ACM SIGSOFT Software Engineering Notes, Vol.23, No. 2, pp.42-48, March 1998.
[36] SystemC Verification Working Group. SystemC Verification Standard Specification (Version 1. Oe). http://www.systemc.org, 2003.
[37] Synopsys. SystemC Versioin 2.0 User's Guide. http://www. systemc.org, 2002.
[38] Synopsys Inc. Functional Specification for SystemC2.0-Q. http://www.systemc.org, 2002.
[39] W. Mueller. The Simulation Semantics of SystemC. Proc. of the conference on Design, automation and test in Europe, pp. 64-70, Munich, Germany, 2001.
[40] A.Fin, F.Fummi, and G.Pravadelli. A multi-language environment for functional test generation. Proc. of IEEE International Test Conference (ITC), pp.821-829, Portland, Maryland, USA, 2001.
[41] I. Bolsens, H. J. De Man, B. Lin, K. V. Rompaey, S. Vercauteren, and D.Verkest. Hardware/software co-design of digital telecommunication systems. Proc. of IEEE, vol. 85, pp. 391—418, New York, United States, 1997.
[42] S. Pasricha. Transaction Level Modeling of SoC with SystemC 2.0. Proc. of Synopsys User Group Conference, pp. 236-240, STARC Press, 2002.
[43] J. Gerlach, W. Rosenstiel. System Level Design Using the SystemC Modeling Platform. Proc. of the 3rd Workshop on System Design Automation, pp.185-189, Rathen, Germany, 2000.
[44] K.Keutzer, S.Malik, R.Newton, J. Rabaey, and A. Sangiovanni-Vincentelli. System Level Design: Orthogonalization of Concerns and Platform-Based Design.IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 19, No. 12, 2000.
[45] R. Grinwald, E. Harel, M. Orgad, S. Ur, and A. Ziv. User defined coverage-a tool supported methodology for design verification. Proc. of the 35th annual conference on Design automation conference, pp.158-163, San Francisco, California, United States, June 15-19, 1998.
[46] Mentor Graphics Co.Ltd. Seamless User's and Reference Manual (Software Version 5.0). http://www.mentor.com, 2003.
[47] Cadence. The Role of Assertions in Verification Methodologies: USING ASSERTIONS IN A SIMULATION ENVIRONMENT. http://www.cadence.com, 2003.
[48] A. Genusov, O. Petlin, L. Wakeman. Methodology and Code Reuse in the verification of Telecommunication SoCs. Proc. 13th Annual IEEE Internatioal ASIC/SOC Conference System-On-Chip in the Internet Age, pp. 103-107, Hyatt Regency Crystal City, Washington, DC, September 2000.
[2] P. Chauhan, E. Clarke, Y. Lu, and D. Wang. Verifying IP core based System on Chip designs. Proc. of the IEEE ASIC conference, pp.206-211, Washington DC, USA, September 1999.
[3] Cadence. THE UNIFIED VERIFICATION METHODOLOGY. http://www.cadence.com, 2003.
[4] A. Silburt, I. Perryman, J. Bergeron, S. Nichols, M. Dufresne, and G. Ward. Accelerating concurrent hardware design with behavioural modelling and system simulation, Proc. of the 32nd ACM/IEEE conference on Design automation conference, pp.528-533, San Francisco, California, United States, Jun. 1995.
[5] J. Connell, B. Johnson. Early Hardware/Software Integration Using SystemC 2.0. Class 552, ESC, pp. 67-71, San Francisco, United States, 2002.
[6] P. Rashinkar, P. Paterson, and L. Singh. System-on-a-chip Verification: Methodology and Techniques. Kluwer Academic Publishers, 2001.
[7] D. Geist, G. Biran, T. Arons, M. Slavkin, Y. Nustov, M. Farkas, and K. Holtz. A Methodology For the Verification of a System on Chip. Proc. of the 36th Conference on Design Automation, pp. 115-120, New Orleans, LA, USA, ACM Press, 1999.
[8] A. Higashi, K. Tamaki, and T. Sasaki. Verification Methodology for a complex System-on-a-Chip. FUJITSU Sci. Tech. J., 36, 1, UDC 621.3.049.771. 14.001.63, June 2000.
[9] B. Cassagnol, S. Weber, D. Kloper, S. Gupta, B. Bautz, and E. J-Ahmadi. Codesigning a complete system on a chip with behavioral models. Integrated system design, pp.12-16, Eedesign Press, November 1998.
[10] M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiovanni-Vincentelli. Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. Proc. of the 38th conference on Design automation, pp. 667-672, Las Vegas, Nevada, United States, June 2001.
[11] G. Siwinski. System-On-Chip Verification Methodology. http://klabs.org/richcontent/MAPLDCon03/abstracts/siwinski_a.pdf, 2003.
[12] A. Aharon, D. Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, M. Molcho, and G. Shurek. Test program generation for functional verification of powerpc processors in IBM. Proc. of Design Automation Conference, pp. 345-351, New York, United States, 1995.
[13] T.W. Albrecht, J. Notbauer, and S. HW/SW Coverification performance estimation and benchmark for a 24 Embedded RISC core design Rohringer. Proc. of the 35th annual conference on Design automation conference San Francisco, pp. 808-811, California, United States, 1998.
[14] ARM Co., Ltd. AMBA~(TM) Specification (Rev2.0). http://www.arm. com, 2002.
[15] Cadence. TRANSACTION-LEVEL MODELS: AN OVERVIEW IN THE CONTEXT OF THE UNIFIED VERIFICATION METHODOLOGY. http://www.cadence.com, 2003.
[16] Cadence. Creating a Functional Virtual Prototype. http://www.cadence.com, 2003.
[17] Cadence. DSP and Communication Design and Verification: USING CADENCE INCISIVE-SPW TO CREATE AND VALIDATE YOUR DESIGN. http://www.cadence.com, 2003.
[18] Cadence. Creating Analogue Behavioural Models. VERILOG-AMS ANALOG MODELING. http://www.cadence.com, 2003.
[19] L. Séméria. G. D. Micheli. Synthesis of pointers in application of pointer analysis to the behavioral synthesis from C. Proc. of the International Conference on Computer-Aided Design ICCAD'98, pp.321-326, San Jose, California, USA, Nov. 1998.
[20] A. Chandra, V. Iyengar, D.Jameson, R. Jawalkelar, I. Nair, B. Rosen, M. Mullen, J. Yoon, R. Armoni, D. Geist, and Y. Wolfsthal. A test Case Generator for Architecture Verification. IEEE Transactions on VLSI Systems, Vol. 6, No. 6, pp. 59-64, 1995.
[21] Synopsys Inc. General manager's column verification avenue. The Synopsys technical bulletin for design and verification engineers, Vol.3, issue 2, http://www.synopsys.com/news/pubs/veritb/ q203/veri_vol3_issl.pdf, May 2003.
[22] Cadence. Reusing Functional Virtual Prototype (FVP) Components in a Testbench: CREATING RESPONSE CHECKERS USING TRANSACTIONAL-LEVEL MODELS (TLMs). http://www.cadence.com, 2003.
[23] K. Keutzer. Hardware/software co-simulation. Proc. of the 31st annual
conference on Design automation conference, pp. 439-440, San Diego, California, United States, 1994.
[24] Cadence. Accelerated Transaction Based Co-simulation. http://www.cadence.com, 2003.
[25] L. Séméria, A. Ghosh. Methodology for hardware/software co-verification in C/C++. Proc. of the 2000 conference on Asia and South Pacific design automation, pp. 405-408, Yokohama, Japan, 2000.
[26] S. Liao, S. Tjiang, and R. Gupta. An efficient implementation of reactivity for modeling hardware in the scenic design environment. Proc. Of ACM IEEE Design Automation Conference, pp. 70-75, Anaheim, California, USA, 1997.
[27] G. Post, A. Muller, and T. Grotker. A system-level co-verification environment for ATM hardware design. Proc. of the conference on Design, automation and test. pp. 424-428, Paris, France, 1998.
[28] P.A. Hsiuing.Formal Synthesis and Code Generation of Embedded Real-Time Software. Proc. Of the ACM/IEEE 9th International Symposium on Hardware/Software Codesign, pp. 208-213, Copenhagen, Denmark, ACM Press, New York, USA, April 2001.
[29] L.A. Cortés. A Petri Net based Modeling and Verification Technique for Real-Time Embedded Systems. Department of Computer and Information Science, School of Engineering, Linkping universitet, Sweden, 2001.
[30] Synopsys Inc. Simulation Technology for Complex SoC Design Verification. http://www.synopsis.com/products/simulation/scirocco/scirocco_wp.html, 2000.
[31] P. Paulin, C. Pilkington, and E. Bensoudane. A System-Level Exploration Platform for Network Processors. Proc. of IEEE Design & Test of Computers, Vol. 18, No. 6, pp. 17-26, 2002.
[32] A. Fin, F. Fummi. A Web-CAD methodology for IP-Core analysis and simulation. Proc. of ACM/IEEE Design Automation Conference, pp.597-600, New Orleans, Louisiana, USA, pp. 16-20, Jun.2000.
[33] V. Singhal, J. Higgins. Compliance Verification for SoC and IP Interfaces. Proc. Of DesignCon 2002, pp. 59-61, California, USA, January 2002.
[34] E.M. Rudnick, J. H. Patel, G. S. Greenstein, and T. M. Niermann. A genetic algorithm framework for test generation. IEEE Transaction on Computer-Aided Design, Vol. 16, No. 9, pp. 1034-1044, Sept. 1997.
[35] S. Ntafos. On Random and Partition Testing. Proc. of ISSTA-98 in ACM SIGSOFT Software Engineering Notes, Vol.23, No. 2, pp.42-48, March 1998.
[36] SystemC Verification Working Group. SystemC Verification Standard Specification (Version 1. Oe). http://www.systemc.org, 2003.
[37] Synopsys. SystemC Versioin 2.0 User's Guide. http://www. systemc.org, 2002.
[38] Synopsys Inc. Functional Specification for SystemC2.0-Q. http://www.systemc.org, 2002.
[39] W. Mueller. The Simulation Semantics of SystemC. Proc. of the conference on Design, automation and test in Europe, pp. 64-70, Munich, Germany, 2001.
[40] A.Fin, F.Fummi, and G.Pravadelli. A multi-language environment for functional test generation. Proc. of IEEE International Test Conference (ITC), pp.821-829, Portland, Maryland, USA, 2001.
[41] I. Bolsens, H. J. De Man, B. Lin, K. V. Rompaey, S. Vercauteren, and D.Verkest. Hardware/software co-design of digital telecommunication systems. Proc. of IEEE, vol. 85, pp. 391—418, New York, United States, 1997.
[42] S. Pasricha. Transaction Level Modeling of SoC with SystemC 2.0. Proc. of Synopsys User Group Conference, pp. 236-240, STARC Press, 2002.
[43] J. Gerlach, W. Rosenstiel. System Level Design Using the SystemC Modeling Platform. Proc. of the 3rd Workshop on System Design Automation, pp.185-189, Rathen, Germany, 2000.
[44] K.Keutzer, S.Malik, R.Newton, J. Rabaey, and A. Sangiovanni-Vincentelli. System Level Design: Orthogonalization of Concerns and Platform-Based Design.IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 19, No. 12, 2000.
[45] R. Grinwald, E. Harel, M. Orgad, S. Ur, and A. Ziv. User defined coverage-a tool supported methodology for design verification. Proc. of the 35th annual conference on Design automation conference, pp.158-163, San Francisco, California, United States, June 15-19, 1998.
[46] Mentor Graphics Co.Ltd. Seamless User's and Reference Manual (Software Version 5.0). http://www.mentor.com, 2003.
[47] Cadence. The Role of Assertions in Verification Methodologies: USING ASSERTIONS IN A SIMULATION ENVIRONMENT. http://www.cadence.com, 2003.
[48] A. Genusov, O. Petlin, L. Wakeman. Methodology and Code Reuse in the verification of Telecommunication SoCs. Proc. 13th Annual IEEE Internatioal ASIC/SOC Conference System-On-Chip in the Internet Age, pp. 103-107, Hyatt Regency Crystal City, Washington, DC, September 2000.