先进的3D叠层芯片封装工艺及可靠性研究
摘要
上个世纪九十年代,棚球阵列(BGA)封装替代了外引脚封装,焊料球凸点面阵使封装尺寸减小,输入和输出端口数增加,功能和性能增强。然而,随着封装技术的发展,在平面方向上的封装已经达到了极限。为了克服平面封装技术的瓶颈,人们开发了一种三维封装技术,即叠层封装。随着硅片减薄技术的成功使用,多芯片叠层封装的厚度几乎与过去BGA封装具有相同的厚度(约1.2毫米)。因此,三维叠层封装能有效地增强电子产品的功能,目前已成为业界最流行的封装技术。
本论文首先分析了3D叠层芯片封装工艺的难点,包括圆片减薄后发生翘曲的解决方案,薄裸芯片的粘贴,低弧度金线的键合,以及封装芯片的潮湿敏感度等级等,并提出了相应的解决方案。然后,采用环氧树脂代替传统的蓝膜作为芯片间的粘贴材料,安排工艺认证。封装后对相应产品进行X射线和C—SEM检测,发现芯片、引脚和框架没有出现明显分层现象,焊线无缺陷,绕线也在规定的误差范围内。进一步地,本论文对该封装产品的可靠性进行了研究,包括恒温恒湿实验、非偏置的高速加速应力测试、高低温循环测试以及高温存放实验。结果表明,所有封装样品均通过上述可靠性测试,没有出现不合格样品。最后,本论文研究了USB四层堆叠球焊工艺,探讨了工艺参数对叠层球焊工艺性能的影响。当采用高低倍同时编程的方式打线时,高倍打线准确,低倍打线会出现十字线偏移,但总体情况良好。通过对金线的拉力和焊球的推力测试,发现金线所能承受的平均拉力在8-13g范围内,焊球所能承受的平均推力在22-28g范围内,上述结果均分别高于其技术标准值5g和13g。总之,本文的实验工作加深了对叠层封装工艺的了解,对提升产品的合格率起到良好的效果。
Since the 1990s, Ball Grid Array (BGA) has gradually replaced the traditional leaded package and become more and more popular. This has caused some advantages such as reduction of the package size, an increase in the number of the input and output ports, and enhancement of the function and performance. However, with the development of advanced packaging technology, the 2-dimensional (2-D) package has reached its limit. In order to overcome the bottleneck of the 2-D package technology, a three-dimensional (3-D) package technology has been proposed. The successful thinning of wafer by back-grinding has made the thickness of the 3-D multi-chip stacked die package similar to that of BGA (about 1.2 mm). Therefore, the 3-D stacked chip package can effectively increase the function of electronic devices, and has already become a very popular packaging method for semiconductor industry.
In my thesis, the key difficulties for the 3-D stacked chip package were analyzed firstly, including wafer back-grinding, die attach, low radian wire bonding and chip MSL etc, and the corresponding solutions were proposed. Then, a stacked chip package qualification experiment was done by using epoxy resin film at the die attachment stage, instead of the traditional blue film. Both X-ray and C-SEM inspections did not reveal any delamination on chips, pins and lead frames, and any defect for the soldering wires etc. Further, the reliability of the package was evaluated, including TH, UHAST, TCT and HTSL measurements. The results indicated that all the samples passed this reliability experiment, no sample failed. Finally, the process of USB four layer stacked chips was investigated, and the influence of the process parameters on the performance of wire bonding was explored. It is found that although there was little cross line migration, in general the wire bonding was in good condition. Based on the ball shear and wire pull test experiments, it is found that the average wire pull force was between 8g and 13g, and the average ball shear force was between 22g and 28g. These data are higher than its technical standard, i.e.,5g for the wire pull force and 13g for the ball shear force. In conclusion, the experimental work in my thesis let us have deep understanding on the knowledge of the 3D stacked die package process, and contributed a lot to improve the yield of products.
本论文首先分析了3D叠层芯片封装工艺的难点,包括圆片减薄后发生翘曲的解决方案,薄裸芯片的粘贴,低弧度金线的键合,以及封装芯片的潮湿敏感度等级等,并提出了相应的解决方案。然后,采用环氧树脂代替传统的蓝膜作为芯片间的粘贴材料,安排工艺认证。封装后对相应产品进行X射线和C—SEM检测,发现芯片、引脚和框架没有出现明显分层现象,焊线无缺陷,绕线也在规定的误差范围内。进一步地,本论文对该封装产品的可靠性进行了研究,包括恒温恒湿实验、非偏置的高速加速应力测试、高低温循环测试以及高温存放实验。结果表明,所有封装样品均通过上述可靠性测试,没有出现不合格样品。最后,本论文研究了USB四层堆叠球焊工艺,探讨了工艺参数对叠层球焊工艺性能的影响。当采用高低倍同时编程的方式打线时,高倍打线准确,低倍打线会出现十字线偏移,但总体情况良好。通过对金线的拉力和焊球的推力测试,发现金线所能承受的平均拉力在8-13g范围内,焊球所能承受的平均推力在22-28g范围内,上述结果均分别高于其技术标准值5g和13g。总之,本文的实验工作加深了对叠层封装工艺的了解,对提升产品的合格率起到良好的效果。
Since the 1990s, Ball Grid Array (BGA) has gradually replaced the traditional leaded package and become more and more popular. This has caused some advantages such as reduction of the package size, an increase in the number of the input and output ports, and enhancement of the function and performance. However, with the development of advanced packaging technology, the 2-dimensional (2-D) package has reached its limit. In order to overcome the bottleneck of the 2-D package technology, a three-dimensional (3-D) package technology has been proposed. The successful thinning of wafer by back-grinding has made the thickness of the 3-D multi-chip stacked die package similar to that of BGA (about 1.2 mm). Therefore, the 3-D stacked chip package can effectively increase the function of electronic devices, and has already become a very popular packaging method for semiconductor industry.
In my thesis, the key difficulties for the 3-D stacked chip package were analyzed firstly, including wafer back-grinding, die attach, low radian wire bonding and chip MSL etc, and the corresponding solutions were proposed. Then, a stacked chip package qualification experiment was done by using epoxy resin film at the die attachment stage, instead of the traditional blue film. Both X-ray and C-SEM inspections did not reveal any delamination on chips, pins and lead frames, and any defect for the soldering wires etc. Further, the reliability of the package was evaluated, including TH, UHAST, TCT and HTSL measurements. The results indicated that all the samples passed this reliability experiment, no sample failed. Finally, the process of USB four layer stacked chips was investigated, and the influence of the process parameters on the performance of wire bonding was explored. It is found that although there was little cross line migration, in general the wire bonding was in good condition. Based on the ball shear and wire pull test experiments, it is found that the average wire pull force was between 8g and 13g, and the average ball shear force was between 22g and 28g. These data are higher than its technical standard, i.e.,5g for the wire pull force and 13g for the ball shear force. In conclusion, the experimental work in my thesis let us have deep understanding on the knowledge of the 3D stacked die package process, and contributed a lot to improve the yield of products.
引文
[1]李丙宗.半导体工艺技术[M].上海：复旦大学出版社,2006：8.
[2]谢庆吴兆华.高密度组装电气互联新技术原理与研究方法[J].电子工艺技术,2003,24(2)：47-49.
[3]杨建生.BGA多芯片组件及三维立体封装(3D)技术[J].电子与封装,2003,3(1)：34-38.
[4]高尚通.跨世纪的微电子封装[J].半导体情报,2000,37(6)：1-7.
[5]高尚通杨克武.新型微电子封装技术[J].电子与封装,2004,1：10-23.
[6]成立王振宇景亮.SOC设计：IC产业链设计史上的重大革命[J].半导体技术,2004,29(12)：8-12.
[7]成立李春明王振宇高平.IC产业链中的新技术应用与产业发展对策[J].半导体技术,2004,29(6)：57—63.
[8]李加元成立王振宇李华乐贺星.系统芯片设计中的可复用IP技术[J].半导体技术,2006,31(1)：15-18.
[9]杨建生.倒装芯片的高速度、低成本、无铅化挑战[J].电子与封装,2006,12(1)：30-36.
[10]杨建生.超薄型圆片级芯片尺寸封装技术[J].电子与封装,2006,9(1)：15-18.
[11]翁寿松.几种新的封装工艺[J].电子与封装,2007,02(1)：20-22.
[12]杜黎光.丝焊互连的高温可靠性和相关问题的研究[D].中国优秀博硕士学位论文全文数据库(博士),2001：
[13]黄卫东.高可靠性电子封装中防潮薄膜技术的研究[D].中国优秀博硕士学位论文全文数据库(博士),2003：
[14]蒋玉齐.高量程MEMS加速度计封装研究[D].中国优秀博硕士学位论文全文数据库(博士),2004：
[15]徐高卫.超级计算机子系统的热管理与无线传感网3D-MCM的设计制造及热机械可靠性研究[D].中国博士学位论文全文数据库,2007：
[16]堆叠式封装和组装技术的研究[D].天津大学,2006：
[17]孙宏伟.叠层芯片封装技术与工艺探讨[J].电子工业专用设备,2006,(05)：28-40.
[18]康雪晶.叠层芯片封装元件热应力分析及焊点寿命预测[J].电子元件与材料,2007.05：22-24.
[2]谢庆吴兆华.高密度组装电气互联新技术原理与研究方法[J].电子工艺技术,2003,24(2)：47-49.
[3]杨建生.BGA多芯片组件及三维立体封装(3D)技术[J].电子与封装,2003,3(1)：34-38.
[4]高尚通.跨世纪的微电子封装[J].半导体情报,2000,37(6)：1-7.
[5]高尚通杨克武.新型微电子封装技术[J].电子与封装,2004,1：10-23.
[6]成立王振宇景亮.SOC设计：IC产业链设计史上的重大革命[J].半导体技术,2004,29(12)：8-12.
[7]成立李春明王振宇高平.IC产业链中的新技术应用与产业发展对策[J].半导体技术,2004,29(6)：57—63.
[8]李加元成立王振宇李华乐贺星.系统芯片设计中的可复用IP技术[J].半导体技术,2006,31(1)：15-18.
[9]杨建生.倒装芯片的高速度、低成本、无铅化挑战[J].电子与封装,2006,12(1)：30-36.
[10]杨建生.超薄型圆片级芯片尺寸封装技术[J].电子与封装,2006,9(1)：15-18.
[11]翁寿松.几种新的封装工艺[J].电子与封装,2007,02(1)：20-22.
[12]杜黎光.丝焊互连的高温可靠性和相关问题的研究[D].中国优秀博硕士学位论文全文数据库(博士),2001：
[13]黄卫东.高可靠性电子封装中防潮薄膜技术的研究[D].中国优秀博硕士学位论文全文数据库(博士),2003：
[14]蒋玉齐.高量程MEMS加速度计封装研究[D].中国优秀博硕士学位论文全文数据库(博士),2004：
[15]徐高卫.超级计算机子系统的热管理与无线传感网3D-MCM的设计制造及热机械可靠性研究[D].中国博士学位论文全文数据库,2007：
[16]堆叠式封装和组装技术的研究[D].天津大学,2006：
[17]孙宏伟.叠层芯片封装技术与工艺探讨[J].电子工业专用设备,2006,(05)：28-40.
[18]康雪晶.叠层芯片封装元件热应力分析及焊点寿命预测[J].电子元件与材料,2007.05：22-24.