ULSI片内互连线寄生参数提取及应用
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摘要
半导体工艺水平的飞速提高使当今集成电路的发展进入超深亚微米(VDSM)阶段。随着系统芯片(SOC)的出现，片内互连线问题已经成为目前ULSI设计中最具挑战性的课题之一。互连的传输线效应成为限制系统整体性能的“瓶颈”。对于高速ULSI设计，传统EDA设计中采用的基于集总概念的参数提取算法已经失去准确性，寻求互新型电磁建模和参数提取方法具有至关重要的意义。它是一系列后续工作的基础。本文以片内互连线的关键长线为主要研究对象，侧重寄生参数提取方法的研究，以及基于互连模型分析各种寄生效应。研究方法从精度和速度两方面着手。文中研究内容可分为两部分：
■ 互连线寄生参数提取部分
1) 基于ULSI片内互连电感、电容参数提取问题的内容和特点，引入互连线不同相对几何位置的寄生参数解析计算公式，得到一类快速寄生电感、电容定界方法。
2) 提出一类基于牛顿法BP网络的互连线寄生电感提取方法；根据ULSI片上互连线曼哈顿结构特点，将ANN方法应用于多导体系统环电感分段计算，提出一种快速限制回路寄生电感提取方法。
3) 利用Csplat模拟互连线光刻，分析光刻中OPE对互连线版图的影响，针对版图畸变现象，采用二维BEM对电容参数作精确的实验性建模；定义有效长度概念，提出基于人工神经网络(ANN)实现多级导体系统寄生电容的快速提取方案。
■ 基于互连线RC、RLC模型的时序分析
1) 针对ULSI设计中常用的晶体管驱动的单条全局互连线，以一阶或二阶模型近似其末端电压，得到时延和过冲分析的简化解析模型；基于两条电容性耦合互连线基本微分方程，推导出低阶近似串扰解析模型，并推广至多条电容性耦合互连线情况。
2) 基于电源树的普通RLC模型与π型RLC模型，利用一类切换事件
驱动的节点重组及参数重编机制，将非线性噪声传播过程简化为线
性系统，实现PST噪声分析的时域解析方法，以提高模拟效率。
With fast advancing of semiconductor design and manufacture techniques, today's ultra-large-scale-integrated-circuits (ULSI) technology are made by very deep semimicrometer (VDSM) process. For a complicated SOC, on-chip interconnect is one of the most challenging problems. The parasitic effects of interconnects now are the bottleneck of the performance of the entire circuit system. The traditional methods of parasitic parameter extraction can't be as accurate as what they did any longer. Electromagnetic modeling and parameter extraction start playing a much more important role in IC design, and it is the foundation of the later works.
This dissertation deals mainly with long interconnects in ULSI, and focuses on parasitic parameter extraction and its application in time domain analysis. It can be divided into two parts:
Part 1: parasitic parameter extraction for on-chip interconnects
1) Based on analytical parasitic inductance and capacitance models of on-chip interconnects, which are arranged respectively according to their relative position, a fast method to determine the bounds of parasitic inductance and capacitance is presented.
2) A new inductance extraction method is presented based on the Newton-BP neural networks. At the same time, the neural network is introduced to calculate partial inductance of the multilevel interconnects; a modified-return-limited-inductance-extraction (MRLIE) method is discussed.
3) Csplat is used to simulate the optical proximity effect (OPE) which could affect the interconnect. Artificial neural networks and a new concept -efficient length, is introduced into the capacitance extraction procedure for multilevel interconnect system.
Part 2: time domain analysis based on RC/ RLC model of on-chip interconnects
1) According to the time-domain analysis theory, delay, overshoot and crosstalk which appear on long interconnects are modeled analytically using one or two first moments of the nonlinear solution.
2) Based on RLC model and n -type RLC model of the power supply trees (PST), a simultaneous switching noise (SSN) estimation method is presented. Switching-event-driven node-regroup and parameter reordering is used to turn the nonlinear noise process into linear system.
■ 互连线寄生参数提取部分
1) 基于ULSI片内互连电感、电容参数提取问题的内容和特点，引入互连线不同相对几何位置的寄生参数解析计算公式，得到一类快速寄生电感、电容定界方法。
2) 提出一类基于牛顿法BP网络的互连线寄生电感提取方法；根据ULSI片上互连线曼哈顿结构特点，将ANN方法应用于多导体系统环电感分段计算，提出一种快速限制回路寄生电感提取方法。
3) 利用Csplat模拟互连线光刻，分析光刻中OPE对互连线版图的影响，针对版图畸变现象，采用二维BEM对电容参数作精确的实验性建模；定义有效长度概念，提出基于人工神经网络(ANN)实现多级导体系统寄生电容的快速提取方案。
■ 基于互连线RC、RLC模型的时序分析
1) 针对ULSI设计中常用的晶体管驱动的单条全局互连线，以一阶或二阶模型近似其末端电压，得到时延和过冲分析的简化解析模型；基于两条电容性耦合互连线基本微分方程，推导出低阶近似串扰解析模型，并推广至多条电容性耦合互连线情况。
2) 基于电源树的普通RLC模型与π型RLC模型，利用一类切换事件
驱动的节点重组及参数重编机制，将非线性噪声传播过程简化为线
性系统，实现PST噪声分析的时域解析方法，以提高模拟效率。
With fast advancing of semiconductor design and manufacture techniques, today's ultra-large-scale-integrated-circuits (ULSI) technology are made by very deep semimicrometer (VDSM) process. For a complicated SOC, on-chip interconnect is one of the most challenging problems. The parasitic effects of interconnects now are the bottleneck of the performance of the entire circuit system. The traditional methods of parasitic parameter extraction can't be as accurate as what they did any longer. Electromagnetic modeling and parameter extraction start playing a much more important role in IC design, and it is the foundation of the later works.
This dissertation deals mainly with long interconnects in ULSI, and focuses on parasitic parameter extraction and its application in time domain analysis. It can be divided into two parts:
Part 1: parasitic parameter extraction for on-chip interconnects
1) Based on analytical parasitic inductance and capacitance models of on-chip interconnects, which are arranged respectively according to their relative position, a fast method to determine the bounds of parasitic inductance and capacitance is presented.
2) A new inductance extraction method is presented based on the Newton-BP neural networks. At the same time, the neural network is introduced to calculate partial inductance of the multilevel interconnects; a modified-return-limited-inductance-extraction (MRLIE) method is discussed.
3) Csplat is used to simulate the optical proximity effect (OPE) which could affect the interconnect. Artificial neural networks and a new concept -efficient length, is introduced into the capacitance extraction procedure for multilevel interconnect system.
Part 2: time domain analysis based on RC/ RLC model of on-chip interconnects
1) According to the time-domain analysis theory, delay, overshoot and crosstalk which appear on long interconnects are modeled analytically using one or two first moments of the nonlinear solution.
2) Based on RLC model and n -type RLC model of the power supply trees (PST), a simultaneous switching noise (SSN) estimation method is presented. Switching-event-driven node-regroup and parameter reordering is used to turn the nonlinear noise process into linear system.
引文
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[5] 李志坚，周润德．ULSI器件、电路与系统．科学出版社．2000．
[6] 陈宏毅．信息时代的微电子科学技术．集成电路设计，No．1，PP．1-14，2001
[7] Deutsch A. On chip wiring design challenges for gigahertz operation. In Proc. IEEE, Vol.89, No.4, pp. 529-553,2001.
[8] Mafferzzoni P. and Branbilla A. Modeling delay and crosstalk in VLSI interconnections for electrical simulation. Electronics letters,Vol.36, No.10, pp.862-864, 2000.
[9] Zhang Q. J., Wang F. and Nakhla M.S. et al. Signal integrity optimization of high speed VLSI packages and interconnects. In 48th IEEE electronic components and technology conference, pp. 1073-1076,1998.
[10] Deutsch A. Electrical characterics of interconnections for high performance systems. In Proc. IEEE, No.2, pp.315-355,1998.
[11] Tomita Y. Morifuji, T. and Tago, M. et al. Advanced packaging technologies on 3D stacked LSI utilizing the mocro interconnections and the layered microthin encapsulation. In proc. 51st electronic components and technology conference, pp.353-360, 2001.
[12] 王效平，刘捷臣．集成电路封装技术的现状和未来．微处理机，No．4，pp．1-8，1996
[13] 小原洋一，赫福申译．半导体封装技术的发展趋势．集成电路设计，No．1，pp．107-118，1999
[14] 李枚．微电子封装技术的发展与展望．半导体杂志．Vol．25，No．2，pp．32-35．2000
[15] Lin X W and Pramanik D. Future interconnect technologies and copper metallization. Solid State Technology, Vol.41, No. 10, pp.63-79, 1998
[16] Lee K. on chip interconnects--gigahertz and beyond. Solid State Technology, Vol.41, No.9, pp.85-89, 1998
[17] Korczynski E. Interconnect: the new frontier. Solid State Technology, Vol.41, No.9, pp.83-84, 1998.
[18] Shieh B, Saraswat K and Deal M, et al. Air gaps lower k of interconnect dielectrics. Solid State Technology, Vol.42, No.2, pp.51-58, 1999
[19] Deutsch A, kopcsay G V, and Surovic C W, et al. Modeling and characterization of long on-chip interconnections for high performance microprocessors. IBM J. Res. Dev., Vol.39, No.5, pp.547-567. 1995.
[20] Deutsch A, kopcsay G V, and Restle P J, et al. When are transmission line effects important for on-chip interconnections. IEEE Trans. MTT, Vol.45, No. 10, pp.1836-1846. 1997.
[21] Qi X, Wang G, Yu Z and Dutton R W. On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation[J]. IEEE CICC'00, 2000; 250-254.
[22] Coatache G I. Finite element mthod applied to the skin-effect problems in strip transmission lines. IEEE Trans. MIT. Vol.35, No. 11, pp. 1009-1013, 1987.
[23] Jin J. the finite element method in electromagnetics. New York: John Wiley & Sons, Inc., 1993.
[24] Zemanian A H. A finite-difference procedure for the exterior problem inherent in capacitance computation for VLSI interconnects. IEEE Trans. Educ. Vol.35, No.7, pp.985-992, 1988.
[25] Zemanian A H and Tewarson R P. Three dimensional xapacitance computations for VLSI/ULSI interconnections. IEEE Trans. CAD. Vol. 8, pp.1319-1326, 1989.
[26] Yee K S. Numerical solution of initial boundary value problems involving Maxwell's equations in isotropic media. IEEE Trans. Antennas Propagation, Vol.14, pp.302-307, 1996.
[27] Taflove A. Review of the formulation and applications of the finite-difference time-domain method for numerical modeling of electromagnetic wave interactions with arbitrary structures. Wave Motion, Vol. 10, pp.547-582, 1988.
[28] Kunz K and Luebbers R J. The finite-difference time-domain method for electromagnetics. CRC press, Inc., 1993
[29] Cao W, Harrington R F and Mantz J P et al. Multi conductor transmission lines in multilayered dielectric media. IEEE Trans. MTT, Vol.32, pp.439-450, 1984.
[30] Matthaei G L, Chinn G C and Plott C H, et al. A simplified means for computation of interconnects distributed capacitance and inductance. IEEE Trans. CAD. Vol.11, pp.513-524, 1992.
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