类数据流驱动的分片式处理器体系结构
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摘要
纳米工艺代微处理器设计中存在的功耗、线延迟和设计复杂度等问题严重地制约了传统的程序执行模型和处理器体系结构的发展。分片式处理器体系结构就是为了应对这些挑战性问题而产生的,其基本思想是将计算、存储和互连资源组织成片式的基本结构单元,这些片式单元是相对简单的、分布式控制且可重用的;大量的片式单元由高能效、可扩展的片上网络连接起来构成高效能的处理器。这种体系结构避免了片上长线延迟的产生,能够充分利用摩尔定律发展带来的丰富而廉价的晶体管资源,获得系统性能的提升。但目前分片式处理器体系结构还处于初级研究阶段,有许多关键技术值得探讨。
本文分别从分片式处理器的程序执行模型和体系结构两个方面开展了深入的研究。主要研究内容和成果包括:(1)研究了类数据流计算模型的原理,提出了一种适于分片式处理器体系结构的类数据流驱动程序执行模型。在该程序执行模型中,由编译器将串行程序划分成一系列包含几十至上百条指令的超块;程序的执行以超块为原子单位进行取指、执行和提交。超块内部的计算采用数据流表示,用数据流图作为机器语言,向硬件显式表达指令间的并行性,无需硬件动态检测依赖,从而降低了硬件设计的复杂性;超块间采用控制流表示,既可以有效地利用程序中的数据局部性,又可以进一步利用线程级推测并行性。(2)分析了类数据流驱动的分片式处理器体系结构的设计空间,研究了影响分片式处理器性能的关键因素。首先,为了提高分片式处理器上计算资源的利用率,分别从数据流和控制流的角度分析了激进推测执行的可行性,并对推测深度给出了量化的标准;其次,为了给分片式处理器选择合适的互连网络结构,分析了多种互连拓扑结构对处理器性能的影响;然后,为了缓解分片式处理器结构及其多跳式的互连结构可能对访存造成的影响,分析了多种应用在分片式处理器的访存特征,研究了数据预取机制对降低访存延迟的作用;最后,为了更准确地探究应用对结构的需求,综合分析了应用在类数据流驱动的程序执行模型上的行为特征。(3)研究了分片式处理器的优化设计方案,提出了一种既能充分挖掘并行性,又能有效降低通信代价的片式单元设计思想。将单个片式单元的计算复杂度限制在应用潜在的指令级并行粒度上,同时,结合程序的通信局部性特征适当增大片式单元内的局部通信相联度,而无需改变整体的通信网络设计。实验表明,这种设计思想既能够满足应用对于指令级并行性的需求,又能够有效地降低关键路径上的数据流通信延迟。(4)基于该优化设计方案,设计并实现了一种类数据流驱动的分片式处理器体系结构TPA-PI。TPA-PI处理器采用DISC-I指令集体系结构,遵循类数据流驱动的程序执行模型。TPA-PI在开发更大的指令级并行性、片式单元有限的计算能力以及日益严峻的线延迟约束之间为单个片式单元的设计找到一个较好的设计折衷点,使得TPA-PI设计具有较好的可扩展性。(5)在TPA-PI的软件模拟环境上,评估了类数据流驱动程序执行模型及TPA-PI体系结构设计的有效性。实验结果印证了类数据流驱动的程序执行模型与控制流执行模型相比所具有的性能优势、片式单元的设计思想的正确性以及优化后的TPA-PI体系结构设计的合理性。
本文的研究工作获得了如下一些重要的认识。首先,在分片式处理器体系结构设计中,程序执行模型、处理器核粒度、片上互连模型以及目标应用的特征都是影响其性能的重要因素。其次,将类数据流驱动的程序执行模型与分片式处理器相结合能够有效地利用片上提供的大量计算资源,在利用数据流驱动执行开发指令级并行性的同时,利用控制流的局部性开发更高层次的超块级和线程级并行性,适应不同特征的应用的需求。
本文的研究工作和结果可用于指导分片式处理器的体系结构设计和进一步的优化。
The development of traditional program execution model and processor architecture is restricted by many problems arose in nanometer technology designs, such as power dissipation, wire delay, design complexity, etc. Tiled processor architecture is a potential solution to these challenges. It organizes computation, storage and interconnects resources into basic tiled architectural units, which are relatively simple, distributed and reusable. A high-productivity processor could be composed of plenty of such tiled units, interconnected by highly efficient and scalable on-chip networks. In the tiled architecture, the design of single tile could be much less complicated, and the wire delay problem of long interconnect could be eliminated, and thus plentiful but cheap transistor resources introduced by Moore's Law could be fully utilized to achieve higher performance. However, tiled architecture is just under studies currently, and some key points need to be investigated and discussed.
This dissertation focuses on exploring and investigating the tiled processor architecture in the views of both execution model and architecture. The major research contributions include: (1) Based on the study of the theory of dataflow-like computation model, a novel dataflow-like driven program execution model which suits for tiled processor architecture is proposed. In this model, sequential program is partitioned into a series of VLIBs (Very Long Instruction Block), which may contain tens or hundreds of instructions and form the atomic units for instruction fetching, execution and commitment. The relationship intra-VLIB follows the dataflow style, in which dataflow diagram is introduced as the machine language to expose parallelism to hardware explicitly, so that the design complexity and costs on hardware of dynamic dependence detection could be alleviated. The control-flow style kept inter-VLIB could effectively utilize the dataflow locality in program, and exploit the parallelism from thread-level in the mean time. (2) The design space of dataflow-like driven architecture for tiled processor is further explored in many aspects, and the key factors which impact the performance are analyzed. Firstly, to improve the utilization of computational resources in tiled processor, the feasibility of aggressive speculative execution is studied in the aspects of dataflow and control-flow respectively, and a quantitative metric is given for the depth of speculation. Secondly, to determine a good topology of interconnect network for tiled processor, the impact of many topologies on processor performance are evaluated and analyzed. Thirdly, to alleviate the effect on memory access by tile processor architecture and multi-hop interconnect network, the behavior of memory access of many applications on tiled processor is analyzed, and the data prefetching scheme to reduce memory access latency on tiled processor is proposed and studied. Fourthly, a systematic analysis on the behaviors of applications executed on dataflow-like computing model is shown, and a more accurate requirement imposed on architecture is derived from applications. (3) An optimized scheme for tiled processor is investigated, and a novel proposal about tiled unit is presented, by which parallelism can be fully exploited and the cost on communication can be effectively reduced. The computing power of single tile should be restricted to the granularity of potential instruction-level parallelism of applications. Meanwhile, the local communicational connectivity should be increased proportionally according to locality of dataflow in program, without any impacts on the design of global communication network. Our experiments showed the need for instruction-level parallelism in applications could be met, and the communicational latencies in critical path could be effectively reduced. (4) Based on the above scheme, an optimized dataflow-like driven tiled processor architecture called TPA-PI is designed and implemented. In TPA-PI processor, an instruction set named DISC-I is defined and realized following the data-flow driven execution model. The design of TPA-PI Tile finds a good tradeoff among the exploitation of more instruction-level parallelism, the limited computing power of single tile and more serious restrictions of wire delay, which provides a good scalability on performance, architecture and technology. (5) Based on TPA-PI experimental platform, the effectiveness of Dataflow-like execution model and architectural design are evaluated. The experimental results verified the advantage of dataflow-like execution model on performance compared with control-flow execution model, the validity of proposal of tiled unit and the reasonableness of optimized TPA-PI architecture.
Based on the work of this dissertation, some important conclusions on dataflow-like driven tiled processor architecture are drawn as following: Firstly, the granularity of processor cores, execution model, on chip interconnect model and the selection of applications are key factors which determine the performance of dataflow-like driven tiled processor architecture. Secondly, the combination of dataflow-like driven program execution model and tiled processor architecture could utilize massive computational resources effectively, and it has a considerable potential to exploit parallelism both in instruction-level and thread-level, meeting the requirement of applications with arbitrary characteristic.The research and experimental results in this dissertation can provide direction for the design and optimization of tiled processor architecture.
本文分别从分片式处理器的程序执行模型和体系结构两个方面开展了深入的研究。主要研究内容和成果包括:(1)研究了类数据流计算模型的原理,提出了一种适于分片式处理器体系结构的类数据流驱动程序执行模型。在该程序执行模型中,由编译器将串行程序划分成一系列包含几十至上百条指令的超块;程序的执行以超块为原子单位进行取指、执行和提交。超块内部的计算采用数据流表示,用数据流图作为机器语言,向硬件显式表达指令间的并行性,无需硬件动态检测依赖,从而降低了硬件设计的复杂性;超块间采用控制流表示,既可以有效地利用程序中的数据局部性,又可以进一步利用线程级推测并行性。(2)分析了类数据流驱动的分片式处理器体系结构的设计空间,研究了影响分片式处理器性能的关键因素。首先,为了提高分片式处理器上计算资源的利用率,分别从数据流和控制流的角度分析了激进推测执行的可行性,并对推测深度给出了量化的标准;其次,为了给分片式处理器选择合适的互连网络结构,分析了多种互连拓扑结构对处理器性能的影响;然后,为了缓解分片式处理器结构及其多跳式的互连结构可能对访存造成的影响,分析了多种应用在分片式处理器的访存特征,研究了数据预取机制对降低访存延迟的作用;最后,为了更准确地探究应用对结构的需求,综合分析了应用在类数据流驱动的程序执行模型上的行为特征。(3)研究了分片式处理器的优化设计方案,提出了一种既能充分挖掘并行性,又能有效降低通信代价的片式单元设计思想。将单个片式单元的计算复杂度限制在应用潜在的指令级并行粒度上,同时,结合程序的通信局部性特征适当增大片式单元内的局部通信相联度,而无需改变整体的通信网络设计。实验表明,这种设计思想既能够满足应用对于指令级并行性的需求,又能够有效地降低关键路径上的数据流通信延迟。(4)基于该优化设计方案,设计并实现了一种类数据流驱动的分片式处理器体系结构TPA-PI。TPA-PI处理器采用DISC-I指令集体系结构,遵循类数据流驱动的程序执行模型。TPA-PI在开发更大的指令级并行性、片式单元有限的计算能力以及日益严峻的线延迟约束之间为单个片式单元的设计找到一个较好的设计折衷点,使得TPA-PI设计具有较好的可扩展性。(5)在TPA-PI的软件模拟环境上,评估了类数据流驱动程序执行模型及TPA-PI体系结构设计的有效性。实验结果印证了类数据流驱动的程序执行模型与控制流执行模型相比所具有的性能优势、片式单元的设计思想的正确性以及优化后的TPA-PI体系结构设计的合理性。
本文的研究工作获得了如下一些重要的认识。首先,在分片式处理器体系结构设计中,程序执行模型、处理器核粒度、片上互连模型以及目标应用的特征都是影响其性能的重要因素。其次,将类数据流驱动的程序执行模型与分片式处理器相结合能够有效地利用片上提供的大量计算资源,在利用数据流驱动执行开发指令级并行性的同时,利用控制流的局部性开发更高层次的超块级和线程级并行性,适应不同特征的应用的需求。
本文的研究工作和结果可用于指导分片式处理器的体系结构设计和进一步的优化。
The development of traditional program execution model and processor architecture is restricted by many problems arose in nanometer technology designs, such as power dissipation, wire delay, design complexity, etc. Tiled processor architecture is a potential solution to these challenges. It organizes computation, storage and interconnects resources into basic tiled architectural units, which are relatively simple, distributed and reusable. A high-productivity processor could be composed of plenty of such tiled units, interconnected by highly efficient and scalable on-chip networks. In the tiled architecture, the design of single tile could be much less complicated, and the wire delay problem of long interconnect could be eliminated, and thus plentiful but cheap transistor resources introduced by Moore's Law could be fully utilized to achieve higher performance. However, tiled architecture is just under studies currently, and some key points need to be investigated and discussed.
This dissertation focuses on exploring and investigating the tiled processor architecture in the views of both execution model and architecture. The major research contributions include: (1) Based on the study of the theory of dataflow-like computation model, a novel dataflow-like driven program execution model which suits for tiled processor architecture is proposed. In this model, sequential program is partitioned into a series of VLIBs (Very Long Instruction Block), which may contain tens or hundreds of instructions and form the atomic units for instruction fetching, execution and commitment. The relationship intra-VLIB follows the dataflow style, in which dataflow diagram is introduced as the machine language to expose parallelism to hardware explicitly, so that the design complexity and costs on hardware of dynamic dependence detection could be alleviated. The control-flow style kept inter-VLIB could effectively utilize the dataflow locality in program, and exploit the parallelism from thread-level in the mean time. (2) The design space of dataflow-like driven architecture for tiled processor is further explored in many aspects, and the key factors which impact the performance are analyzed. Firstly, to improve the utilization of computational resources in tiled processor, the feasibility of aggressive speculative execution is studied in the aspects of dataflow and control-flow respectively, and a quantitative metric is given for the depth of speculation. Secondly, to determine a good topology of interconnect network for tiled processor, the impact of many topologies on processor performance are evaluated and analyzed. Thirdly, to alleviate the effect on memory access by tile processor architecture and multi-hop interconnect network, the behavior of memory access of many applications on tiled processor is analyzed, and the data prefetching scheme to reduce memory access latency on tiled processor is proposed and studied. Fourthly, a systematic analysis on the behaviors of applications executed on dataflow-like computing model is shown, and a more accurate requirement imposed on architecture is derived from applications. (3) An optimized scheme for tiled processor is investigated, and a novel proposal about tiled unit is presented, by which parallelism can be fully exploited and the cost on communication can be effectively reduced. The computing power of single tile should be restricted to the granularity of potential instruction-level parallelism of applications. Meanwhile, the local communicational connectivity should be increased proportionally according to locality of dataflow in program, without any impacts on the design of global communication network. Our experiments showed the need for instruction-level parallelism in applications could be met, and the communicational latencies in critical path could be effectively reduced. (4) Based on the above scheme, an optimized dataflow-like driven tiled processor architecture called TPA-PI is designed and implemented. In TPA-PI processor, an instruction set named DISC-I is defined and realized following the data-flow driven execution model. The design of TPA-PI Tile finds a good tradeoff among the exploitation of more instruction-level parallelism, the limited computing power of single tile and more serious restrictions of wire delay, which provides a good scalability on performance, architecture and technology. (5) Based on TPA-PI experimental platform, the effectiveness of Dataflow-like execution model and architectural design are evaluated. The experimental results verified the advantage of dataflow-like execution model on performance compared with control-flow execution model, the validity of proposal of tiled unit and the reasonableness of optimized TPA-PI architecture.
Based on the work of this dissertation, some important conclusions on dataflow-like driven tiled processor architecture are drawn as following: Firstly, the granularity of processor cores, execution model, on chip interconnect model and the selection of applications are key factors which determine the performance of dataflow-like driven tiled processor architecture. Secondly, the combination of dataflow-like driven program execution model and tiled processor architecture could utilize massive computational resources effectively, and it has a considerable potential to exploit parallelism both in instruction-level and thread-level, meeting the requirement of applications with arbitrary characteristic.The research and experimental results in this dissertation can provide direction for the design and optimization of tiled processor architecture.
引文
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