嵌入式闪存测试技术研究
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摘要
众所周之,存储芯片本身在市场竞争中就异常激烈,大部份国内外芯片制造厂(FAB)都具备存储芯片制造的能力,从目前的趋势来看,测试是影响价格的最关键因素之一,所以如何降低测试成本,是一个需要长期重视的问题。同时也需要兼顾提高测试效率和测试可靠性。
本文作者所在公司主要生产0.13μm工艺嵌入式闪存(E-Flash),结合日常的嵌入式闪存芯片测试工作,和辅助工艺整合部门和器件设计部门人员对嵌入式闪存(E-Flash)进行的改良研究,得到了大量的工程测试数据。对新设计的电路和工艺进行参数和功能测试检查,使本款嵌入式闪存IP模块最终符合各项期望参数指标并满足量产的需求,并得出了许多新的测试方法。
首先,结合电路设计,列举了各种BIST(Built-in Self-test,内建自测试电路)设计的特点,芯片管脚数量的限制,主要的管脚功能以及各种电路设计给测试所带来的优缺点。根据实际所需,提供相应的最佳测试方案,同时也提到了一些常用的测试方法及测试参数,并对其进行了分析和研究,从而让大家理解到测试方法和参数之间所存在的相互制约的作用,得出了相关缺陷检查和弥补的方法。
其次,结合器件的工作特性,特别是对嵌入式闪存写操作工作特性进行了着重分析。从理论到实践,借用传统测试方法,尝试调整某些工艺参数,不断提高器件的工作稳定性和扩大参数的正常工作区域,最终达到有效提高成品率的目的。
再次,结合量产中的工程改进,针对优化测试程序所需要的缩短测试时间、优化测试流程及提高测试覆盖率问题,研究出一套完善的测试方法和验证手段。
最终,虽然本文中所列述的大部份的工程实际问题都已经基本解决,但本文作者对于这些问题的延伸和工程运用及拓展研究,还需要进一步去证实和优化。同时,这些研究对存储芯片测试研究领域具有一定的借鉴作用,可以对将来相同的案例有所帮助。
As is known to all, there is a very competitive market on sales of the memory IC chip. The majority of the FAB can have the capability on the manufacture of this kind of IC chip. From the current analysis trend of view, testing is one of the most valued key factors which will impact the price itself. Therefore, we need to take it into account on reducing the cost of the testing. Besides, we also need consider about how to improve the testing efficient as well as the testing reliability.
The author of this dissertation works in the company which can supply the 0.13μm process Super Flash EEPROM. Base on the routine job, the author has summarized the huge engineering data in the hand, including the testing data on the parameters of new circuit or process design. The author always assists the related persons of Process Integration Engineering and Design Service Engineering, provide the related testing support and analyze each parameter whether it is within specification or meet the requirement of the mass production.
Firstly, from the circuit design concern, the author lists the features of the several BIST design solutions, including the limitation of the pin counts, the functionality of the pins and also the advantage and disadvantage of the BIST circuit design itself. Base on the choice of the actual application, find out the best testing solution, the best testing methodology and the most reasonable testing parameters. Indeed, the author carried out a lot of analysis and study so as to make each one better understand the constraint between the testing methodology and the parameter so as to realize the whole procedure of the faults checking.
Secondly, from the process feature concern, the author demonstrates the testing methodology, especially on how to analyze the writing operation of the embedded memory. Base on the theory of testing and practice in fining rune some process parameters, continuously improve the stability of device and expand the work area of the parameters of the process, with purpose to improve the yield eventually.
Thirdly, from the production improvement concern, the author provide a series of testing methodology on how to reduce testing time, optimize testing program and enhance the testing coverage and yield.
Finally, although the majority of the issues has listed out in this dissertation and solved at engineering period, not only these simple issues, but also the extend application, theory or hypnosis, hopefully can be further validated and come out the universal meanings afterwards. Meanwhile, it must help each one on actually application that all current testing methodologies listed out in this dissertation.
本文作者所在公司主要生产0.13μm工艺嵌入式闪存(E-Flash),结合日常的嵌入式闪存芯片测试工作,和辅助工艺整合部门和器件设计部门人员对嵌入式闪存(E-Flash)进行的改良研究,得到了大量的工程测试数据。对新设计的电路和工艺进行参数和功能测试检查,使本款嵌入式闪存IP模块最终符合各项期望参数指标并满足量产的需求,并得出了许多新的测试方法。
首先,结合电路设计,列举了各种BIST(Built-in Self-test,内建自测试电路)设计的特点,芯片管脚数量的限制,主要的管脚功能以及各种电路设计给测试所带来的优缺点。根据实际所需,提供相应的最佳测试方案,同时也提到了一些常用的测试方法及测试参数,并对其进行了分析和研究,从而让大家理解到测试方法和参数之间所存在的相互制约的作用,得出了相关缺陷检查和弥补的方法。
其次,结合器件的工作特性,特别是对嵌入式闪存写操作工作特性进行了着重分析。从理论到实践,借用传统测试方法,尝试调整某些工艺参数,不断提高器件的工作稳定性和扩大参数的正常工作区域,最终达到有效提高成品率的目的。
再次,结合量产中的工程改进,针对优化测试程序所需要的缩短测试时间、优化测试流程及提高测试覆盖率问题,研究出一套完善的测试方法和验证手段。
最终,虽然本文中所列述的大部份的工程实际问题都已经基本解决,但本文作者对于这些问题的延伸和工程运用及拓展研究,还需要进一步去证实和优化。同时,这些研究对存储芯片测试研究领域具有一定的借鉴作用,可以对将来相同的案例有所帮助。
As is known to all, there is a very competitive market on sales of the memory IC chip. The majority of the FAB can have the capability on the manufacture of this kind of IC chip. From the current analysis trend of view, testing is one of the most valued key factors which will impact the price itself. Therefore, we need to take it into account on reducing the cost of the testing. Besides, we also need consider about how to improve the testing efficient as well as the testing reliability.
The author of this dissertation works in the company which can supply the 0.13μm process Super Flash EEPROM. Base on the routine job, the author has summarized the huge engineering data in the hand, including the testing data on the parameters of new circuit or process design. The author always assists the related persons of Process Integration Engineering and Design Service Engineering, provide the related testing support and analyze each parameter whether it is within specification or meet the requirement of the mass production.
Firstly, from the circuit design concern, the author lists the features of the several BIST design solutions, including the limitation of the pin counts, the functionality of the pins and also the advantage and disadvantage of the BIST circuit design itself. Base on the choice of the actual application, find out the best testing solution, the best testing methodology and the most reasonable testing parameters. Indeed, the author carried out a lot of analysis and study so as to make each one better understand the constraint between the testing methodology and the parameter so as to realize the whole procedure of the faults checking.
Secondly, from the process feature concern, the author demonstrates the testing methodology, especially on how to analyze the writing operation of the embedded memory. Base on the theory of testing and practice in fining rune some process parameters, continuously improve the stability of device and expand the work area of the parameters of the process, with purpose to improve the yield eventually.
Thirdly, from the production improvement concern, the author provide a series of testing methodology on how to reduce testing time, optimize testing program and enhance the testing coverage and yield.
Finally, although the majority of the issues has listed out in this dissertation and solved at engineering period, not only these simple issues, but also the extend application, theory or hypnosis, hopefully can be further validated and come out the universal meanings afterwards. Meanwhile, it must help each one on actually application that all current testing methodologies listed out in this dissertation.
引文
[1]薛霆,李红.嵌入式存储器发展现状[A].《中国集成电路》,2007年,第10期,82-87
[2]蔡玥.不断发展的闪存及与之对应的测试方案[A].《中国集成电路》,第9期,2004年,61-65
[3]ITRS. Semiconductor Industry Association (SIA) and International Technology Roadmap for Semiconductor [J],2001
[4]Thomas Trexler,许伟达.下一代测试系统化解闪存复杂性问题[A].《中国集成电路》,2004年,第11期,70-75
[5]马晓华.闪存在嵌入式Linux系统中的应用[A].《现代电子技术》,2010年,第12期,19-25
[6]电路设计部.GSMC_FLS003M0FDA_DS[J],宏力半导体制造有限公司：电路设计部,2009年
[7]邵晶波.SoC测试资源优化方法研究[E]哈尔滨工程大学：计算机应用技术,2008年
[8]易茂祥.系统芯片测试应用时间最小化技术研究[E].合肥工业大学：计算机应用技术,2010年
[9]The Fundamentals Of Digital Semiconductor Testing [J]. Soft Test Co., 2000
[10]杨卫.一种实用CMOS芯片开路和短路特性测试的新方法[A].《电工电气》,2009年,第9期,50-53
[11]高华.嵌入式存储器测试工艺流程分析设计[E].北京大学,电子与通信工程,2007年
[12]郭桂良,朱思奇,阎跃鹏.Flash Memory测试技术发展[A].《电子器件》,2008年,第4期,1131-1133
[13]许伟达.IC测试原理解析[E].科利登系统有限公司,2008和6月
[14]王宁波,崔艳CMOS集成电路潜在缺陷的最小电压检测[A].单片机与嵌入式系统,天津工业大学,2009年8月,42-43
[15]周少华.基于纳米晶粒浮栅结构的先进FLASH存储器的设计与模拟[E],湖南大学：电子通信工程,2007年
[16]电路设计部GSMC_FLS004M59DA_DS [J]宏力半导体制造有限公司：电路设计部,2010年5月
[17]工艺器件整合部.嵌入式闪存内部单元结构[J].宏力半导体制造有限公司,2009年5月
[18]冯国臣,郑新建,沈绪榜.一种减小存储单元间串扰的新型阵列布局结构[A].《半导体学报》,2005年,第1期,170-175
[19]郭红英.存储测试专用集成电路成测技术研究[E].中北大学测试计量技术及仪器,2007年
[20]Maly W. Computer-aided design for VLSI circuit manufacturability [H]. Proc. IEEE,1990,78(2):356-392
[21]周晓明.良率导向的IC设计方法研究[E].东南大学：软件工程(IC设计),2007年
[22]徐晓庆.内嵌式SRAM对逻辑产品良率提升的重要作用[E].复旦大学：电子与通信工程,2005年
[2]蔡玥.不断发展的闪存及与之对应的测试方案[A].《中国集成电路》,第9期,2004年,61-65
[3]ITRS. Semiconductor Industry Association (SIA) and International Technology Roadmap for Semiconductor [J],2001
[4]Thomas Trexler,许伟达.下一代测试系统化解闪存复杂性问题[A].《中国集成电路》,2004年,第11期,70-75
[5]马晓华.闪存在嵌入式Linux系统中的应用[A].《现代电子技术》,2010年,第12期,19-25
[6]电路设计部.GSMC_FLS003M0FDA_DS[J],宏力半导体制造有限公司：电路设计部,2009年
[7]邵晶波.SoC测试资源优化方法研究[E]哈尔滨工程大学：计算机应用技术,2008年
[8]易茂祥.系统芯片测试应用时间最小化技术研究[E].合肥工业大学：计算机应用技术,2010年
[9]The Fundamentals Of Digital Semiconductor Testing [J]. Soft Test Co., 2000
[10]杨卫.一种实用CMOS芯片开路和短路特性测试的新方法[A].《电工电气》,2009年,第9期,50-53
[11]高华.嵌入式存储器测试工艺流程分析设计[E].北京大学,电子与通信工程,2007年
[12]郭桂良,朱思奇,阎跃鹏.Flash Memory测试技术发展[A].《电子器件》,2008年,第4期,1131-1133
[13]许伟达.IC测试原理解析[E].科利登系统有限公司,2008和6月
[14]王宁波,崔艳CMOS集成电路潜在缺陷的最小电压检测[A].单片机与嵌入式系统,天津工业大学,2009年8月,42-43
[15]周少华.基于纳米晶粒浮栅结构的先进FLASH存储器的设计与模拟[E],湖南大学：电子通信工程,2007年
[16]电路设计部GSMC_FLS004M59DA_DS [J]宏力半导体制造有限公司：电路设计部,2010年5月
[17]工艺器件整合部.嵌入式闪存内部单元结构[J].宏力半导体制造有限公司,2009年5月
[18]冯国臣,郑新建,沈绪榜.一种减小存储单元间串扰的新型阵列布局结构[A].《半导体学报》,2005年,第1期,170-175
[19]郭红英.存储测试专用集成电路成测技术研究[E].中北大学测试计量技术及仪器,2007年
[20]Maly W. Computer-aided design for VLSI circuit manufacturability [H]. Proc. IEEE,1990,78(2):356-392
[21]周晓明.良率导向的IC设计方法研究[E].东南大学：软件工程(IC设计),2007年
[22]徐晓庆.内嵌式SRAM对逻辑产品良率提升的重要作用[E].复旦大学：电子与通信工程,2005年