基于核心路由器的缓存需求分析
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摘要
由于光纤传输和电子工艺发展速度的不均衡性,作为网络节点的核心路由器正在成为网络演进的瓶颈。路由器是一种存储转发设备,其内部的缓存容量是限制其性能的主要因素之一。
     本文以核心路由器的缓存需求为研究目标,结合国家863重大课题“可扩展到T比特的高性能IPv4/v6路由器基础平台及实验系统”,在总结和分析了现行的核心路由器缓存设置法则及各种改进方案的基础上,寻求一种适合于实际网络需求的核心路由器缓存设置指导方案。针对现行法则及各种改进方案在功耗、成本、时延、丢包率和利用串等方面的不足,从丢包率、链路速率等多种性能需求入手,研究了核心路由器的缓存需求问题,并结合当前骨干网络链路利用率较低的实际情况,给出了一种更贴近于实际网络的核心路由器缓存设置法则。仿真结果表明,在牺牲一定链路利用率的条件下,新的缓存设置法则在丢包率性能方面明显优于现有的缓存设置方案,能够更好的满足核心路由器的缓存需求;最后利用该法则指导了NDSC自主研发的T比特路由器的缓存设置,有效降低了项目成本。本文的主要工作如下;
     1.总结、分析和比较了当前核心路由器缓存设置法则及后续的一些改进方案,指出现行法则及各种改进方案在功耗、时延、丢包率、利用率和成本等方面的不足,给出了课题的研究方向,为课题的研究提供了参考依据和新的研究思路。
     2.从当前骨干网络链路利用率较低且骨干链路的TCP业务流规模巨大的实际情况出发,综合考虑丢包率、链路速率等多种性能需求,通过对不同TCP业务类型的分析,给出了一个更贴近实际网络的核心路由器缓存设置法则。
     3.利用网络仿真工具NS2,针对两种主要的TCP协议类型,对本文所提出的新的缓存设置法则进行了仿真验证,仿真结果为该法则提供了有力的佐证。
     4.结合国家863项目“可扩展到T比特的高性能IPv4/v6路由器基础平台及实验系统”,给出了应用于T比特路由器的缓存设置方案,指导了工程实现,有效地降低了T比特路由器的成本。
Due to the technology development disproportion of optical fiber transmission and electronics, the core router as network core node has become the main bottleneck in the progress of modern networks. As Storage and forwarding equipment, the Router's buffer size is one of the most important factors which influence router's performance.
     This paper aims to size buffers for core routers and is according to the requirements on one of key projects of the National High-Tech Research and Development Program of China (863 Program) named "The basic platform and experiment system for terabit scalable high performance IPv4/v6 routers". This dissertation tries to find out a new rule to sizing buffers for core routers, based on the analysis and comparison of router's buffer sizing rules in existence. Being dead against the deficiency such as consumption, cost, delay, loss rate, utilization, and considering the loss rate and utilization. This paper analyzes the buffer sizing for core routers. Considering the situation that the link utilization is very low in backbone networks, we propose a new rule of sizing buffers. The results of simulation show the new rule is better than the current ones. This new rule applied to Terabit Router successfully and reduced the cost of the project. The key contributions of this dissertation include:
     1. This dissertation briefly compares the different results and proposals of routers buffer sizing, and point out the deficiencies in consumption, cost, delay, loss rate and utilization. Giving direction, supplying references and new methods for the dissertation.
     2. In consideration of the low link utilization and the large volume of TCP flows in current backbone networks, we propose a more realistic rule for sizing the buffers of backbone routers, which take into account several performance metrics such as packet loss rate and link utilization simultaneity.
     3. This paper verifies the conclusions by using ns2 network simulator and giving strong proof to the conclusions.
     4. Based on the forementioned analysis and according to the requirements of 863 Terabit Router project and other factors, we present a scheme of buffer size, applying the scheme to Terabit Router successfully and reducing the cost of the project.
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