无线传感器网络节点芯片的低功耗设计与实现
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摘要
无线传感器网络节点一般工作于室外环境并且分布广,只适于采用电池供电,有效工作时间很短。当电池能量耗尽后节点会退出网络,直接影响通信的效能,当过多节点退出网络后更会影响整体功能的实现。所以如何解决节点能量约束、提高节点工作寿命已经成为了无线传感器网络研究中的核心问题。
     本文首先在比较分析了当前解决能量约束问题的两个主要措施——能量补充和节能措施之后,提出利用动态功耗管理策略设计低功耗节点芯片来解决节点能量约束问题。详细阐述了动态功耗管理策略利用芯片在多种节能模式模式间切换降低功耗的原理。
     然后采用门控时钟和门控电源方法从硬件上实现了动态功耗管理策略,并研究了采用这两种方法后给节点芯片设计带来的新问题及相应的解决办法,包括:使用扫描链结构解决数据的恢复问题;使用隔离单元解决数据隔离问题;使用双时钟结构缩短芯片休眠唤醒时间;利用扫描链解决电源连接仿真;利用休眠定时器解决MAC计数器的恢复问题;合理设计了功耗管理时序以保证芯片节能模式切换的顺利完成。在此基础上,设计了改进后的低功耗的节点芯片架构。
     最后,采用低功耗设计流程,使用HHNEC EF25G工艺完成了芯片的版图实现。使用Primepower对低功耗实现后的节点芯片进行功耗仿真,结果显示节能模式下的功耗仅不到正常工作模式下的1%,表明本文的低功耗策略有效的降低了节点芯片的功耗。
Wireless sensor network has been rated as one of the top ten technologies in the 21st century. Now it is has a wide range of applications in the military, environmental science, medicine, space exploration and so on. However, the limited energy of the network node limits its application. How to solve this problem has become the core issue of the research of wireless sensor networks now.
     In this paper, the work of the following several aspects has been carried out around the issue of limited energy of wireless sensor network. First, the basic situation of wireless sensor network has been introduced, including the characteristics of the network, topology of the network and application status quo. The dangers and the status quo of the problem of limited energy have been introduced in particular. Based on the analysis of the status quo of the limited energy of the network, the current studies to address this issue have been introduced, including the addition of energy and network energy-saving measures.
     After the discussion of the nodes system and the design method of main modules, low-power strategy in this article has been proposed: dynamic power management. The principles of dynamic power management has been analyzed, include its hardware implementation. Based on this, chip architecture of the node after the implement of low power has been put forward. Then the key technologies of low-power design has been carefully studied and analyzed, including: data recovery and isolation, the wake-up time shorten, power connector simulation, MAC timer recovery, and power-down power-up timing. For various techniques, the details of their problems and the details of their realizations have been introduced. Finally, the design flow of low power design has been introduced. The power simulation results of the netlist after the layout show that the dynamic power management strategy has a very significant reduce of power consumption. In sleep mode, power consumption is less than 1% of normal working mode power consumption. The chip has been layout by HHNEC EF250G process. The chip is being tested now.
引文
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