新型半导体材料的电输运特性研究
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摘要
本文主要是利用不同外场条件下的直流和交流测量技术,借助于不同的理论分析手段,针对最近比较热门的两种新型半导体材料:硅量子点材料和氮化铟材料,研究了三种不同的结构——硅量子点/单晶硅异质结二极管结构,InN薄膜结构,InN/GaAs界面的电子输运特性。
通常情况下,由于异质结电子导带不连续性,异质结界面上会存在电子沟道和二维电子气。我们的研究对象——硅量子点/单晶硅异质结界面上也同样存在二维(2D)电子气体,其面密度约为1011 cm-2。硅量子点本身是零维(0D)电子结构。很显然,硅量子点/单晶硅异质结是一个3D-2D-0D的电学体系。这些2D和0D低维结构的存在会导致该异质结在低温下表现出量子特性。低温下的伏安特性(I-V)曲线直接展现了量子共振隧穿峰的存在。值得注意的是,虽然有很多成熟的理论[例如Matveev–Larkin(ML)理论]曾成功的解释了大量低维体系中的共振隧穿现象,但是他们主要研究给定态间的共振隧穿,不能清楚的解释我们这样一个3D-2D-0D体系中共振隧穿峰的根源和隧穿机制。因此我们需要根据量子输运理论,建立适用于硅量子点/单晶硅异质结的共振隧穿二极管(RTD)模型来解释该异质结伏安特性曲线上观察到的共振隧穿现象。
我们在基于自洽势计算和转移矩阵方法的量子输运理论框架下,综合考虑了电荷贡献,界面电子的积累,电子-电子相互作用等因素,建立了共振隧穿二极管模型,并对磷烷掺杂比为0.1 %,p型单晶硅掺杂浓度为1.0×1016 cm-3的硅量子点(n)/单晶硅(p)异质结伏安特性曲线上观察到的共振隧穿峰进行了理论模拟计算。理论模拟时所需要的能带参数皆来自文献报道和该样品实验测定结果。X射线衍射(XRD)和拉曼实验测量给出了硅量子点薄膜内量子点的晶粒尺寸和晶态比,而电容-电压(C-V)实验则给出了异质结能带中的重要能带参数——能带偏移,量子阱势垒宽度和高度皆来自于文献的报道。理论计算不仅成功模拟了实验中的共振隧穿特性,揭示出该异质结I-V中的共振隧穿峰源于电子从三维(3D)-二维(2D)的共振隧穿,还表明异质结两侧掺杂浓度的改变对共振隧穿特性影响很大,即由掺杂浓度造成的二维及零维态能级位置不同会改变异质结共振隧穿特性。
借助于顺序隧穿理论,理论计算结果进一步阐述了二维和零维态能级相对位置变化对隧穿电流的具体调控过程。量子输运理论计算表明适当改变异质结两侧掺杂浓度可以调控二维(2D)-零维(0D)隧穿峰的位置以及隧穿峰产生(消失)。我们能够在磷烷掺杂比为0.8 %,p型单晶硅掺杂浓度为7.6×1014 cm-3硅量子点(n)/单晶硅(p)异质结伏安特性曲线上可观察到双峰共振隧穿结构(3D-2D和2D-0D)。掺杂浓度的这种调控可以给RTD器件提供必要设计参数。此外,我们还在硅量子点(n)/单晶硅(p)异质结二极管伏安特性曲线上观察到了周期性的负微分电导峰,并指出这种周期性的负微分电导峰源于中性区纳米点层中电子的不断耗尽与积累,即缘自于量子点内零维-零维(0D-0D)的共振隧穿现象,从而进一步完整的阐述硅量子点(n)/单晶硅(p)异质结内所有与低维态相关的共振隧穿机制。
其次,我们还详细研究了不同生长条件下射频磁控溅射法在砷化稼(GaAs)衬底上得到的氮化铟(InN)薄膜的载流子输运特性。变温I-V实验表明InN薄膜的电导随温度降低而增大,并在低温时趋于常值。低温下由于中性杂质散射占主导低位,电导值基本不随温度改变。我们发现室温-低温段电导随温度的反常变化行为可以通过晶界势垒模型来解释。由于InN薄膜内含有较多的位错,因此在晶界内形成的缺陷态能够俘获一定数量的自由载流子,并在晶界处形成具有一定高度的晶界势垒,从而部分阻碍了自由载流子在薄膜内部的运动。由于缺陷浓度较高,InN薄膜内部晶界势垒高度较低,这种较低的晶界势垒高度将会造成InN薄膜电导随温度降低而逐渐增大这样反常的电导-温度行为。
晶界势垒模型不仅可以用来模拟电导随温度的变化关系,指出InN薄膜内这一反常变化行为的根源,还可以用来模拟势垒高度随偏压的变化关系,指出一定偏压下InN薄膜内部的动力学输运机制及势垒高度随偏压变化的趋势和根源。实验结果和理论的自洽计算结果都表明随着偏压的增大,势垒高度将逐渐减小,直至大的偏压下势垒高度的消失。这是因为在弹性碰撞输运的情况下,电子所有的势能都转变为动能,当动能超过阈值能量(由材料的带隙及电子和空穴的有效质量决定)时,n型InN薄膜中的电子能够撞击离子化价带中的空穴,从而产生电子空穴对。作为少数载流子的空穴在电场力的作用下运动到界面处,部分空穴在扩散过程中被俘获在界面处,微晶界面处空穴的积累补偿了部分屏蔽的负电荷,使得界面处的净电荷密度下降,最终导致了势垒高度的降低,直至在大的偏压下晶界势垒消失。晶界势垒高度随电压的变化关系向我们进一步表明InN薄膜内部载流子输运特性是由于空穴在晶界处的积累决定的。由于晶界势垒是由晶界处缺陷俘获一定数量的载流子后形成的,因此我们根据晶界势垒高度获得了InN薄膜内部的缺陷体浓度值,且发现理论计算值可以得到显微喇曼实验结果的验证。所有这些进一步证实了在室温-低温范围内,磁控溅射生长的多晶InN薄膜内晶界势垒散射占据了主导地位。
本文最后还讨论了由InN/GaAs界面上存在的界面陷阱及界面电荷导致的负电容效应。常温下测得的用射频磁控溅射法在半绝缘GaAs衬底上得到的InN样品其同侧电容-频率关系曲线皆是负值。同侧电极的制作则表明这种负电容特性可能源于InN薄膜本身的贡献、InN/GaAs界面的贡献或二者贡献之和。通过与宝石衬底上InN样品的电容-频率特性比较,我们认为至少有部分的负电容源于InN/GaAs界面,因为二块样品中InN薄膜的电学特性基本相同,且宝石衬底上InN样品负电容值明显小于GaAs衬底上InN样品。均匀半导体模型则向我们表明InN薄膜本身电容较小与测量值相比可以忽略,GaAs衬底InN薄膜中观测到的负电容特性源于InN与GaAs界面的贡献。由于InN与GaAs晶格失配较大,界面上存在大量的界面陷阱,交流小信号存在时,界面陷阱能俘获一定量的电荷,产生偶极子层来调制界面势垒高度,因此势垒高度的变化主要依赖于InN/GaAs界面的载流子俘获与激发。这样的一个过程需要一定的时间,导致势垒高度的变化迟滞于交流电压,最终导致了负电容的出现。
在本文中,我们还通过基于充放电和迟滞电导的暂态电流模型模拟并进一步研究了InN/GaAs界面特性。此模型不仅能成功的模拟InN/GaAs界面的电容-频率特性,还可给出一些与界面陷阱性质密切相关的参数(例如InN/GaAs界面陷阱时间常数约为0.5ms左右)。这些界面参数与生长条件的关系表明界面特性与生长条件、薄膜质量密切相关,薄膜质量较好的样品其界面陷阱和界面电荷较少。
以上的研究得到了国家自然科学基金(10125416和10674094),上海市基础研究重大项目(03DJ14003和05DJ14003)、重点项目(06JC14039)和教育部“长江学者和创新团队发展计划”创新团队计划(IRT0524)的资助。
In this paper, we report the investigation on the novel semiconductor materials of silicon quantum dots and Indium nitride. We mainly demonstrate the study on the electron transport properities of three kinds of different structures: Silicon quantum dots (nc-Si:H)/crystalline Silicon (c-Si) heterojunction diode, Indium nitride (InN) thin film and Indium nitride/Gallium arsenide (GaAs) interface according to the theoretical analysis with the aid of direct current (dc) and alternating current (ac) measurement.
Generally, there exist electron channel and two dimensional (2D) electron gas (EG) at the heterojunction interface due to the conduction-band discontinuity. Similarly, there is 2DEG existed at nc-Si:H/ c-Si interface, which has a sheet density of about 1011 cm-2. Furthermore, Silicon quantum dot itself is a zero-dimensional (0D) structure. Hence obviously nc-Si:H/c-Si heterojunction is electrically a three dimensional (3D)-2D-0D system. The existence of the low-dimensional structure would result in the appearance of quantum effect at low temperatures. Current-voltage (I-V) curves at low temperatures directly exhibit the existence of resonant tunneling peak. It should be noted here that though many mature theories, such as Matveev-Larkin (ML) theory, have succeeded in explainng a lot of resonant tunneling phenomena in low dimensional systems, they focus on the demonstration of resonant tunneling between two given states and could not clearly explain the resonant tunneling process in our 3D-2D-0D system. We need to establish a resonant tunneling diode (RTD) model based on the quantum transport theory to explain the resonant tunneling phenomena observed in I-V curves of nc-Si:H/c-Si heterojunction.
Within the framework of quantum transport theory, a RTD model based on the self-consistent potential calculation and transfer matrix procedure, has been constructed, in which a great number of factors, such as charge contribution, electron accumulation at the interface, and electron-electron interactions have been taken into account. The model has been used to simulate the resonant tunneling peak in a nc-Si:H(n)/c-Si(p) heterojunction with a doping ratio in nc-Si:H of 0.1 % and an acceptor concentration in c-Si of 1.0×1016 cm-3. The energy band parameters required in the simulation all come from either the literature or the experiments. The grain size and crystallinity of the silicon quantum dot are obtained from X ray diffraction and Raman shift experiments, and the conduction band discontinuity of the heterojunction is gained from the capacitance-voltage (C-V) measurement, while the barrier height and width are achieved from the literature. The theoretical calculation not only succeed in simulating the experimental results and illustrating the origin (3D-2D tunneling) of the tunneling peak, but also indicates the doped concentration of the heterojunction can control the resonant tunneling characteristics.
By the aid of sequence tunneling theory, we have further showed the detailed control of the tunneling current by the position of 2D and/or 0D states. The calculated results show that by properly changing the doped concentration of the heterojunction, the position of 2D-0D tunneling peak would vary and evenmore appear/disappear. The double-peak resonant tunneling (3D-2D and 2D-0D) structure has been observed in the I-V curve of a nc-Si:H(n)/c-Si(p) heterojunction which has a doping ratio of 0.8 % and an acceptor concentration of 7.6×1014 cm-3. This above control of the resonant tunneling current by the doped concentration can provide the essential designing parameters for the RTD devices. We have also observed the periodic negative differential conductance peaks in the above nc-Si:H(n)/c-Si(p) heterojunction. The theoretical analysis indicates the phenomena originate from the accumulation and depletion of electrons tunneling through the nanodot layers in the neutral region, that is, the 0D-0D resonant tunneling occurring in the silicon quantum dots. Therefore, all the tunneling regimes related to the low dimensional states in the nc-Si:H/c-Si heterojunction have been explored.
Furthermore, we have investigated the carrier transport characteristics of InN thin film grown on GaAs substrate by reactive frequency magnetron sputtering with different growth conditions. The experimental temperature-dependent conductance illustrates the conductance of the InN thin films increases with the decreasing temperature and tends to be a steady value at low temperatures. At low temperature the neutral impurity scattering plays the dominant role, which leads to the steady varying tendency of the conductance. We also found the grain boundary barrier model could explain the observed abnormal conductance behavior with the temperature from room temperature (RT) to low temperature (LT). The traps in the InN thin films can capture the free carrier and form the grain boundary barrier, which partly blocks the motion of the free carrier in the InN thin films. The grain boundary barrier height in the InN thin film is low due to the high trap concentration, eventually resulting in the abnormal conductance behaviour that conductance increases with the decreasing temperature.
Not only can we use the grain boundary model to simulate and explain temperature-conductance characteristics, but also the variation of the barrier height with the bias. Both the experimental and self-consistent calculating results indicate that the barrier height decreases with the increasing bias, and finally disappears at larger bias. For the case of a pure ballistic transport, all the potential energy of the electrons is converted into kinetic energy. When kinetic energy is larger than threshold energy, electrons in the n-type InN films can impact-ionize a valence state and thereby create a hole. Holes created as minority carriers probably have to go back to the interface due to the force of the electric field. Part of the holes are trapped in the grain boundary during the diffusion; the accumulation of holes at the grain boundaries compensates parts of the negative screening charge, makes the charge in the grain boundary decrease, and consequently lowers the barrier height until the barrier disappears in the large applied bias. The relationship between the bias and barrier height illustrates the carrier transport properties in InN thin film is govern by the holes trapping at the grain boundary. We have also obtained the trap concentration according to the grain boundary barrier height, for the barrier forms after the traps at the grain boundary capture an amount of free carriers. The calculated trap concentration can be proved by the Micro-Raman experiments. All above facts confirm that the grain boundary barrier scattering play a dominant role in the InN thin film grown on GaAs substrate by rf magnetron sputtering in the range of temperature from RT to LT.
In addition, we have still discussed the negative capacitance induced by the traps and charges at the InN/GaAs interface. A negative capacitance effect has been observed throughout the measured frequency in the InN thin film on GaAs substrate grown by rf magnetron sputtering. The coplanar electric contacts show that the negative capacitance probably derives from the contribution of InN thin film, or InN/GaAs interface, or sum of them. The direct comparison experiments between the InN thin films on GaAs and sapphire substrates clearly confirm that the NC effects of InN thin films on GaAs substrates partly comes from the interfaces between InN thin films and GaAs substrates. The barrier free model declares that the capacitance of the InN thin film is negligible in magnitude, as compared to the experimental data, and the negative capacitance effect originates from the contribution of InN/GaAs interface. There are a lot of traps existed at the InN/GaAs interface due to the larger lattice mismatch. In the presence of an ac perturbation with a small voltage, the interface traps can retain a sufficient quantity of charge so that they build a dipole layer, which modulates the barrier height. The variation of barrier height arises mainly from carrier capture and emission at interface states. This process requires a certain period of time, which makes the variation of barrier height lag behind small voltage and therefore results in the NC effect.
Based on a transient current model of charging-discharging and inertial conducting for the InN/GaAs interface states, we have further investigated the InN/GaAs interface characteristics. This model can not only successfully simulate the experimental capacitance-frequency characteristics of the InN/GaAs interface, but also give some parameters related with the interface properties. The relationship between these interface-parameters and the growth conditions indicates that the interface characteristics are closely related with the growth condition and quality of the thin film. In another word, it shows the samples which have better quality of thin film have less interface traps and charges.
This work is supported by the Natural Science Foundation of China under contract Nos. 10125416, and 10674094, Shanghai municipal projects of 03DJ14003, 05DJ14003, and 06JC14039, as well as the National Minister of Education Program for Changjiang Scholars and Innovative Research Team in University (PCSIRT) of IRT0524.
通常情况下,由于异质结电子导带不连续性,异质结界面上会存在电子沟道和二维电子气。我们的研究对象——硅量子点/单晶硅异质结界面上也同样存在二维(2D)电子气体,其面密度约为1011 cm-2。硅量子点本身是零维(0D)电子结构。很显然,硅量子点/单晶硅异质结是一个3D-2D-0D的电学体系。这些2D和0D低维结构的存在会导致该异质结在低温下表现出量子特性。低温下的伏安特性(I-V)曲线直接展现了量子共振隧穿峰的存在。值得注意的是,虽然有很多成熟的理论[例如Matveev–Larkin(ML)理论]曾成功的解释了大量低维体系中的共振隧穿现象,但是他们主要研究给定态间的共振隧穿,不能清楚的解释我们这样一个3D-2D-0D体系中共振隧穿峰的根源和隧穿机制。因此我们需要根据量子输运理论,建立适用于硅量子点/单晶硅异质结的共振隧穿二极管(RTD)模型来解释该异质结伏安特性曲线上观察到的共振隧穿现象。
我们在基于自洽势计算和转移矩阵方法的量子输运理论框架下,综合考虑了电荷贡献,界面电子的积累,电子-电子相互作用等因素,建立了共振隧穿二极管模型,并对磷烷掺杂比为0.1 %,p型单晶硅掺杂浓度为1.0×1016 cm-3的硅量子点(n)/单晶硅(p)异质结伏安特性曲线上观察到的共振隧穿峰进行了理论模拟计算。理论模拟时所需要的能带参数皆来自文献报道和该样品实验测定结果。X射线衍射(XRD)和拉曼实验测量给出了硅量子点薄膜内量子点的晶粒尺寸和晶态比,而电容-电压(C-V)实验则给出了异质结能带中的重要能带参数——能带偏移,量子阱势垒宽度和高度皆来自于文献的报道。理论计算不仅成功模拟了实验中的共振隧穿特性,揭示出该异质结I-V中的共振隧穿峰源于电子从三维(3D)-二维(2D)的共振隧穿,还表明异质结两侧掺杂浓度的改变对共振隧穿特性影响很大,即由掺杂浓度造成的二维及零维态能级位置不同会改变异质结共振隧穿特性。
借助于顺序隧穿理论,理论计算结果进一步阐述了二维和零维态能级相对位置变化对隧穿电流的具体调控过程。量子输运理论计算表明适当改变异质结两侧掺杂浓度可以调控二维(2D)-零维(0D)隧穿峰的位置以及隧穿峰产生(消失)。我们能够在磷烷掺杂比为0.8 %,p型单晶硅掺杂浓度为7.6×1014 cm-3硅量子点(n)/单晶硅(p)异质结伏安特性曲线上可观察到双峰共振隧穿结构(3D-2D和2D-0D)。掺杂浓度的这种调控可以给RTD器件提供必要设计参数。此外,我们还在硅量子点(n)/单晶硅(p)异质结二极管伏安特性曲线上观察到了周期性的负微分电导峰,并指出这种周期性的负微分电导峰源于中性区纳米点层中电子的不断耗尽与积累,即缘自于量子点内零维-零维(0D-0D)的共振隧穿现象,从而进一步完整的阐述硅量子点(n)/单晶硅(p)异质结内所有与低维态相关的共振隧穿机制。
其次,我们还详细研究了不同生长条件下射频磁控溅射法在砷化稼(GaAs)衬底上得到的氮化铟(InN)薄膜的载流子输运特性。变温I-V实验表明InN薄膜的电导随温度降低而增大,并在低温时趋于常值。低温下由于中性杂质散射占主导低位,电导值基本不随温度改变。我们发现室温-低温段电导随温度的反常变化行为可以通过晶界势垒模型来解释。由于InN薄膜内含有较多的位错,因此在晶界内形成的缺陷态能够俘获一定数量的自由载流子,并在晶界处形成具有一定高度的晶界势垒,从而部分阻碍了自由载流子在薄膜内部的运动。由于缺陷浓度较高,InN薄膜内部晶界势垒高度较低,这种较低的晶界势垒高度将会造成InN薄膜电导随温度降低而逐渐增大这样反常的电导-温度行为。
晶界势垒模型不仅可以用来模拟电导随温度的变化关系,指出InN薄膜内这一反常变化行为的根源,还可以用来模拟势垒高度随偏压的变化关系,指出一定偏压下InN薄膜内部的动力学输运机制及势垒高度随偏压变化的趋势和根源。实验结果和理论的自洽计算结果都表明随着偏压的增大,势垒高度将逐渐减小,直至大的偏压下势垒高度的消失。这是因为在弹性碰撞输运的情况下,电子所有的势能都转变为动能,当动能超过阈值能量(由材料的带隙及电子和空穴的有效质量决定)时,n型InN薄膜中的电子能够撞击离子化价带中的空穴,从而产生电子空穴对。作为少数载流子的空穴在电场力的作用下运动到界面处,部分空穴在扩散过程中被俘获在界面处,微晶界面处空穴的积累补偿了部分屏蔽的负电荷,使得界面处的净电荷密度下降,最终导致了势垒高度的降低,直至在大的偏压下晶界势垒消失。晶界势垒高度随电压的变化关系向我们进一步表明InN薄膜内部载流子输运特性是由于空穴在晶界处的积累决定的。由于晶界势垒是由晶界处缺陷俘获一定数量的载流子后形成的,因此我们根据晶界势垒高度获得了InN薄膜内部的缺陷体浓度值,且发现理论计算值可以得到显微喇曼实验结果的验证。所有这些进一步证实了在室温-低温范围内,磁控溅射生长的多晶InN薄膜内晶界势垒散射占据了主导地位。
本文最后还讨论了由InN/GaAs界面上存在的界面陷阱及界面电荷导致的负电容效应。常温下测得的用射频磁控溅射法在半绝缘GaAs衬底上得到的InN样品其同侧电容-频率关系曲线皆是负值。同侧电极的制作则表明这种负电容特性可能源于InN薄膜本身的贡献、InN/GaAs界面的贡献或二者贡献之和。通过与宝石衬底上InN样品的电容-频率特性比较,我们认为至少有部分的负电容源于InN/GaAs界面,因为二块样品中InN薄膜的电学特性基本相同,且宝石衬底上InN样品负电容值明显小于GaAs衬底上InN样品。均匀半导体模型则向我们表明InN薄膜本身电容较小与测量值相比可以忽略,GaAs衬底InN薄膜中观测到的负电容特性源于InN与GaAs界面的贡献。由于InN与GaAs晶格失配较大,界面上存在大量的界面陷阱,交流小信号存在时,界面陷阱能俘获一定量的电荷,产生偶极子层来调制界面势垒高度,因此势垒高度的变化主要依赖于InN/GaAs界面的载流子俘获与激发。这样的一个过程需要一定的时间,导致势垒高度的变化迟滞于交流电压,最终导致了负电容的出现。
在本文中,我们还通过基于充放电和迟滞电导的暂态电流模型模拟并进一步研究了InN/GaAs界面特性。此模型不仅能成功的模拟InN/GaAs界面的电容-频率特性,还可给出一些与界面陷阱性质密切相关的参数(例如InN/GaAs界面陷阱时间常数约为0.5ms左右)。这些界面参数与生长条件的关系表明界面特性与生长条件、薄膜质量密切相关,薄膜质量较好的样品其界面陷阱和界面电荷较少。
以上的研究得到了国家自然科学基金(10125416和10674094),上海市基础研究重大项目(03DJ14003和05DJ14003)、重点项目(06JC14039)和教育部“长江学者和创新团队发展计划”创新团队计划(IRT0524)的资助。
In this paper, we report the investigation on the novel semiconductor materials of silicon quantum dots and Indium nitride. We mainly demonstrate the study on the electron transport properities of three kinds of different structures: Silicon quantum dots (nc-Si:H)/crystalline Silicon (c-Si) heterojunction diode, Indium nitride (InN) thin film and Indium nitride/Gallium arsenide (GaAs) interface according to the theoretical analysis with the aid of direct current (dc) and alternating current (ac) measurement.
Generally, there exist electron channel and two dimensional (2D) electron gas (EG) at the heterojunction interface due to the conduction-band discontinuity. Similarly, there is 2DEG existed at nc-Si:H/ c-Si interface, which has a sheet density of about 1011 cm-2. Furthermore, Silicon quantum dot itself is a zero-dimensional (0D) structure. Hence obviously nc-Si:H/c-Si heterojunction is electrically a three dimensional (3D)-2D-0D system. The existence of the low-dimensional structure would result in the appearance of quantum effect at low temperatures. Current-voltage (I-V) curves at low temperatures directly exhibit the existence of resonant tunneling peak. It should be noted here that though many mature theories, such as Matveev-Larkin (ML) theory, have succeeded in explainng a lot of resonant tunneling phenomena in low dimensional systems, they focus on the demonstration of resonant tunneling between two given states and could not clearly explain the resonant tunneling process in our 3D-2D-0D system. We need to establish a resonant tunneling diode (RTD) model based on the quantum transport theory to explain the resonant tunneling phenomena observed in I-V curves of nc-Si:H/c-Si heterojunction.
Within the framework of quantum transport theory, a RTD model based on the self-consistent potential calculation and transfer matrix procedure, has been constructed, in which a great number of factors, such as charge contribution, electron accumulation at the interface, and electron-electron interactions have been taken into account. The model has been used to simulate the resonant tunneling peak in a nc-Si:H(n)/c-Si(p) heterojunction with a doping ratio in nc-Si:H of 0.1 % and an acceptor concentration in c-Si of 1.0×1016 cm-3. The energy band parameters required in the simulation all come from either the literature or the experiments. The grain size and crystallinity of the silicon quantum dot are obtained from X ray diffraction and Raman shift experiments, and the conduction band discontinuity of the heterojunction is gained from the capacitance-voltage (C-V) measurement, while the barrier height and width are achieved from the literature. The theoretical calculation not only succeed in simulating the experimental results and illustrating the origin (3D-2D tunneling) of the tunneling peak, but also indicates the doped concentration of the heterojunction can control the resonant tunneling characteristics.
By the aid of sequence tunneling theory, we have further showed the detailed control of the tunneling current by the position of 2D and/or 0D states. The calculated results show that by properly changing the doped concentration of the heterojunction, the position of 2D-0D tunneling peak would vary and evenmore appear/disappear. The double-peak resonant tunneling (3D-2D and 2D-0D) structure has been observed in the I-V curve of a nc-Si:H(n)/c-Si(p) heterojunction which has a doping ratio of 0.8 % and an acceptor concentration of 7.6×1014 cm-3. This above control of the resonant tunneling current by the doped concentration can provide the essential designing parameters for the RTD devices. We have also observed the periodic negative differential conductance peaks in the above nc-Si:H(n)/c-Si(p) heterojunction. The theoretical analysis indicates the phenomena originate from the accumulation and depletion of electrons tunneling through the nanodot layers in the neutral region, that is, the 0D-0D resonant tunneling occurring in the silicon quantum dots. Therefore, all the tunneling regimes related to the low dimensional states in the nc-Si:H/c-Si heterojunction have been explored.
Furthermore, we have investigated the carrier transport characteristics of InN thin film grown on GaAs substrate by reactive frequency magnetron sputtering with different growth conditions. The experimental temperature-dependent conductance illustrates the conductance of the InN thin films increases with the decreasing temperature and tends to be a steady value at low temperatures. At low temperature the neutral impurity scattering plays the dominant role, which leads to the steady varying tendency of the conductance. We also found the grain boundary barrier model could explain the observed abnormal conductance behavior with the temperature from room temperature (RT) to low temperature (LT). The traps in the InN thin films can capture the free carrier and form the grain boundary barrier, which partly blocks the motion of the free carrier in the InN thin films. The grain boundary barrier height in the InN thin film is low due to the high trap concentration, eventually resulting in the abnormal conductance behaviour that conductance increases with the decreasing temperature.
Not only can we use the grain boundary model to simulate and explain temperature-conductance characteristics, but also the variation of the barrier height with the bias. Both the experimental and self-consistent calculating results indicate that the barrier height decreases with the increasing bias, and finally disappears at larger bias. For the case of a pure ballistic transport, all the potential energy of the electrons is converted into kinetic energy. When kinetic energy is larger than threshold energy, electrons in the n-type InN films can impact-ionize a valence state and thereby create a hole. Holes created as minority carriers probably have to go back to the interface due to the force of the electric field. Part of the holes are trapped in the grain boundary during the diffusion; the accumulation of holes at the grain boundaries compensates parts of the negative screening charge, makes the charge in the grain boundary decrease, and consequently lowers the barrier height until the barrier disappears in the large applied bias. The relationship between the bias and barrier height illustrates the carrier transport properties in InN thin film is govern by the holes trapping at the grain boundary. We have also obtained the trap concentration according to the grain boundary barrier height, for the barrier forms after the traps at the grain boundary capture an amount of free carriers. The calculated trap concentration can be proved by the Micro-Raman experiments. All above facts confirm that the grain boundary barrier scattering play a dominant role in the InN thin film grown on GaAs substrate by rf magnetron sputtering in the range of temperature from RT to LT.
In addition, we have still discussed the negative capacitance induced by the traps and charges at the InN/GaAs interface. A negative capacitance effect has been observed throughout the measured frequency in the InN thin film on GaAs substrate grown by rf magnetron sputtering. The coplanar electric contacts show that the negative capacitance probably derives from the contribution of InN thin film, or InN/GaAs interface, or sum of them. The direct comparison experiments between the InN thin films on GaAs and sapphire substrates clearly confirm that the NC effects of InN thin films on GaAs substrates partly comes from the interfaces between InN thin films and GaAs substrates. The barrier free model declares that the capacitance of the InN thin film is negligible in magnitude, as compared to the experimental data, and the negative capacitance effect originates from the contribution of InN/GaAs interface. There are a lot of traps existed at the InN/GaAs interface due to the larger lattice mismatch. In the presence of an ac perturbation with a small voltage, the interface traps can retain a sufficient quantity of charge so that they build a dipole layer, which modulates the barrier height. The variation of barrier height arises mainly from carrier capture and emission at interface states. This process requires a certain period of time, which makes the variation of barrier height lag behind small voltage and therefore results in the NC effect.
Based on a transient current model of charging-discharging and inertial conducting for the InN/GaAs interface states, we have further investigated the InN/GaAs interface characteristics. This model can not only successfully simulate the experimental capacitance-frequency characteristics of the InN/GaAs interface, but also give some parameters related with the interface properties. The relationship between these interface-parameters and the growth conditions indicates that the interface characteristics are closely related with the growth condition and quality of the thin film. In another word, it shows the samples which have better quality of thin film have less interface traps and charges.
This work is supported by the Natural Science Foundation of China under contract Nos. 10125416, and 10674094, Shanghai municipal projects of 03DJ14003, 05DJ14003, and 06JC14039, as well as the National Minister of Education Program for Changjiang Scholars and Innovative Research Team in University (PCSIRT) of IRT0524.
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