Viterbi译码器的低功耗设计
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摘要
卷积码是一类重要的前向纠错编码,它编码简单,易于实现最佳译码,是当今无线数字通信系统的一个十分重要的组成部分。Viterbi译码算法是一种用来解卷积编码的最大似然译码算法,它具有译码效率高、速度快及译码器实现结构简单的优点,被认为是卷积码的最佳译码算法。
随着VLSI的飞速发展和便携通信设备的大量涌现,功耗越来越成为制约设计的一个主要问题。Viterbi译码器是移动通信系统中的主要耗能单元,因此如何降低Viterbi译码的复杂性和功耗,就成为一种迫切的需要,受到人们的普遍关注。本课题就是设计适用于移动通信系统的低功耗Viterbi译码器。
电路的功耗分为静态功耗和动态功耗,对于CMOS电路,功耗主要是动态功耗,大约占总功耗的85—90%。动态功耗由负载电容、工作频率、工作电压和能耗状态活动转换几率决定。在通常的设计环境中,设计者不能改变负载电容、工作频率或工作电压,而只能改变开关活动频率。降低开关活动频率的实质就是尽量去除不必要的翻转、避免能量的白白浪费。从这里发掘功耗的潜力是很大的,主要通过优化算法、优化逻辑结构来实现。这是当前开展低功耗逻辑优化的重要方面,也是本课题采用的方法。
Viterbi译码器主要由四个功能单元组成:分支度量单元(BMU),加比选单元(ACS),路径度量存储单元(PMU),幸存路径存储和输出单元(SMU)。本文所做的Viterbi译码器设计采用模块化的设计方法,先对各个功能单元进行优化设计,然后将各个功能单元组合在一起,形成最终的译码器。
本文对SMU单元进行了低功耗设计。在SMU中,由于要进行频繁的存储器读写,功耗很大,成为整个viterbi译码器中消耗功率最大的单元,因此对SMU单元进行低功耗设计对降低Viterbi译码器的功耗起着非常重要的作用。本文首先分析了两种传统的SMU实现方法,这两种方法都存在一定的缺陷。其次通过分析幸存路径存储和输出的过程,讨论了改进寄存器交换法,减少存储器使用数目和减少存储单元数据读写次数的可能性,并提出了具体的实现方法。然后对比传统的寄存器交换法,进行了存储单元使用数量和功耗的对比,仿真结果表明能明显的降低功耗。
最后把各个功能模块组合成在一起,设计出了低功耗的Viterbi译码器,仿真结果表明比起没有采用低功耗技术的译码器,在译码器纠错性能和译码速度不变的情况下,动态功耗降低了33%。
Convolutinal coding is a coding scheme often employed in digital wireless communications.Viterbi decoders are used to decode convolutional codes.
Viterbi decoders employed in digital wireless communications are complex and dissipate large power. With the proliferation of battery powered devices such as cellular phones and laptop computers, power dissipation, along with speed and area, is a major concern in VLSI design. In this thesis, we investigated a low-power design of Viterbi decoders for wireless communications applications.
In CMOS technology the major source of power dissipation is attributed to dynamic power dissipation, which is due to the switching of signal values. The focus of our research in the low-power design of Viterbi decoders is reduction of dynamic power dissipation at logic level in the standard cell design environment.
The VD is composed of four functional units:
1) The branch metrics unit (BMU);
2) The add-compare-select unit (ACS);
3) The path metrics unit ( PMU);
4) The survivor memory unit (SMU);
Regarding the power dissipation of the Viterbi decoder, the SMU is the hottest spot in the Viterbi decoder due to the frequent memory accesses.There are two traditional techniques for the realization of survivor memory unit in viterbi decoder--register exchange (RE) and trace back (TB) method. RE has a very complicated interconnections and needs a high power consumption .TB needs a large quantity of buffers and has long decoding delay. In this paper a modified register-exchange (RE) method is presented, which reduce its memory access rate and its amount of memory, thus, reduces the power consumption. Based on the modified register-exchange (RE) method SMU, a Low power viterbi decoder can be designed. Our experimental result shows the proposed design reduces the dynamic power dissipation of a Viterbi decoder by about 33 percent compared with the one without considering the low-power design.
随着VLSI的飞速发展和便携通信设备的大量涌现,功耗越来越成为制约设计的一个主要问题。Viterbi译码器是移动通信系统中的主要耗能单元,因此如何降低Viterbi译码的复杂性和功耗,就成为一种迫切的需要,受到人们的普遍关注。本课题就是设计适用于移动通信系统的低功耗Viterbi译码器。
电路的功耗分为静态功耗和动态功耗,对于CMOS电路,功耗主要是动态功耗,大约占总功耗的85—90%。动态功耗由负载电容、工作频率、工作电压和能耗状态活动转换几率决定。在通常的设计环境中,设计者不能改变负载电容、工作频率或工作电压,而只能改变开关活动频率。降低开关活动频率的实质就是尽量去除不必要的翻转、避免能量的白白浪费。从这里发掘功耗的潜力是很大的,主要通过优化算法、优化逻辑结构来实现。这是当前开展低功耗逻辑优化的重要方面,也是本课题采用的方法。
Viterbi译码器主要由四个功能单元组成:分支度量单元(BMU),加比选单元(ACS),路径度量存储单元(PMU),幸存路径存储和输出单元(SMU)。本文所做的Viterbi译码器设计采用模块化的设计方法,先对各个功能单元进行优化设计,然后将各个功能单元组合在一起,形成最终的译码器。
本文对SMU单元进行了低功耗设计。在SMU中,由于要进行频繁的存储器读写,功耗很大,成为整个viterbi译码器中消耗功率最大的单元,因此对SMU单元进行低功耗设计对降低Viterbi译码器的功耗起着非常重要的作用。本文首先分析了两种传统的SMU实现方法,这两种方法都存在一定的缺陷。其次通过分析幸存路径存储和输出的过程,讨论了改进寄存器交换法,减少存储器使用数目和减少存储单元数据读写次数的可能性,并提出了具体的实现方法。然后对比传统的寄存器交换法,进行了存储单元使用数量和功耗的对比,仿真结果表明能明显的降低功耗。
最后把各个功能模块组合成在一起,设计出了低功耗的Viterbi译码器,仿真结果表明比起没有采用低功耗技术的译码器,在译码器纠错性能和译码速度不变的情况下,动态功耗降低了33%。
Convolutinal coding is a coding scheme often employed in digital wireless communications.Viterbi decoders are used to decode convolutional codes.
Viterbi decoders employed in digital wireless communications are complex and dissipate large power. With the proliferation of battery powered devices such as cellular phones and laptop computers, power dissipation, along with speed and area, is a major concern in VLSI design. In this thesis, we investigated a low-power design of Viterbi decoders for wireless communications applications.
In CMOS technology the major source of power dissipation is attributed to dynamic power dissipation, which is due to the switching of signal values. The focus of our research in the low-power design of Viterbi decoders is reduction of dynamic power dissipation at logic level in the standard cell design environment.
The VD is composed of four functional units:
1) The branch metrics unit (BMU);
2) The add-compare-select unit (ACS);
3) The path metrics unit ( PMU);
4) The survivor memory unit (SMU);
Regarding the power dissipation of the Viterbi decoder, the SMU is the hottest spot in the Viterbi decoder due to the frequent memory accesses.There are two traditional techniques for the realization of survivor memory unit in viterbi decoder--register exchange (RE) and trace back (TB) method. RE has a very complicated interconnections and needs a high power consumption .TB needs a large quantity of buffers and has long decoding delay. In this paper a modified register-exchange (RE) method is presented, which reduce its memory access rate and its amount of memory, thus, reduces the power consumption. Based on the modified register-exchange (RE) method SMU, a Low power viterbi decoder can be designed. Our experimental result shows the proposed design reduces the dynamic power dissipation of a Viterbi decoder by about 33 percent compared with the one without considering the low-power design.
引文
[1] 王新梅,肖国镇.纠错码原理与方法[M].西安:西安电子科技大学出版社,2001.
[2] 沈振元,聂志泉,赵雪荷. 通信系统原理. 西安电子科技大学出版社.
[3] C.E.Shannon, A mathematical theory of communication ,B.S.T.J.,27, July 1948.
[4] A. J. Viterbi. Error bounds for convolutional odes and asymptotically optimum decoding algorithm. IEEE Transactions on Information Theory,1967,13(2): 260 - 269
[5] J. G. D. Forney. The Viterbi algorithm. Proceedings of the IEEE, 1973, 61(3): 268-278
[6] I. Kang , A. N. Willson Jr.. Low-power Viterbi decoder for CDMA mobile terminals. IEEE Journal of Solid-State Circuits,1998,33(3):473-482.
[7] S. B. Wicker, Error Control Systems for Digital Communication andStorage. Englewood Cliffs, NJ: Prentice-Hall, 1995.
[8] G. K. Yeap, Practical Low Power Digital VLSI Design, Kluwer Academic Publishers, 1998.
[9] 羊性滋,CMOS 电路的低功耗设计技术,半导体技术,1996 年 6 月第 3 期。
[10] 孙猛.VB 高速译码算法及其 FPGA 实现.中国有线电视,3(4):13-18
[11] 张昌芳,雷菁.高速 Viterbi 译码器中幸存路径存储单元的设计与实现. 电子工程师,2005,31(3):11-13
[12] 黄君凯 ,王鑫. 一种高速Viterbi译码器的优化设计及Verilog实现. 微电子与计算机,2005,22(2):178-182
[13] Mohiedin Wainakh, Isam Abboud, Mazen Morhej . Fast decoding Viterbi algorithm. Proceedings of 2004 International Conference on Information and Communication Technologies: From Theory to Applications Publication Date, 2004 , page(s): 289 - 290
[14] [14] Boutillon, E., Demassieux, N.. High speed low power architecture for memory management in a Viterbi decoder. IEEE International Symposium on Circuits and Systems, 1996. ISCAS ''96., ''Connecting the World''., Volume4:284-287
[15] Shung, C.B. , Lin, H.-D. , Cypher, R. , Siegel, P.H. , Thapar, H.K. . Area-efficient architectures for the Viterbi algorithm. I. Theory. IEEE Transactions on Communications,1993,41(4): 636 - 644
[16] Shung, C.B. , Lin, H.-D. , Cypher, R. , Siegel, P.H. , Thapar, H.K. Area-efficient architectures for the Viterbi algorithm II. Applications. IEEE Transactions on ommunications,1993,41(5): 802 - 807
[17] Cabrera, C. , Boo, M. , Bruguera, J.D. .VLSI implementation of an area-efficient architecture for the Viterbi algorithm. IEEE International Conference on Acoustics, Speech, and Signal Processing, 1997, Volume 1: 623 - 626
[18] 赵崇辉,赵旦峰,齐金月.基于 FPGA 的多约束长度 Viterbi 译码器.应用科技,2004,31(5):28-30
[19] 沈礼权, 李明, 王梦, 严来金.CDMA2000 系统中通用高速 Viterbi 译码器的设计与实现.无线通信技术,2004 年第 4 期,page(s):48-50
[20] Kelly, P.H. , Chau, P.M. .A flexible constraint length, foldable Viterbi decoder.Global Telecommunications Conference, 1993, including a Communications Theory Mini-Conference, 1993,volume 1: 631 - 635
[21] Zwolinski, M. , Reeve, J.S. . Behavioural synthesis of an adaptive Viterbi decoder. The 2nd IEE/EURASIP Conference on DSPenabledRadio, 2005, On page(s): 10/1 - 10/4
[22] Ming-Hwa Chan , Wen-Ta Lee , Mao-Chao Lin , Liang-Gee Chen .IC design of an adaptive Viterbi decoder. IEEE Transactions on Consumer Electronics, 1996, 42 ( 1): 52 - 62
[23] Qin Xiang-Ju Zhu Ming-Cheng Wei Zhong-Yi Chao Du ,An adaptive Viterbi decoder based on FPGA dynamic reconfiguration technology. IEEE International Conference on Field-Programmable Technology, 2004, On page(s): 315 - 318
[24] 孙晓岩,付永庆,张文鑫.Viterbi 译码器的 FPGA 实现技术研究.应用科技,2003,30(5):11-13
[25] 魏忠义,覃祥菊.Viterbi译码器的FPGA设计实现与优化.西安工程科技学院学报,2005, 19(1):75-78
[26] 汪晓岩,胡庆生,孙荣久,樊 昊,易浩勇.Viterbi 译码器的硬件实现.微电子学,2002,32(4): 297-301
[27] Irfan, M. , Shah, S.M. , Khan, A.K. .Design and Implementation of Viterbi Encoding and Decoding Algorithm on FPGA . 2005. ICM 2005. The 17th International Conference on Microelectronics, 2005 , page(s): 234 - 239
[28] Reeve, J.S. , Amarasinghe, K. .A FPGA implementation of a parallel Viterbi decoder for block cyclic and convolution codes . IEEE International Conference on Communications, 2004, Volume5 : 2596 - 2599
[29] Pandita, B. Roy, S.K.,Design and implementation of a Viterbi decoder using FPGAs,VLSI Design, 1999. Proceedings. Twelfth International Conference On Publication Date: 7-10 Jan. 1999 On page(s): 611 - 614
[30] 李劲,吕岩.viterbi 译码器设置门限的低功耗设计方法,仪器仪表用户,2004 年第 1期,page(s):71-72
[31] 游余新, 王进祥, 来逢昌,叶以正.高速低功耗 Viterbi 译码器的设计与实现.计算机研究与发展,2003,40(2):360-365
[32] 罗义军,通信中 Viterbi 算法和均衡器的优化设计及低功耗考虑.[浙江大学博士学位论文],浙江:浙江大学,2003 年 7 月
[33] K. Seki , S. Kubota , M. Mizoguchi , S. Kato . Very low power consumption Viterbi decoder LSIC employing the SST (scarce state transition) scheme for multimedia mobile communications. Electronics-Letters, IEEE, 1994,volume30:637-639
[34] I. Kang , A.N. Willson, Jr . A low-power state-sequential Viterbi decoder for CDMA digital cellular applications. IEEE Conference-Paper, 1996,volume4: 272-275 v
[35] Sudhakar, R. , Mukhtar, A. , Zhenzhong Gu .Low-complexity error selective Viterbi decoder. Electronics Letters ,2000,36(2): 147-148
[36] Ranpara, S. , Dong Sam Ha . A low-power Viterbi decoder design for wireless communications applications. Proceedings of Twelfth Annual IEEE ; ASIC/SOC Conference, 1999, page(s): 377 - 381
[37] Wen-Ta Lee , Ming-Hwa Chan , Liang-Gee Chen , Mao-Chao Lin .A single-chip Viterbi decoder for a binary convolutional code using an adaptive algorithm. IEEE Transactions on Consumer Electronics, 1995 ,41(1): 150 - 159
[38] Allan, G. , Simmons, S. .A VLSI implementation of an adaptive-effort low-power Viterbi decoder for wireless communications. Canadian Conference on Electrical and Computer Engineering, 2001, Volume 2: 1183 - 1188
[39] Anderson, J. , Mohan, S. .Sequential Coding Algorithms: A Survey and Cost Analysis. IEEE Transactions on Communications, 1984,32(2): 169- 176
[40] Simmons, S.J. , Ho, S. .Reduced-search trellis decoding of coded 8-PSK over flat fading channels. IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing, 1995, page(s): 241-244
[41] Traber, M. .A low power survivor memory unit for sequential Viterbi-Decoders. IEEE International Symposium on Circuits and Systems ,2001, Volume 4: 214 – 217
[42] Zhu, Y. , Benaissa, M. . A novel ACS scheme for area-efficient Viterbi decoders, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003, Volume 2:264-267
[43] Biver, M. , Kaeslin, H. , Tommasini, C. . In-place updating of path metrics in Viterbi decoders . IEEE Journal of Solid-State Circuits, 1989,24(4): 1158 – 1160
[44] Hekstra, A.P. . An alternative to metric rescaling in Viterbi decoders . IEEE Transactions on Communications, 1989, 37(11): 1220 – 1222
[45] 韩雁,石教英. viterbi 译码器 VLSI 设计中幸存路径存储管理的新方法.电子学报,1996,24(2):124-127
[46] 付永庆,孙晓岩,李福昌. 实现 Viterbi 译码器幸存路径存储及译码输出的一种新方法.应用科技,2003,30(3):25-26
[47] 孙晓岩 ,王 艳, 付永庆. 幸存路径存储及输出的一种新方法.电子技术,2002 年第 6 期:63-64
[48] El-Dib, D.A. , Elmasry, M.I. . Modified register-exchange Viterbi decoder for low-power wireless communications . IEEE Transactions on Circuits and Systems I: Regular Papers, 2004,51(2):371-378
[2] 沈振元,聂志泉,赵雪荷. 通信系统原理. 西安电子科技大学出版社.
[3] C.E.Shannon, A mathematical theory of communication ,B.S.T.J.,27, July 1948.
[4] A. J. Viterbi. Error bounds for convolutional odes and asymptotically optimum decoding algorithm. IEEE Transactions on Information Theory,1967,13(2): 260 - 269
[5] J. G. D. Forney. The Viterbi algorithm. Proceedings of the IEEE, 1973, 61(3): 268-278
[6] I. Kang , A. N. Willson Jr.. Low-power Viterbi decoder for CDMA mobile terminals. IEEE Journal of Solid-State Circuits,1998,33(3):473-482.
[7] S. B. Wicker, Error Control Systems for Digital Communication andStorage. Englewood Cliffs, NJ: Prentice-Hall, 1995.
[8] G. K. Yeap, Practical Low Power Digital VLSI Design, Kluwer Academic Publishers, 1998.
[9] 羊性滋,CMOS 电路的低功耗设计技术,半导体技术,1996 年 6 月第 3 期。
[10] 孙猛.VB 高速译码算法及其 FPGA 实现.中国有线电视,3(4):13-18
[11] 张昌芳,雷菁.高速 Viterbi 译码器中幸存路径存储单元的设计与实现. 电子工程师,2005,31(3):11-13
[12] 黄君凯 ,王鑫. 一种高速Viterbi译码器的优化设计及Verilog实现. 微电子与计算机,2005,22(2):178-182
[13] Mohiedin Wainakh, Isam Abboud, Mazen Morhej . Fast decoding Viterbi algorithm. Proceedings of 2004 International Conference on Information and Communication Technologies: From Theory to Applications Publication Date, 2004 , page(s): 289 - 290
[14] [14] Boutillon, E., Demassieux, N.. High speed low power architecture for memory management in a Viterbi decoder. IEEE International Symposium on Circuits and Systems, 1996. ISCAS ''96., ''Connecting the World''., Volume4:284-287
[15] Shung, C.B. , Lin, H.-D. , Cypher, R. , Siegel, P.H. , Thapar, H.K. . Area-efficient architectures for the Viterbi algorithm. I. Theory. IEEE Transactions on Communications,1993,41(4): 636 - 644
[16] Shung, C.B. , Lin, H.-D. , Cypher, R. , Siegel, P.H. , Thapar, H.K. Area-efficient architectures for the Viterbi algorithm II. Applications. IEEE Transactions on ommunications,1993,41(5): 802 - 807
[17] Cabrera, C. , Boo, M. , Bruguera, J.D. .VLSI implementation of an area-efficient architecture for the Viterbi algorithm. IEEE International Conference on Acoustics, Speech, and Signal Processing, 1997, Volume 1: 623 - 626
[18] 赵崇辉,赵旦峰,齐金月.基于 FPGA 的多约束长度 Viterbi 译码器.应用科技,2004,31(5):28-30
[19] 沈礼权, 李明, 王梦, 严来金.CDMA2000 系统中通用高速 Viterbi 译码器的设计与实现.无线通信技术,2004 年第 4 期,page(s):48-50
[20] Kelly, P.H. , Chau, P.M. .A flexible constraint length, foldable Viterbi decoder.Global Telecommunications Conference, 1993, including a Communications Theory Mini-Conference, 1993,volume 1: 631 - 635
[21] Zwolinski, M. , Reeve, J.S. . Behavioural synthesis of an adaptive Viterbi decoder. The 2nd IEE/EURASIP Conference on DSPenabledRadio, 2005, On page(s): 10/1 - 10/4
[22] Ming-Hwa Chan , Wen-Ta Lee , Mao-Chao Lin , Liang-Gee Chen .IC design of an adaptive Viterbi decoder. IEEE Transactions on Consumer Electronics, 1996, 42 ( 1): 52 - 62
[23] Qin Xiang-Ju Zhu Ming-Cheng Wei Zhong-Yi Chao Du ,An adaptive Viterbi decoder based on FPGA dynamic reconfiguration technology. IEEE International Conference on Field-Programmable Technology, 2004, On page(s): 315 - 318
[24] 孙晓岩,付永庆,张文鑫.Viterbi 译码器的 FPGA 实现技术研究.应用科技,2003,30(5):11-13
[25] 魏忠义,覃祥菊.Viterbi译码器的FPGA设计实现与优化.西安工程科技学院学报,2005, 19(1):75-78
[26] 汪晓岩,胡庆生,孙荣久,樊 昊,易浩勇.Viterbi 译码器的硬件实现.微电子学,2002,32(4): 297-301
[27] Irfan, M. , Shah, S.M. , Khan, A.K. .Design and Implementation of Viterbi Encoding and Decoding Algorithm on FPGA . 2005. ICM 2005. The 17th International Conference on Microelectronics, 2005 , page(s): 234 - 239
[28] Reeve, J.S. , Amarasinghe, K. .A FPGA implementation of a parallel Viterbi decoder for block cyclic and convolution codes . IEEE International Conference on Communications, 2004, Volume5 : 2596 - 2599
[29] Pandita, B. Roy, S.K.,Design and implementation of a Viterbi decoder using FPGAs,VLSI Design, 1999. Proceedings. Twelfth International Conference On Publication Date: 7-10 Jan. 1999 On page(s): 611 - 614
[30] 李劲,吕岩.viterbi 译码器设置门限的低功耗设计方法,仪器仪表用户,2004 年第 1期,page(s):71-72
[31] 游余新, 王进祥, 来逢昌,叶以正.高速低功耗 Viterbi 译码器的设计与实现.计算机研究与发展,2003,40(2):360-365
[32] 罗义军,通信中 Viterbi 算法和均衡器的优化设计及低功耗考虑.[浙江大学博士学位论文],浙江:浙江大学,2003 年 7 月
[33] K. Seki , S. Kubota , M. Mizoguchi , S. Kato . Very low power consumption Viterbi decoder LSIC employing the SST (scarce state transition) scheme for multimedia mobile communications. Electronics-Letters, IEEE, 1994,volume30:637-639
[34] I. Kang , A.N. Willson, Jr . A low-power state-sequential Viterbi decoder for CDMA digital cellular applications. IEEE Conference-Paper, 1996,volume4: 272-275 v
[35] Sudhakar, R. , Mukhtar, A. , Zhenzhong Gu .Low-complexity error selective Viterbi decoder. Electronics Letters ,2000,36(2): 147-148
[36] Ranpara, S. , Dong Sam Ha . A low-power Viterbi decoder design for wireless communications applications. Proceedings of Twelfth Annual IEEE ; ASIC/SOC Conference, 1999, page(s): 377 - 381
[37] Wen-Ta Lee , Ming-Hwa Chan , Liang-Gee Chen , Mao-Chao Lin .A single-chip Viterbi decoder for a binary convolutional code using an adaptive algorithm. IEEE Transactions on Consumer Electronics, 1995 ,41(1): 150 - 159
[38] Allan, G. , Simmons, S. .A VLSI implementation of an adaptive-effort low-power Viterbi decoder for wireless communications. Canadian Conference on Electrical and Computer Engineering, 2001, Volume 2: 1183 - 1188
[39] Anderson, J. , Mohan, S. .Sequential Coding Algorithms: A Survey and Cost Analysis. IEEE Transactions on Communications, 1984,32(2): 169- 176
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