硬盘读写通道若干关键技术的研究与仿真
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摘要
从现代硬盘的技术发展趋势来看,硬盘的磁头、盘片、头盘界面等技术均已取得长足进展,而且未来还有充足的发展空间。即便还存在一些困难,但发展方向和基础理论问题已基本确定。而随着这些技术发展变化带来的一个必然要求就是要解决可能超过10Gb/s的内部数据传输率并将误码率控制在可接受范围之内。目前无论是硬盘通道还是控制器、译码器均尚未能达到处理如此速率的技术水平。而由于硬盘技术更新换代很快,ASIC开发成本又高昂,因此探索通道的仿真研究技术也具有重大意义。
如何处理在超高密度条件下越来越严重的码间干扰和道间干扰,将淹没在各种噪声中的微弱信号提取出来,真实、高速的再现原始数据,是读写通道和编解码器必须协同解决的问题。
读写通道融合了复杂的模数混合信号和数字信号处理技术,是现代硬盘必不可少的核心技术。在介绍读写通道的各种模型和国内外读写通道研究的技术变化趋势之后,可知对图形化读写通道仿真模型的研究可为我国的磁存储工业提供关键性系统结构研究的基础平台。
介绍了硬盘读写通道的主要结构,对通道内各部分的工作原理做了详细分析,按照数据流向分别对读出和写入过程的编解码流程、部分响应方式、自适应均衡、最大似然维特比译码算法做了描述。针对有色噪声对维特比译码器的影响,给出了在维特比译码算法中嵌入噪声预测滤波器的方法,并给出了计算波形自相关系数和噪声自相关系数的方法。此外给出了不同存储密度条件下PR4、EPR4和NPR高阶部分响应的离散时间特性方程,并描绘了它们的网格图。对根据维特比译码中的最可能错误事件,将译码结果进一步进行后处理的方法进行了详细的推导,对错误事件的成因给出了解释。
针对现代硬盘控制器中的高码率游长受限编码方法问题,在分块受限编码基础上,利用输入码字分块后的分布特性,根据计算机系统结构中的Amdahl定律,提出了一种可用于读写通道的高码率游长受限编码方法,给出了标志子块排队规则和无冲突子块映射策略,由它们组成的RLL编码方法既能满足合理的码率限制,又能加以递推用于设计更高码率如128/129、256/257等RLL编码,并且能简单的用Verilog/VHDL等语言实现。利用ModelSim仿真工具仿真了32/33(d=0,k=6)的高码率游长受限编码器,实验表明,采用这种方法所得到的实际码率(0.9697)与理论容量(0.99422)相差很小,且随着k值增加,由于允许的数据字长度n可更长,码率与理论容量越来越接近。
对硬盘高码率游长编码可能发生的误差传播问题做了分析,提出了以域变换的方法实现交错级联编码的方案,并对该方案的原理和实现方法做了分析。结合高码率编码方法,应用10位超长机器字长和变形里德-所罗门编码,具体提出了一套ECC/RLL交错的级联编码方案。这种交错级联编/解码方法能抑制错误传播问题,减少突发错误的长度,获得更好的差错性能和更低的误码率。
设计了基于MATLAB Simulink的图形化硬盘读写通道的仿真模型,能直观显示各模块、各环节的特性以及通道参数修改引起的变化。提出了分块求卷积的方法,来设计不同存储密度条件下的Lorentz任意波形发生器。分析了硬盘伺服信息的频率谱,针对直流分量和噪声,设计了基线校正和连续时间滤波器,给出了VGA的门限判别方法、梯度产生算法以及AGC增益的稳定时间,并设计了自适应FIR均衡器模型。分析了高存储密度条件下(PW50/T>2.5)的有色噪声来源,提出了FIR型白化滤波器方法来抑制有色噪声,并设计了可加入噪声预测算法的软判决噪声预测维特比译码器模型。对译码中错误事件的成因以及后处理方法做了讨论。根据伺服信息中扇区标记字段由格雷码编码的特性,提出了一种检验模型有效性的简便方法。
利用该模型,对自定义序列、随机序列和导入的实际硬盘信号等三种不同类型的输入序列分别进行了分析。实验表明,模型能对三种数据正确处理,并能用误码率来分析模型中引入不同噪声时的读写通道的性能。在加入噪声预测算法后,分别描述了4个系数的FIR预测器和20个系数的FIR预测器的幅频响应曲线。通过设置通道模型中的AWGN模块的SNR参数值为5～12,并分别测量不同算法下误码总数达到10个时的位错误率,发现在相同信噪比下,通过对均衡器输出的有色噪声和残余干扰进行白化,系统的位错误率得到了不同程度的降低。在BER=10-4附近时,设置1个系数(N=1)的FIR预测器,通道的SNR比PRML可提高约1dB。系数设为4个,改善更明显,约为2dB。而对应SNR都等于12时,BER随FIR系数增加按数量级下降,性能改进明显。
According to the technology trend of modern Hard disk, the technologies of magnetic head, disk medium, interface between head and disk have made significant progress, also have adequate development of space in the future. Even there are some difficults, the developing direction and elementalstudies have been basically decided. Along with these technology changes, a neccesory requirement is to meet internal data transforming rate which maybe more than 10Gb/s, and control the bit error rate to acceptable range. Now whether the read/write channel or controller, detector can not reach the skills to process such high-speed data transforming. Moreover because of fast upgrading of thecnologies and expensive development costs of ASIC, the reseach and development of simulation method about read/write channel has important ignificance.
How to deal with the intersymbol interference and interference between tracks, to extract weak signals from all kinds of noise, and to high-speed regenerate the original data, are the questions which need to cooperating solute by read/write channel and encoder or decoder.
The Read/Write channel integrates advanced analog and digital filter technologies, is a core technology and indispensable to modern hard disk. After introducing several models of read/write channel and technology trends at domestic and abroad, it can be seen that the reseach about grahic simulation of read/write channel can support key foundation studing platform to magnetic industry in our country.
Instroducing the structure and principle of read/write channel, respectively descripting encoding/decoding process, partial response, adaptive equalization and maximum likelihood viterbi detection algorithm according to data stream. Aimed to reduce color noise in channel that damages the preconditions of viterbi detector, an embedded noise prediction algorithm in viterbi detection is proposed. Giving the computing method of waveform autocorrelation coefficients, and deriving noise sequence autocorrelation coefficients, furthermore introducing the discrete time characteristics of PR4, EPR4 and high level partial response form such as NPR under the different storage densities, and descript their trellis structures. Afterthat the post processing method using PR4 pipeline struct to auxiliarily parse EPR4 channel is discussed.
Based on the block RLL coding scheme, the distribution characteristic of input codewords and Amdahl’s low in computer architecture, a high rating RLL coding scheme which could be used in read/write channel is proposed, and a set of rules to queue flag sub-blocks as well as strategies to map non-conflict sub-blocks is established. This high rating RLL coding scheme made of rules and strategies can not only meet reasonable coding rate limitation, but also can be recursively used to design higher code rating RLL coding scheme such as 128/129 or 256/257, moreover can be simplily implemented by Verilog/VHDL language. A 32/33(d=0, k=6) high rating RLLencoder with ModelSim software is simulated. It can be seen from the experiment results that the real code rate designed with this scheme has little difference with theoretical code rate, and increasing with parameter k, the code rate can approximate to theoretical limitation of code rate due to tolerance longer codeword.
Furthermore the possible error propagation that maybe happen in the process of RLL decoding is analyzed, and a field transforming method to implement the ECC/RLL permuted coding sheme is proposed, also its principle of this scheme is explained. Combined with high rating coding scheme and 10 bits machinery word, an ECC/RLL permuted coding scheme mixed with HRRLL, LRRLL and RS code is proposed. This sheme can be used to contain error propagation, decrease the length of burst errors and acquire better performance and lower BER.
A graphic simulation model of read/write channel of hard disk based on MATLAB Simulink has been designed to observe each module’s characteristic and all kinds of changes caused by modifying channel parameters. A block convolution method is proposed to design a Lorentz arbitrary waveform generator under different storage densities. To contain the DC component and noise, the frequency spectrum of servo signals is analyzed, a baseline correction filter and a continuous time filter are designed, a technique of VGA threshold judgement and a grident generation algorithm are proposed, the stable time of AGC gain is set, also an adaptive FIR equalizer to reshape the input waveform is designed. Because color noise would impact the precondition of viterbi algorithm, a FIR white noise predictive filter is proposed to contain it, furthermore a soft-decision viterbi detector model embedded noise prediction algorithm is developed. The reasons of error events in the process of detection and post-processing method that dectect EPRML channel symbols just with PRML channel trellis are all discussed. According to the characteristic of graycode in the sector mark field of servo signals, a simple and convenient method to judge the validity of our simulation model is proposed.
With this simulation model, three kinds of input sequences, specified sequence, random sequence and derived actual hard disk signal sequence are compared. The experiment shows that the model can deal with three kinds of input sequences, and analyze the performance of channel when import different noise according to compare bit error rate. The amplitude-frequency response graph of 4-tap FIR predictor and 20-tap FIR predictor both embedded noise predictive algorithm is descripted. When setup SNR parameter of AWGN module from 5 to 12, measuring BER under different algorithm as the number of error symbols reach to 10, it can be seen from the results that the BER decrease with various degrees after whitening color noise and residual interference in the output signals of equalizer. When BER is near 10-4, and tap’s number of FIR predictor is set to 1, channel’s SNR can improve 1dB than PRML. When tap’s number of FIR predictor is set to 4, the improvement is much more obvious, about 2dB. As for SNR becoming 12, BER descend according to the number of class along with the tap’s number of FIR, and channel’s performance achieves obvious improvement.
如何处理在超高密度条件下越来越严重的码间干扰和道间干扰,将淹没在各种噪声中的微弱信号提取出来,真实、高速的再现原始数据,是读写通道和编解码器必须协同解决的问题。
读写通道融合了复杂的模数混合信号和数字信号处理技术,是现代硬盘必不可少的核心技术。在介绍读写通道的各种模型和国内外读写通道研究的技术变化趋势之后,可知对图形化读写通道仿真模型的研究可为我国的磁存储工业提供关键性系统结构研究的基础平台。
介绍了硬盘读写通道的主要结构,对通道内各部分的工作原理做了详细分析,按照数据流向分别对读出和写入过程的编解码流程、部分响应方式、自适应均衡、最大似然维特比译码算法做了描述。针对有色噪声对维特比译码器的影响,给出了在维特比译码算法中嵌入噪声预测滤波器的方法,并给出了计算波形自相关系数和噪声自相关系数的方法。此外给出了不同存储密度条件下PR4、EPR4和NPR高阶部分响应的离散时间特性方程,并描绘了它们的网格图。对根据维特比译码中的最可能错误事件,将译码结果进一步进行后处理的方法进行了详细的推导,对错误事件的成因给出了解释。
针对现代硬盘控制器中的高码率游长受限编码方法问题,在分块受限编码基础上,利用输入码字分块后的分布特性,根据计算机系统结构中的Amdahl定律,提出了一种可用于读写通道的高码率游长受限编码方法,给出了标志子块排队规则和无冲突子块映射策略,由它们组成的RLL编码方法既能满足合理的码率限制,又能加以递推用于设计更高码率如128/129、256/257等RLL编码,并且能简单的用Verilog/VHDL等语言实现。利用ModelSim仿真工具仿真了32/33(d=0,k=6)的高码率游长受限编码器,实验表明,采用这种方法所得到的实际码率(0.9697)与理论容量(0.99422)相差很小,且随着k值增加,由于允许的数据字长度n可更长,码率与理论容量越来越接近。
对硬盘高码率游长编码可能发生的误差传播问题做了分析,提出了以域变换的方法实现交错级联编码的方案,并对该方案的原理和实现方法做了分析。结合高码率编码方法,应用10位超长机器字长和变形里德-所罗门编码,具体提出了一套ECC/RLL交错的级联编码方案。这种交错级联编/解码方法能抑制错误传播问题,减少突发错误的长度,获得更好的差错性能和更低的误码率。
设计了基于MATLAB Simulink的图形化硬盘读写通道的仿真模型,能直观显示各模块、各环节的特性以及通道参数修改引起的变化。提出了分块求卷积的方法,来设计不同存储密度条件下的Lorentz任意波形发生器。分析了硬盘伺服信息的频率谱,针对直流分量和噪声,设计了基线校正和连续时间滤波器,给出了VGA的门限判别方法、梯度产生算法以及AGC增益的稳定时间,并设计了自适应FIR均衡器模型。分析了高存储密度条件下(PW50/T>2.5)的有色噪声来源,提出了FIR型白化滤波器方法来抑制有色噪声,并设计了可加入噪声预测算法的软判决噪声预测维特比译码器模型。对译码中错误事件的成因以及后处理方法做了讨论。根据伺服信息中扇区标记字段由格雷码编码的特性,提出了一种检验模型有效性的简便方法。
利用该模型,对自定义序列、随机序列和导入的实际硬盘信号等三种不同类型的输入序列分别进行了分析。实验表明,模型能对三种数据正确处理,并能用误码率来分析模型中引入不同噪声时的读写通道的性能。在加入噪声预测算法后,分别描述了4个系数的FIR预测器和20个系数的FIR预测器的幅频响应曲线。通过设置通道模型中的AWGN模块的SNR参数值为5～12,并分别测量不同算法下误码总数达到10个时的位错误率,发现在相同信噪比下,通过对均衡器输出的有色噪声和残余干扰进行白化,系统的位错误率得到了不同程度的降低。在BER=10-4附近时,设置1个系数(N=1)的FIR预测器,通道的SNR比PRML可提高约1dB。系数设为4个,改善更明显,约为2dB。而对应SNR都等于12时,BER随FIR系数增加按数量级下降,性能改进明显。
According to the technology trend of modern Hard disk, the technologies of magnetic head, disk medium, interface between head and disk have made significant progress, also have adequate development of space in the future. Even there are some difficults, the developing direction and elementalstudies have been basically decided. Along with these technology changes, a neccesory requirement is to meet internal data transforming rate which maybe more than 10Gb/s, and control the bit error rate to acceptable range. Now whether the read/write channel or controller, detector can not reach the skills to process such high-speed data transforming. Moreover because of fast upgrading of thecnologies and expensive development costs of ASIC, the reseach and development of simulation method about read/write channel has important ignificance.
How to deal with the intersymbol interference and interference between tracks, to extract weak signals from all kinds of noise, and to high-speed regenerate the original data, are the questions which need to cooperating solute by read/write channel and encoder or decoder.
The Read/Write channel integrates advanced analog and digital filter technologies, is a core technology and indispensable to modern hard disk. After introducing several models of read/write channel and technology trends at domestic and abroad, it can be seen that the reseach about grahic simulation of read/write channel can support key foundation studing platform to magnetic industry in our country.
Instroducing the structure and principle of read/write channel, respectively descripting encoding/decoding process, partial response, adaptive equalization and maximum likelihood viterbi detection algorithm according to data stream. Aimed to reduce color noise in channel that damages the preconditions of viterbi detector, an embedded noise prediction algorithm in viterbi detection is proposed. Giving the computing method of waveform autocorrelation coefficients, and deriving noise sequence autocorrelation coefficients, furthermore introducing the discrete time characteristics of PR4, EPR4 and high level partial response form such as NPR under the different storage densities, and descript their trellis structures. Afterthat the post processing method using PR4 pipeline struct to auxiliarily parse EPR4 channel is discussed.
Based on the block RLL coding scheme, the distribution characteristic of input codewords and Amdahl’s low in computer architecture, a high rating RLL coding scheme which could be used in read/write channel is proposed, and a set of rules to queue flag sub-blocks as well as strategies to map non-conflict sub-blocks is established. This high rating RLL coding scheme made of rules and strategies can not only meet reasonable coding rate limitation, but also can be recursively used to design higher code rating RLL coding scheme such as 128/129 or 256/257, moreover can be simplily implemented by Verilog/VHDL language. A 32/33(d=0, k=6) high rating RLLencoder with ModelSim software is simulated. It can be seen from the experiment results that the real code rate designed with this scheme has little difference with theoretical code rate, and increasing with parameter k, the code rate can approximate to theoretical limitation of code rate due to tolerance longer codeword.
Furthermore the possible error propagation that maybe happen in the process of RLL decoding is analyzed, and a field transforming method to implement the ECC/RLL permuted coding sheme is proposed, also its principle of this scheme is explained. Combined with high rating coding scheme and 10 bits machinery word, an ECC/RLL permuted coding scheme mixed with HRRLL, LRRLL and RS code is proposed. This sheme can be used to contain error propagation, decrease the length of burst errors and acquire better performance and lower BER.
A graphic simulation model of read/write channel of hard disk based on MATLAB Simulink has been designed to observe each module’s characteristic and all kinds of changes caused by modifying channel parameters. A block convolution method is proposed to design a Lorentz arbitrary waveform generator under different storage densities. To contain the DC component and noise, the frequency spectrum of servo signals is analyzed, a baseline correction filter and a continuous time filter are designed, a technique of VGA threshold judgement and a grident generation algorithm are proposed, the stable time of AGC gain is set, also an adaptive FIR equalizer to reshape the input waveform is designed. Because color noise would impact the precondition of viterbi algorithm, a FIR white noise predictive filter is proposed to contain it, furthermore a soft-decision viterbi detector model embedded noise prediction algorithm is developed. The reasons of error events in the process of detection and post-processing method that dectect EPRML channel symbols just with PRML channel trellis are all discussed. According to the characteristic of graycode in the sector mark field of servo signals, a simple and convenient method to judge the validity of our simulation model is proposed.
With this simulation model, three kinds of input sequences, specified sequence, random sequence and derived actual hard disk signal sequence are compared. The experiment shows that the model can deal with three kinds of input sequences, and analyze the performance of channel when import different noise according to compare bit error rate. The amplitude-frequency response graph of 4-tap FIR predictor and 20-tap FIR predictor both embedded noise predictive algorithm is descripted. When setup SNR parameter of AWGN module from 5 to 12, measuring BER under different algorithm as the number of error symbols reach to 10, it can be seen from the results that the BER decrease with various degrees after whitening color noise and residual interference in the output signals of equalizer. When BER is near 10-4, and tap’s number of FIR predictor is set to 1, channel’s SNR can improve 1dB than PRML. When tap’s number of FIR predictor is set to 4, the improvement is much more obvious, about 2dB. As for SNR becoming 12, BER descend according to the number of class along with the tap’s number of FIR, and channel’s performance achieves obvious improvement.
引文
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