高速帧同步格式化器
摘要
高速数据传输处理技术是现代通信系统研究的主要新热点方向之一。随着数据传输速率增高，其帧同步的实现就越来越困难，而该领域主要是应用高速数字电路技术。基于此，本论文试图解决其在空间卫星通信上的应用－“高速帧同步格式化器”的实现。
高速帧同步格式化器是遥感卫星地面接收系统中必不可少的关键设备之一，主要将从卫星接收到的高速数码流格式化，使计算机得以辨识每一帧的起始位置，然后将数码流经高速接口进入计算机进行预处理。现代军事和民用对地观察卫星的分辨力越来越高，因此对地面站系统的性能的要求也越来越高，而对作为卫星地面站的核心关键之一的帧同步格式化器的要求当然也是越来越高，不仅对速率的要求提高了很多，还要求其能应用于多种卫星。高速帧同步格式化器的国外报价昂贵，并且军用卫星数据格式及加密都为国家机密，所以不可能都购买国外的产品，必须国产化。这一工作的完成，将在这个关键环节上有助于我国新型遥感卫星、军用卫星地面系统的建设，促进我国遥感卫星应用技术的发展。
本文主要完成了高速帧同步格式化的设计方法、仿真及其软硬件实现。该高速帧同步格式化器最高工作速率为150Mbps，适用于多颗卫星多种帧格式，可通过计算机初始化控制。其可控参数有：IQ路信息、帧头长度、帧同步码内容、帧同步误差容限（同步门限）、帧保护容限（锁定门限）、帧保护系数（失锁门限）、帧的长度。为完成设计指标，作者查阅了大量相关资料，同时完成了：FPGA编程实现主体设计、系统的仿真、制作高速PCB板、编写单片机控制程序、调试实验。
实验结果表明，高速帧同步格式化器的设计达到了速率高，控制灵活的要求。
High-speed data transfer technique is one of the key hotspot aspects in modern communication system. It becomes more difficult to realize frame synchronization with higher data transfer speed, and this field applies mostly high-speed digital circuits technique. So this dissertation named "High-Speed Frame-Synchronizer" tries to resolve the application of high-speed digital circuit technique in satellite communication.
High-Speed Frame-Synchronizer is an absolutely necessarily key device of the Remote Sensing Satellite's Ground-Receiving system. It is mainly used to format the high-speed data stream, so that computer can get the beginning address of every frame of the high-speed data stream, and then data stream would be send to computer for pretreatment through high-speed interface. The observing ground satellites of modem time have higher resolving power, so that they require ground station system with more performance accordingly. As the key device of ground station system, High-Speed Frame-Synchronizer needs to have higher performance also. High-Speed Frame-Synchronizer not only is required higher speed but also requires to be used for more kind of satellites. It is impossible to buy the High-Speed Frame-Synchronizer overseas because of high price, and more important, the way of data format and encrypt of military satellites is involved the secret of nation. We must research and produce the key device by ourselves. The achievement in the technique will help our country in constructing the system of new Remote Sensing Satellites and military satellite's ground stations.
The dissertation accomplishes the design, simulation and realization in software and hardware of High-Speed Frame-Synchronizer, which its highest speed is 150Mbps. The High-Speed Frame-Synchronizer can be used to work for many kind of satellites, and can be controlled
by computer initializing. The High-Speed Frame-Synchronizer can be controlled by changing parameter as followings: IQ routes information, the length of frame head, the content of frame-synchronization codes, frame-synchronization error sufferance, frame protect sufferance, frame protect coefficient, the length of frame. To achieve design target, the author referred a great deal of correlated data, and accomplished hereinafter parts: compile programs of FPGA to realize main design, simulate system, protract high-speed PCB board, compile single chip machine's programs for control, and debug experiment.
The results of experiment indicates that the High-Speed Frame-Synchronizer's design meet the request of high-speed and flexible control.
高速帧同步格式化器是遥感卫星地面接收系统中必不可少的关键设备之一，主要将从卫星接收到的高速数码流格式化，使计算机得以辨识每一帧的起始位置，然后将数码流经高速接口进入计算机进行预处理。现代军事和民用对地观察卫星的分辨力越来越高，因此对地面站系统的性能的要求也越来越高，而对作为卫星地面站的核心关键之一的帧同步格式化器的要求当然也是越来越高，不仅对速率的要求提高了很多，还要求其能应用于多种卫星。高速帧同步格式化器的国外报价昂贵，并且军用卫星数据格式及加密都为国家机密，所以不可能都购买国外的产品，必须国产化。这一工作的完成，将在这个关键环节上有助于我国新型遥感卫星、军用卫星地面系统的建设，促进我国遥感卫星应用技术的发展。
本文主要完成了高速帧同步格式化的设计方法、仿真及其软硬件实现。该高速帧同步格式化器最高工作速率为150Mbps，适用于多颗卫星多种帧格式，可通过计算机初始化控制。其可控参数有：IQ路信息、帧头长度、帧同步码内容、帧同步误差容限（同步门限）、帧保护容限（锁定门限）、帧保护系数（失锁门限）、帧的长度。为完成设计指标，作者查阅了大量相关资料，同时完成了：FPGA编程实现主体设计、系统的仿真、制作高速PCB板、编写单片机控制程序、调试实验。
实验结果表明，高速帧同步格式化器的设计达到了速率高，控制灵活的要求。
High-speed data transfer technique is one of the key hotspot aspects in modern communication system. It becomes more difficult to realize frame synchronization with higher data transfer speed, and this field applies mostly high-speed digital circuits technique. So this dissertation named "High-Speed Frame-Synchronizer" tries to resolve the application of high-speed digital circuit technique in satellite communication.
High-Speed Frame-Synchronizer is an absolutely necessarily key device of the Remote Sensing Satellite's Ground-Receiving system. It is mainly used to format the high-speed data stream, so that computer can get the beginning address of every frame of the high-speed data stream, and then data stream would be send to computer for pretreatment through high-speed interface. The observing ground satellites of modem time have higher resolving power, so that they require ground station system with more performance accordingly. As the key device of ground station system, High-Speed Frame-Synchronizer needs to have higher performance also. High-Speed Frame-Synchronizer not only is required higher speed but also requires to be used for more kind of satellites. It is impossible to buy the High-Speed Frame-Synchronizer overseas because of high price, and more important, the way of data format and encrypt of military satellites is involved the secret of nation. We must research and produce the key device by ourselves. The achievement in the technique will help our country in constructing the system of new Remote Sensing Satellites and military satellite's ground stations.
The dissertation accomplishes the design, simulation and realization in software and hardware of High-Speed Frame-Synchronizer, which its highest speed is 150Mbps. The High-Speed Frame-Synchronizer can be used to work for many kind of satellites, and can be controlled
by computer initializing. The High-Speed Frame-Synchronizer can be controlled by changing parameter as followings: IQ routes information, the length of frame head, the content of frame-synchronization codes, frame-synchronization error sufferance, frame protect sufferance, frame protect coefficient, the length of frame. To achieve design target, the author referred a great deal of correlated data, and accomplished hereinafter parts: compile programs of FPGA to realize main design, simulate system, protract high-speed PCB board, compile single chip machine's programs for control, and debug experiment.
The results of experiment indicates that the High-Speed Frame-Synchronizer's design meet the request of high-speed and flexible control.
引文
[1] 李广军 孟宪元 《可编程ASIC设计及应用》 电子科技大学出版社 2000
[2] 侯伯亨 顾新 《VHDL硬件描述语言与数字逻辑电路设计》 西安电子科技大学出版社 1999
[3] 赵雅兴 《FPGA原理、设计与应用》 天津大学出版社 1998
[4] 宋万杰 罗丰 吴顺君 《CPLD技术及其应用》 西安电子科技大学出版社2000
[5] 王兴亮 林家薇 王瑜 达新宇 《数字通信原理与技术》 西安电子科技大学出版社 2001
[6] 樊昌信 张甫翊 许炳祥 吴成柯 《国防工业出版社》 2001
[7] 冯重熙等 《现代数字通信技术》 人民邮电出版社
[8] 赵世强 许杰 荆炳礼 王兴亮 王瑜 《电子电路EDA技术》 西安电子科技大学出版社 2000
[9] 李棠之 杜国新 《通信电子线路》 电子工业出版社 2000
[10] 苏文平 《新型电子电路应用实例精选》 北京航空航天大学出版社 1999
[11]孙涵芳 徐爱卿 《MCS－51/96系列单片机原理及应用》 北京航空航天大学出版社 1996
[12] 武庆生 仇梅 《单片机原理与应用》 电子科技大学出版社
[13] 白同云 吕晓德 《电磁兼容设计》 北京邮电大学出版社 2001
[14] 张松梅 《C++语言教程》 电子科技大学出版社 1993
[15] 王乐毅 《EDA设计技术与方法－EDA方法及其进展》 青岛化工学院报
[16] 李泞亚 《34Mb/s数字微波帧同步检测与保护电路设计》
[17] 蒋伟荣 《EDA设计流水线技术的应用》 湖北汽车工业学院 2000.3
[18] 刘捷臣 郑智磊 范月珍 高良检 《FPGA-ASIC设计的新方法》 微处理机
[19] 侯同强 刘和平 《FPGA与CPLD器件的特点与应用》 电子与自动化
2000 年 第2期
[20] 米良 常青 陈辉煌 《VHDL逻辑综合及FPGA实现》 微电子学 1996.10
[21] 邓仰东 王志华 《VHDL硬件描述语言的最新发展》 电子科技导报
[22] 析伟 《高速PCB板设计信号完整性问题研究》
[23] 袁子建 吴志敏 高举 《高速PCB板的过孔设计》
[24] 王素珍 《两类高密度可编程器件CPLD与FPGA的比较分析》 内蒙古科技与经济
[25] Mentor Graphtics公司 张忠 《自顶向下的FPGA设计》
[26] AMD's Application note "High-Speed Board Design Techniques"
[27] Patrick Robertson “Improving Frame Synchronization When Using Convolutional Codes” German Aerospace Research Establishment (DLR) Institute for communications Technology
[28] SHUJI KUBOTA MASAHIRO MORIKURA SHUZO KATO "High-Quality Frame-Synchronization for Satellite Video Signal Transmission" NTT Wireless Systems Laboratories Japan
[29] C.J.HOSSACK and C.G.GUY "The Route From VHDL to FPGA Using Synthesis" Department of Engineering,University of Reading,Whiteknights,Reading,FG62AY,UK
[30] C.G.Harrison and P.L.Jones "Xilinx FPGA design in a group environment using VHDL and synthesis tools"
[31] Xiangning Chen Yan Li Shixin Cheng "Frame Synchronization By De-Correlation Detection" Southeast University National Mobile Communications Research Lab. International Conference on Communication Technology ICCT'98 October22-24,1998 Beijing,China
[32] Eduardo de Vasconcelos,Rui L.Aguiar "FRAME DETECTION IN HIGH BIT-RATE CMOS SYSTEMS
[33] Xie Qiu-cheng. "A New Searching Method of Optimum Frame Synchronization Codes" ITC'86.USA.
[34] "Board Station 500 for New User" Mentor Graphics Corp,1 995
[35] "Allegro- Printed Circuit Board Design System" Valid L ogic Systems,Inc,
1988
[36] DONG Xiu-jie, GAO hui, ZHANG Li-na "Optimum Design in the Circuit Using VHDL" Electricity Engineering Dept.,Zhongyuan Institute of Technology ,Zhengzhou 450007,China
[37] Allen Dewey, Aart J.Geus."VHDL Toward a Unified View of Design" IEEE Edsing&Test of Computers,June 1992,pp.8~17
[38]XILINX Product Overview,Volume 2002
[2] 侯伯亨 顾新 《VHDL硬件描述语言与数字逻辑电路设计》 西安电子科技大学出版社 1999
[3] 赵雅兴 《FPGA原理、设计与应用》 天津大学出版社 1998
[4] 宋万杰 罗丰 吴顺君 《CPLD技术及其应用》 西安电子科技大学出版社2000
[5] 王兴亮 林家薇 王瑜 达新宇 《数字通信原理与技术》 西安电子科技大学出版社 2001
[6] 樊昌信 张甫翊 许炳祥 吴成柯 《国防工业出版社》 2001
[7] 冯重熙等 《现代数字通信技术》 人民邮电出版社
[8] 赵世强 许杰 荆炳礼 王兴亮 王瑜 《电子电路EDA技术》 西安电子科技大学出版社 2000
[9] 李棠之 杜国新 《通信电子线路》 电子工业出版社 2000
[10] 苏文平 《新型电子电路应用实例精选》 北京航空航天大学出版社 1999
[11]孙涵芳 徐爱卿 《MCS－51/96系列单片机原理及应用》 北京航空航天大学出版社 1996
[12] 武庆生 仇梅 《单片机原理与应用》 电子科技大学出版社
[13] 白同云 吕晓德 《电磁兼容设计》 北京邮电大学出版社 2001
[14] 张松梅 《C++语言教程》 电子科技大学出版社 1993
[15] 王乐毅 《EDA设计技术与方法－EDA方法及其进展》 青岛化工学院报
[16] 李泞亚 《34Mb/s数字微波帧同步检测与保护电路设计》
[17] 蒋伟荣 《EDA设计流水线技术的应用》 湖北汽车工业学院 2000.3
[18] 刘捷臣 郑智磊 范月珍 高良检 《FPGA-ASIC设计的新方法》 微处理机
[19] 侯同强 刘和平 《FPGA与CPLD器件的特点与应用》 电子与自动化
2000 年 第2期
[20] 米良 常青 陈辉煌 《VHDL逻辑综合及FPGA实现》 微电子学 1996.10
[21] 邓仰东 王志华 《VHDL硬件描述语言的最新发展》 电子科技导报
[22] 析伟 《高速PCB板设计信号完整性问题研究》
[23] 袁子建 吴志敏 高举 《高速PCB板的过孔设计》
[24] 王素珍 《两类高密度可编程器件CPLD与FPGA的比较分析》 内蒙古科技与经济
[25] Mentor Graphtics公司 张忠 《自顶向下的FPGA设计》
[26] AMD's Application note "High-Speed Board Design Techniques"
[27] Patrick Robertson “Improving Frame Synchronization When Using Convolutional Codes” German Aerospace Research Establishment (DLR) Institute for communications Technology
[28] SHUJI KUBOTA MASAHIRO MORIKURA SHUZO KATO "High-Quality Frame-Synchronization for Satellite Video Signal Transmission" NTT Wireless Systems Laboratories Japan
[29] C.J.HOSSACK and C.G.GUY "The Route From VHDL to FPGA Using Synthesis" Department of Engineering,University of Reading,Whiteknights,Reading,FG62AY,UK
[30] C.G.Harrison and P.L.Jones "Xilinx FPGA design in a group environment using VHDL and synthesis tools"
[31] Xiangning Chen Yan Li Shixin Cheng "Frame Synchronization By De-Correlation Detection" Southeast University National Mobile Communications Research Lab. International Conference on Communication Technology ICCT'98 October22-24,1998 Beijing,China
[32] Eduardo de Vasconcelos,Rui L.Aguiar "FRAME DETECTION IN HIGH BIT-RATE CMOS SYSTEMS
[33] Xie Qiu-cheng. "A New Searching Method of Optimum Frame Synchronization Codes" ITC'86.USA.
[34] "Board Station 500 for New User" Mentor Graphics Corp,1 995
[35] "Allegro- Printed Circuit Board Design System" Valid L ogic Systems,Inc,
1988
[36] DONG Xiu-jie, GAO hui, ZHANG Li-na "Optimum Design in the Circuit Using VHDL" Electricity Engineering Dept.,Zhongyuan Institute of Technology ,Zhengzhou 450007,China
[37] Allen Dewey, Aart J.Geus."VHDL Toward a Unified View of Design" IEEE Edsing&Test of Computers,June 1992,pp.8~17
[38]XILINX Product Overview,Volume 2002