专用信息处理模块设计
|
摘要
近年来，CPLD／FPGA技术迅速发展，已经成为数字信号处理的重要技术之一。本文讨论的就是应用CPLD／FPGA来实现两个专用信息处理模块的设计。它们分别是图象压缩系统的图象反变换模块—S+P逆变换模块及数字脉冲压缩系统的核心模块—4096点FFT变换模块。在第一部分中，首先介绍了S+P逆变换的原理，该变换实现简单而且变换性能较好，这是某图象压缩系统中所采用的图象编码方法的基础。然后说明了基于CPLD的S+P逆变换硬件实现方案。在第二部分中，首先说明了数字脉压技术是现代雷达中重要的信号处理技术之一，而4096点FFT变换模块就是硬件实现脉压技术的核心部分，然后说明了基4FFT的基本知识以及基于FPGA的详细的硬件实现方案。
In recent years, the rapidly developing technology of CPLD/FPGA has been one of important technology of digital signal processing. In this paper what is mainly discussed is the hardware implementation of the two application specific information processing modules by CPLD or FPGA, which are S+P inverse transformation, the inverse transform module of an image compressing system, and 4096-point complex FFT/IFFT module, the central module of the digital pulse compressing system. In the former, firstly the related knowledge of S+P inverse transform is presented. Easy in implementation, good in storage space, such transform is the base of an image coding algorithm image compressing system. Secondly, the hardware implementation based on CPLD of the S+P inverse transformation is shown. In the latter, firstly the fact that digital pulse compressing technology is one of the most important ways of signal processing in modern radar is introduced. The module of 4096-point complex FFT/IFFT play a very important role in ha
rdware implementation of digital pulse compressing system. Secondly the basic theory of Radix-4 FFT and the hardware implementation based on FPGA of the 4096-point complex FFT/IFFT is illustrated in detail.
In recent years, the rapidly developing technology of CPLD/FPGA has been one of important technology of digital signal processing. In this paper what is mainly discussed is the hardware implementation of the two application specific information processing modules by CPLD or FPGA, which are S+P inverse transformation, the inverse transform module of an image compressing system, and 4096-point complex FFT/IFFT module, the central module of the digital pulse compressing system. In the former, firstly the related knowledge of S+P inverse transform is presented. Easy in implementation, good in storage space, such transform is the base of an image coding algorithm image compressing system. Secondly, the hardware implementation based on CPLD of the S+P inverse transformation is shown. In the latter, firstly the fact that digital pulse compressing technology is one of the most important ways of signal processing in modern radar is introduced. The module of 4096-point complex FFT/IFFT play a very important role in ha
rdware implementation of digital pulse compressing system. Secondly the basic theory of Radix-4 FFT and the hardware implementation based on FPGA of the 4096-point complex FFT/IFFT is illustrated in detail.
引文
[1]A.V.奥本海姆、R.W.谢弗，《数字信号处理》，科学出版社，1980
[2]赵树杰、史林，《数字信号处理》，西安电子科技大学出版社，1997．10
[3]张澄波，《综合孔径雷达原理、系统分析与应用》，科学出版社，1989．11
[4]希尔曼，曼若斯，《雷达信息处理的理论与技术》，1987
[5]苏洪涛，《雷达脉冲压缩系统设计及实现》，西安电子科技大学硕士论文，2000年1月
[6]蔡献峰，《静止图象压缩编码技术研究》，西安电子科技大学硕士论文，1999年1月
[7]Xilinx Corporation,Logicore,"High-Performance 1024-Point Complex FFT/IFFT V.0",July 5,2000
[8]Xilinx,Inc.,Logicore,"Dual-Port Block Memory for Virtex,Virtex-Ⅱ,and Spartan-Ⅱ V3.1",March 2,2001
[9]Xilinx,Inc,"Virtex-Ⅱ 1.5V Field-Programmable Gate Arrays",April 2,2001
[10]Charles Wu SC & Marketing-TI Taiwan,Digital Processing Solutions,"Implementing the Radix-4 Decimation in Frequency(DIF)Fast Fourier Transform(FFT)Algorithm Using a TMS320C80 DSP",January 1998
[11]Nabeel Shirazi,Peter M.Athanas,and A.Lynn Abbott,Virgin Polyteclmic Institute and State University,Btadley Departmentof Electrical Engineering,"Implemen-tation of a 2-D Fast Fourier Transform on a FPGA-Based Custom Computing Machine"
[12]Optimized DSP Library for C Progreammers on the TMS320C62X,Ver 0.6 Beta,"TMS320C62x DSPLIB User's Guide",January,2000
[13]Yao-Ting Cheng,TEXAS indtruments,Application Report."Autoscaling Radix-4 FFT for TMS320C6000",March 2000
[14]B. Wei,H.Du and H.Chen,"A Complex-Number Multiplier Using Radix-4 Digits,"Proceedings of the 12th Symposium on Computer Arithmetic,1995.
[15]lan O'Donnell and Dennis Yee."FFT Implementation Exploration"
[16]Amir Said and William A.Peralman."An image multiresolution representation for lossless and lossy compression",IEEE Trans.On Image Processing.vol.5,no.9,September 1996
[17]J.Singh,A.Antoniou, and D.J.Shpak."Hardware implementtation of a wavelet based image compression coder"
[18]QuickLogic Corporation. "QuickLogic's Expanding Families of ESPs & FPGAs"
[19]Altera Inc.,data sheet,Ver.3, "Fast Fourier Transform",Oct 1997
[20]Altera Inc.,User Guide,Ver. 1.02, "Fast Fourier Transform Megacore Function",March 2001
[2]赵树杰、史林，《数字信号处理》，西安电子科技大学出版社，1997．10
[3]张澄波，《综合孔径雷达原理、系统分析与应用》，科学出版社，1989．11
[4]希尔曼，曼若斯，《雷达信息处理的理论与技术》，1987
[5]苏洪涛，《雷达脉冲压缩系统设计及实现》，西安电子科技大学硕士论文，2000年1月
[6]蔡献峰，《静止图象压缩编码技术研究》，西安电子科技大学硕士论文，1999年1月
[7]Xilinx Corporation,Logicore,"High-Performance 1024-Point Complex FFT/IFFT V.0",July 5,2000
[8]Xilinx,Inc.,Logicore,"Dual-Port Block Memory for Virtex,Virtex-Ⅱ,and Spartan-Ⅱ V3.1",March 2,2001
[9]Xilinx,Inc,"Virtex-Ⅱ 1.5V Field-Programmable Gate Arrays",April 2,2001
[10]Charles Wu SC & Marketing-TI Taiwan,Digital Processing Solutions,"Implementing the Radix-4 Decimation in Frequency(DIF)Fast Fourier Transform(FFT)Algorithm Using a TMS320C80 DSP",January 1998
[11]Nabeel Shirazi,Peter M.Athanas,and A.Lynn Abbott,Virgin Polyteclmic Institute and State University,Btadley Departmentof Electrical Engineering,"Implemen-tation of a 2-D Fast Fourier Transform on a FPGA-Based Custom Computing Machine"
[12]Optimized DSP Library for C Progreammers on the TMS320C62X,Ver 0.6 Beta,"TMS320C62x DSPLIB User's Guide",January,2000
[13]Yao-Ting Cheng,TEXAS indtruments,Application Report."Autoscaling Radix-4 FFT for TMS320C6000",March 2000
[14]B. Wei,H.Du and H.Chen,"A Complex-Number Multiplier Using Radix-4 Digits,"Proceedings of the 12th Symposium on Computer Arithmetic,1995.
[15]lan O'Donnell and Dennis Yee."FFT Implementation Exploration"
[16]Amir Said and William A.Peralman."An image multiresolution representation for lossless and lossy compression",IEEE Trans.On Image Processing.vol.5,no.9,September 1996
[17]J.Singh,A.Antoniou, and D.J.Shpak."Hardware implementtation of a wavelet based image compression coder"
[18]QuickLogic Corporation. "QuickLogic's Expanding Families of ESPs & FPGAs"
[19]Altera Inc.,data sheet,Ver.3, "Fast Fourier Transform",Oct 1997
[20]Altera Inc.,User Guide,Ver. 1.02, "Fast Fourier Transform Megacore Function",March 2001