基于FPGA硬件实现的谐波检测方法研究
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摘要
本文依据谐波检测理论,在对谐波检测实现技术进行综合分析的基础上,以高精度和高速度为目标,设计了一个高性能的谐波检测系统。文中阐述了电力系统谐波的来源、特点、分类和危害,并对当前国内外谐波检测方法及其实现技术的发展现状、存在问题和技术难点进行综述。本设计的重点是采用FPGA硬件实现傅立叶谐波检测算法。在技术上采用低通滤波器来消除频谱混叠;采用以FPGA硬件实现的数字锁相环来实现对电力系统工频信号的跟踪,以消除由于非同步采样所产生的频谱泄漏,并以尽量提高采样速率来减小“栅栏效应”对谐波测量精度的影响。另外为了进一步提高测量精度和测量速度,本设计采用6路并行16位高速A/D转换器同时对多路谐波信号进行高速高精度采样,并采用具有高并行性的256点基-4 FFT算法实现对谐波信号的分析。为了最大限度地提高谐波检测的速度,算法的实现采用并行的乘法运算单元结构和并行的存储分配方法;A/D采样控制电路、数字锁相环和基-4 FFT处理器等均用VHDL语言实现。本系统全部用MAX+plus II软件进行仿真,仿真结果表明,所设计的数字锁相环可以很好地跟踪被测信号,在模值K设为1时,对被测信号跟踪至180ms时,误差达到0.01Hz;为了方便仿真,采用16点的基-4 FFT对给定谐波数据进行运算,得到的谐波幅值和相位误差小于0.05%,运算时间仅为2.4us。
In this paper, the design of the high accuracy and speed harmonic measurement system is based on the harmonic measurement theories and the realization techniques. The sources, features, classification and harms to the power system of harmonic are summarized, as well as the development, existing problems and difficulties of the different harmonic measurement theories and realization techniques. The Fourier transform algorithm is chosen and is realized with hardware on FPGA. A low-pass filter is designed to eliminate the aliasing, and the Digital Phase Locked Logic (DPLL) is designed on FPGA to synchronize the tested signal to minish the error caused by leakage effect, while, the affect of the picket-fence effect can be minished with the increase of sample numbers. To make further, the six channels parallel 16 bits high speed A/D converter is used, and the 256-point radix-4 FFT is used to compute the harmonic data. The multiplication cells and the storage design of radix-4 FFT are highly parallelized to farthest improve the speed of harmonic measurement. The A/D sampling and control logic, the DPLL and the radix-4 FFT and etc. are designed with VHDL and simulated with MAX+plusⅡsoftware. The simulation result shows that the designed DPLL hardware is good for tracking the tested signal. With the K value is set as 1, an error only of 0.01% is caused at 180ms. And for simulation simplicity, the 16-point radix-4 FFT is simulated, which causes an error less than 0.05%, and takes only 2.4us.
引文
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