0.25μm CMOS工艺中ESD关键技术研究
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摘要
随着集成电路的特征尺寸的缩小以及先进工艺技术的不断涌现,芯片往往会产生一些可靠性方面的问题,也使得原本具有较好性能的静电防护结构的防护能力大打折扣。在设计一款DSP(Digital Signal Processor)芯片时,为了缩短设计周期,采用了一种简单而常见的标准单元结构作为此芯片IO电路和静电防护电路。此IO标准单元能满足不同输出驱动电流的要求,但在静电防护方面却存在致命的缺陷,致使这个芯片的防护能力大幅下降。为了给该DSP芯片提供更好的静电防护,现需要对此IO标准单元结构进行优化,或采取更优秀的静电防护结构。论文研究了常见的各种ESD防护结构的同时,针对Chartered 0.25μm CMOS工艺,对原来的IO标准单元结构进行优化设计。设计方案结合了动态浮接栅耦合结构专利的优点,并实现了IO标准单元中的输出结构和静电防护结构相分离,并设计出同时具有栅耦合结构和衬底触发结构优点的静电防护单元。另外,还采用了一些关键的版图设计,有效降低了静电防护结构的触发电压和箝位电压,并获得了更好的均匀触发特性。最终的HBM模型静电放电测试结果表明,此防护结构的HBM模型的全芯片防护能力达到4kV,并已经成功应用于此款DSP芯片。
As the technology scaled down, some advanced process technologies have been developed to ensure better performance, which also cause some reliability problems to chip, especially cause a strong negative effect on the robustness of electrostatic discharge protection circuit, which is used to be effective for chip.
While design the input/output and ESD protection circuits of a DSP(digital signal processing) chip, a standard input/output cell, which could satisfy the different driven current requirement, is adopted to decrease the design period. While testing, this cell only bypasses lower ESD current and then fails. For increasing the ESD robustness of the DSP IC, the prior standard input/output should be optimized, or a new efficient ESD protection structure should be used. In this paper, several common ESD protection structure and Dynamic-Floating-Gate-Couple structure patent are investigated. Based on Chartered 0.25μm CMOS technology, an optimized protection circuit structure is developed, which absorb the advantage of the patent. This ESD protection structure has the advantage of both gate couple NMOS structure and substrate triggering NMOS structure, and uses a poly resistor to divide the output buffer circuit and ESD circuit to provide efficient protection for the output circuit. Some critical layout design is provided to ensure lower trigger/clamp voltage and uniform current distribution. The optimized ESD protection circuit has passed the 4kV HBM(Human Body Model) test under all test condition, and it has been applied in the DSP chip successfully.
As the technology scaled down, some advanced process technologies have been developed to ensure better performance, which also cause some reliability problems to chip, especially cause a strong negative effect on the robustness of electrostatic discharge protection circuit, which is used to be effective for chip.
While design the input/output and ESD protection circuits of a DSP(digital signal processing) chip, a standard input/output cell, which could satisfy the different driven current requirement, is adopted to decrease the design period. While testing, this cell only bypasses lower ESD current and then fails. For increasing the ESD robustness of the DSP IC, the prior standard input/output should be optimized, or a new efficient ESD protection structure should be used. In this paper, several common ESD protection structure and Dynamic-Floating-Gate-Couple structure patent are investigated. Based on Chartered 0.25μm CMOS technology, an optimized protection circuit structure is developed, which absorb the advantage of the patent. This ESD protection structure has the advantage of both gate couple NMOS structure and substrate triggering NMOS structure, and uses a poly resistor to divide the output buffer circuit and ESD circuit to provide efficient protection for the output circuit. Some critical layout design is provided to ensure lower trigger/clamp voltage and uniform current distribution. The optimized ESD protection circuit has passed the 4kV HBM(Human Body Model) test under all test condition, and it has been applied in the DSP chip successfully.
引文
[1] C. Duvvury and A. Amerasekera, ESD: a pervasive reliability concern for IC technologies, Proc. IEEE, 81, 690–702, 1993.
[2] H. Hill and D.P. Renaud, ESD in semiconductor wafer processing, Proceedings of the 7th EOS/ESD Symposium, pp. 6–9, 1985.
[3] R. G. Wagner, J. M. Soden, and C. F. Hawkins, Extent and cost of EOS/ESD damage in an IC manufacturing process, Proc. EOS/ESD Symp., vol. EOS-15, pp. 49–55. Sept, 1993.
[4] C. Duvvury and R.N. Rountree and L.S. White, A summary of most effective electrostatic protection circuits for MOS memories and their observed failure modes, Proc. 5th EOS/ESD Symposium, pp. 181–184, 1983.
[5] H. Weston, V. Lee and T. Stanik, A newly observed high frequency effect on the ESD protection utilized in a gigahertz NMOS technology, Proc. 14th EOS/ESD Symposium, pp. 95–98, 1992.
[6] R. McPhee, C. Duvvury, R. Rountree and H. Domingos, Thick oxide ESD performance under process variations, Proc. 8th EOS/ESD Symposium, pp. 173–179, 1986.
[7] C. Duvvury, R. Rountree and D. Baglee, A. Hyslop, L. White, ESD design considerations for ULSI, Proc. 7th EOS/ESD Symposium, pp. 45–48, 1985.
[8] C. Duvvury, R. McPhee, D. Baglee, and R. Rountree, ESD protection reliability in 1-μm CMOS circuit performance, Proc. 24th IRPS, pp. 199–208, 1986.
[9] D. Wilson, H. Domingos and M.M.S. Hassan, Electrical overstress in nMOS silicided devices, Proc. 9th EOS/ESD Symposium, pp. 265–273, 1987.
[10] A. Chatterjee, J.A. Seitchik, J.-H. Chern, P. Wang and C.-C. Wei, Direct evidence supporting the premises of a two-dimensional diode model for the parasitic thyristor in CMOS circuits built on thin Epi, IEEE Electr. Device Lett., EDL-9, 509–511, 1988.
[11] C. Russ, M. Mergens, J. Armer, C. Jozwiak, G. Kolluri, L. Avery and K. Verhaege, GGSCRs: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submicron CMOS processes, Proc. 23rd EOS/ESD Symposium, pp. 22–31, 2001.
[12] K. Kunz, C. Duvvury and H. Shichijo, 5-Volt tolerant fail-safe ESD solutions for a 0.18μm logic CMOS process, Proc. 23rd EOS/ESD Symposium, pp. 12–21, 2001.
[13] A. Chatterjee, T. Polgreen and A. Amerasekera, Design and simulation of a 4 kV ESD protection circuit, in Tech. Dig. IEDM, 913–916, 1991.
[14] C. Duvvury and C. Diaz, Dynamic gate coupling of NMOS for efficient output ESD protection, IPRS pp.141-150, 1992
[15] K-L. Chen, Effect of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistors, Proc. 10th EOS/ESD Symposium, pp. 212–219, 1988.
[16] T. Polgreen and A. Chatterjee, Improving the ESD failure threshold of silicided NMOS output transistors by ensuring uniform current flow, Proc. 11th EOS/ESD Symposium, pp. 167–174, 1989.
[17] J.Z. Chen, A. Amerasekera and C. Duvvury, Design methodology for optimizing gate driven ESD protection circuits in submicron CMOS processes, Proc. 19th EOS/ESD Symposium, pp. 230–239, 1997.
[18] C. Duvvury, S. Ramaswamy, A. Amerasekera et al, Substrate pump NMOS for ESD protection applications, in Proc. EOS/ESD Symposium, 2000.
[19] A. Amerasekera, C. Duvvury, ESD in silicon integrated circuits, 2nd Edition, pp. 394-399, 2002
[20] ESD Association WG 5.1, ESD STM5.1-2001: standard test method for electrostatic discharge sensitivity testing-Human Body Model (HBM) component level”, 2001.
[21] JEDEC Solid State Technology Association, JESD22-A114-B: Electrostatic Discharge (ESD) sensitivity testing Human Body Model (HBM), 2000.
[22] ESD Association WG 5.2, ESD TR 10-00: Machine Model(MM) Electrostatic Discharge (ESD) investigation—reduction in pulse number and delay time, 2000.
[23] JEDEC Solid State Technology Association, JESD22-A115-A: Electrostatic Discharge (ESD) sensitivity testing Machine Model (MM), 1997.
[24] JEDEC Solid State Technology Association, JESD22-C101-A: field-induced Charged Device Model test method for Electrostatic discharge-withstand thresholds of microelectronic components, 2000.
[25] Ming-Dou Ker, http://www.ics.ee.nctu.edu.tw/~mdker/ESD/index.html.
[26] G. Notermans, P. de Jong and F. Kuper, Pitfalls when correlating TLP, HBM and MM testing, Proc. 20th EOS/ESD Symposium, ESD Association, Rome, NY, USA, pp. 170–176, 1998.
[27] H. Gieser, Verfahren zur Charakterisierung von integrierten Schaltungen mit sehr schnellen Hochstromimpulsen (Methods for the characterization of integratedcircuits employing very fast high current impulses), Dissertation Technische Universitaet Muenchen TUM, Shaker-Verlag, Aachen, Germany, 1999.
[28] E.A. Amerasekera, W. van den Abeelen, L.J. van Roozendaal et al, ESD failure modes: characteristics, mechanisms and process influences, IEEE T. Electron Dev., ED-39, 2, 1992.
[29] E.R. Knight and P.P. Budenstein, Effect of junction spikes and doping level on the second breakdown susceptibility of silicon-on-sapphire diodes, Proceedings of the 2nd EOS/ESD Symposium, pp. 122–129, 1980.
[30] S. Aur, A. Chatterjee and T. Polgreen, Hot electron reliability and ESD latent damage, IEEE T. Electron Dev., ED-35, 2189–2193, 1988.
[31] J. Colvin, The identification and analysis of latent ESD damage on CMOS input gates, Proceedings of the 15th EOS/ESD Symposium, pp. 109–116, 1993.
[32] J. Wu, P. Juliano and E. Rosenbaum, Breakdown and latent damage of ultrathin gate oxides under ESD stress conditions, in Proceedings of the 22nd EOS/ESD Symposium, pp. 287–295, 2000.
[33] S.C. Thierauf and W.R. Anderson, I/O and ESD circuit design in A. Chandrakasan, W.J. Bowhill and F. Fox, eds., Design of High-Performance Microprocessor Circuits, IEEE Press, pp. 377–396, 2001.
[34] Louis Luh, John Choma, and Jeffrey Draper, A zener-diode-activated ESD protection circuit for sub-micron CMOS process, IEEE, pp. 65-68, 2000.
[35] Ming-Dou Ker and Wen-Yu Lo, Design on the low-leakage diode string for using in the power-rail ESD clamp circuit in a 0.35-μm silicide CMOS process, IEEE, pp. 601-611, 2000.
[36]刘永,张福海,晶体管原理,北京国防工业出版社,p59-144,2002。
[37] V. Vassilev, G. Groeseneken, M. Steyaert and H. Maes, Dynamic substrate resistance snapback triggering of ESD protection devices, IEEE, pp. 256-260, 2003.
[38] USPATENT 5,631,793, Ming-Dou Ker, Chung-Yu Wu, Tao Cheng et al, Capacitor-couple electrostatic discharge protection Circuit, May. 20, 1997.
[39] M.-D. Ker, T.-Y. Chen, and C.-Y. Wu, Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC’s with substrate-triggering technique, Proc. of IEEE Int. ASIC Conf. and Exhibit, pp. 287-290, 1997.
[40] Ming-Dou Ker, Hun-Hsien chang and Chung-Yu Wu, A gated-couple PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC’s, IEEE, pp.38-51, 1997.
[41] USPATENT 5,086,365, Cheun-Der Lien, Mountain View and Calif, Electrostatic discharge protection circuit, Feb. 4 1992.
[42] USPATENT 6,034,552, Hun-hsin Chang, Ming-Dou Ker and Kuo-Tsai Lee, Output ESD protection using dynamic-floating-gate arrangement, Mar. 7, 2000.
[43] Che-Hao Chuang and Ming-Dou Ker, Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-μm CMOS technology, ISCAS, pp. 577-580, 2004.
[44] M.-D. Ker and Wen-Yu Lo, Design on the low-leakage diode string for using in the power-rail ESD Clamp Circuits in a 0.35μm Silicide CMOS Process, IEEE Trans on Solid-State Circuits, pp. 601-611, 2000.
[45] Kwang-Hoon Oh, Charvaka duvvury, Kaustav Banerjee et al, Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors, IEEE Transactions on Electron Devices, pp. 2171-2182, 2002.
[46] Ming-Dou Ker, Chung-Yu Wu, Tain-Shun Wu, Area-efficient layout design for CMOS output transistors, IEEE Transactions on Electron Devices, pp. 635-645, 1997.
[47] Ming-Dou Ker and Shih-Lun Chen, Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3*VDD devices and single VDD supply, IEEE International Solid-State Circuits Conference, pp. 524-525, 2005.
[48] Ming-Dou Ker and Jia-Huei Chen, Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices,IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2601-2609. 2006.
[49] Ming-Dou Ker, Shih-Hung Chen and Che-Hao Chuang, ESD failure mechanisms of analog I/O cells in 0.18-μm CMOS technolgy, IEEE Transactions on Device and Meterials Reliability, vol. 6, no.1 pp. 102-111, 2006.
[50] Ming-Dou Ker, Wei-Jen Chang, Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology, Microelectronics Reliability, pp. 27-35, 2007.
[2] H. Hill and D.P. Renaud, ESD in semiconductor wafer processing, Proceedings of the 7th EOS/ESD Symposium, pp. 6–9, 1985.
[3] R. G. Wagner, J. M. Soden, and C. F. Hawkins, Extent and cost of EOS/ESD damage in an IC manufacturing process, Proc. EOS/ESD Symp., vol. EOS-15, pp. 49–55. Sept, 1993.
[4] C. Duvvury and R.N. Rountree and L.S. White, A summary of most effective electrostatic protection circuits for MOS memories and their observed failure modes, Proc. 5th EOS/ESD Symposium, pp. 181–184, 1983.
[5] H. Weston, V. Lee and T. Stanik, A newly observed high frequency effect on the ESD protection utilized in a gigahertz NMOS technology, Proc. 14th EOS/ESD Symposium, pp. 95–98, 1992.
[6] R. McPhee, C. Duvvury, R. Rountree and H. Domingos, Thick oxide ESD performance under process variations, Proc. 8th EOS/ESD Symposium, pp. 173–179, 1986.
[7] C. Duvvury, R. Rountree and D. Baglee, A. Hyslop, L. White, ESD design considerations for ULSI, Proc. 7th EOS/ESD Symposium, pp. 45–48, 1985.
[8] C. Duvvury, R. McPhee, D. Baglee, and R. Rountree, ESD protection reliability in 1-μm CMOS circuit performance, Proc. 24th IRPS, pp. 199–208, 1986.
[9] D. Wilson, H. Domingos and M.M.S. Hassan, Electrical overstress in nMOS silicided devices, Proc. 9th EOS/ESD Symposium, pp. 265–273, 1987.
[10] A. Chatterjee, J.A. Seitchik, J.-H. Chern, P. Wang and C.-C. Wei, Direct evidence supporting the premises of a two-dimensional diode model for the parasitic thyristor in CMOS circuits built on thin Epi, IEEE Electr. Device Lett., EDL-9, 509–511, 1988.
[11] C. Russ, M. Mergens, J. Armer, C. Jozwiak, G. Kolluri, L. Avery and K. Verhaege, GGSCRs: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submicron CMOS processes, Proc. 23rd EOS/ESD Symposium, pp. 22–31, 2001.
[12] K. Kunz, C. Duvvury and H. Shichijo, 5-Volt tolerant fail-safe ESD solutions for a 0.18μm logic CMOS process, Proc. 23rd EOS/ESD Symposium, pp. 12–21, 2001.
[13] A. Chatterjee, T. Polgreen and A. Amerasekera, Design and simulation of a 4 kV ESD protection circuit, in Tech. Dig. IEDM, 913–916, 1991.
[14] C. Duvvury and C. Diaz, Dynamic gate coupling of NMOS for efficient output ESD protection, IPRS pp.141-150, 1992
[15] K-L. Chen, Effect of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistors, Proc. 10th EOS/ESD Symposium, pp. 212–219, 1988.
[16] T. Polgreen and A. Chatterjee, Improving the ESD failure threshold of silicided NMOS output transistors by ensuring uniform current flow, Proc. 11th EOS/ESD Symposium, pp. 167–174, 1989.
[17] J.Z. Chen, A. Amerasekera and C. Duvvury, Design methodology for optimizing gate driven ESD protection circuits in submicron CMOS processes, Proc. 19th EOS/ESD Symposium, pp. 230–239, 1997.
[18] C. Duvvury, S. Ramaswamy, A. Amerasekera et al, Substrate pump NMOS for ESD protection applications, in Proc. EOS/ESD Symposium, 2000.
[19] A. Amerasekera, C. Duvvury, ESD in silicon integrated circuits, 2nd Edition, pp. 394-399, 2002
[20] ESD Association WG 5.1, ESD STM5.1-2001: standard test method for electrostatic discharge sensitivity testing-Human Body Model (HBM) component level”, 2001.
[21] JEDEC Solid State Technology Association, JESD22-A114-B: Electrostatic Discharge (ESD) sensitivity testing Human Body Model (HBM), 2000.
[22] ESD Association WG 5.2, ESD TR 10-00: Machine Model(MM) Electrostatic Discharge (ESD) investigation—reduction in pulse number and delay time, 2000.
[23] JEDEC Solid State Technology Association, JESD22-A115-A: Electrostatic Discharge (ESD) sensitivity testing Machine Model (MM), 1997.
[24] JEDEC Solid State Technology Association, JESD22-C101-A: field-induced Charged Device Model test method for Electrostatic discharge-withstand thresholds of microelectronic components, 2000.
[25] Ming-Dou Ker, http://www.ics.ee.nctu.edu.tw/~mdker/ESD/index.html.
[26] G. Notermans, P. de Jong and F. Kuper, Pitfalls when correlating TLP, HBM and MM testing, Proc. 20th EOS/ESD Symposium, ESD Association, Rome, NY, USA, pp. 170–176, 1998.
[27] H. Gieser, Verfahren zur Charakterisierung von integrierten Schaltungen mit sehr schnellen Hochstromimpulsen (Methods for the characterization of integratedcircuits employing very fast high current impulses), Dissertation Technische Universitaet Muenchen TUM, Shaker-Verlag, Aachen, Germany, 1999.
[28] E.A. Amerasekera, W. van den Abeelen, L.J. van Roozendaal et al, ESD failure modes: characteristics, mechanisms and process influences, IEEE T. Electron Dev., ED-39, 2, 1992.
[29] E.R. Knight and P.P. Budenstein, Effect of junction spikes and doping level on the second breakdown susceptibility of silicon-on-sapphire diodes, Proceedings of the 2nd EOS/ESD Symposium, pp. 122–129, 1980.
[30] S. Aur, A. Chatterjee and T. Polgreen, Hot electron reliability and ESD latent damage, IEEE T. Electron Dev., ED-35, 2189–2193, 1988.
[31] J. Colvin, The identification and analysis of latent ESD damage on CMOS input gates, Proceedings of the 15th EOS/ESD Symposium, pp. 109–116, 1993.
[32] J. Wu, P. Juliano and E. Rosenbaum, Breakdown and latent damage of ultrathin gate oxides under ESD stress conditions, in Proceedings of the 22nd EOS/ESD Symposium, pp. 287–295, 2000.
[33] S.C. Thierauf and W.R. Anderson, I/O and ESD circuit design in A. Chandrakasan, W.J. Bowhill and F. Fox, eds., Design of High-Performance Microprocessor Circuits, IEEE Press, pp. 377–396, 2001.
[34] Louis Luh, John Choma, and Jeffrey Draper, A zener-diode-activated ESD protection circuit for sub-micron CMOS process, IEEE, pp. 65-68, 2000.
[35] Ming-Dou Ker and Wen-Yu Lo, Design on the low-leakage diode string for using in the power-rail ESD clamp circuit in a 0.35-μm silicide CMOS process, IEEE, pp. 601-611, 2000.
[36]刘永,张福海,晶体管原理,北京国防工业出版社,p59-144,2002。
[37] V. Vassilev, G. Groeseneken, M. Steyaert and H. Maes, Dynamic substrate resistance snapback triggering of ESD protection devices, IEEE, pp. 256-260, 2003.
[38] USPATENT 5,631,793, Ming-Dou Ker, Chung-Yu Wu, Tao Cheng et al, Capacitor-couple electrostatic discharge protection Circuit, May. 20, 1997.
[39] M.-D. Ker, T.-Y. Chen, and C.-Y. Wu, Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC’s with substrate-triggering technique, Proc. of IEEE Int. ASIC Conf. and Exhibit, pp. 287-290, 1997.
[40] Ming-Dou Ker, Hun-Hsien chang and Chung-Yu Wu, A gated-couple PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC’s, IEEE, pp.38-51, 1997.
[41] USPATENT 5,086,365, Cheun-Der Lien, Mountain View and Calif, Electrostatic discharge protection circuit, Feb. 4 1992.
[42] USPATENT 6,034,552, Hun-hsin Chang, Ming-Dou Ker and Kuo-Tsai Lee, Output ESD protection using dynamic-floating-gate arrangement, Mar. 7, 2000.
[43] Che-Hao Chuang and Ming-Dou Ker, Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-μm CMOS technology, ISCAS, pp. 577-580, 2004.
[44] M.-D. Ker and Wen-Yu Lo, Design on the low-leakage diode string for using in the power-rail ESD Clamp Circuits in a 0.35μm Silicide CMOS Process, IEEE Trans on Solid-State Circuits, pp. 601-611, 2000.
[45] Kwang-Hoon Oh, Charvaka duvvury, Kaustav Banerjee et al, Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors, IEEE Transactions on Electron Devices, pp. 2171-2182, 2002.
[46] Ming-Dou Ker, Chung-Yu Wu, Tain-Shun Wu, Area-efficient layout design for CMOS output transistors, IEEE Transactions on Electron Devices, pp. 635-645, 1997.
[47] Ming-Dou Ker and Shih-Lun Chen, Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3*VDD devices and single VDD supply, IEEE International Solid-State Circuits Conference, pp. 524-525, 2005.
[48] Ming-Dou Ker and Jia-Huei Chen, Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices,IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2601-2609. 2006.
[49] Ming-Dou Ker, Shih-Hung Chen and Che-Hao Chuang, ESD failure mechanisms of analog I/O cells in 0.18-μm CMOS technolgy, IEEE Transactions on Device and Meterials Reliability, vol. 6, no.1 pp. 102-111, 2006.
[50] Ming-Dou Ker, Wei-Jen Chang, Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology, Microelectronics Reliability, pp. 27-35, 2007.