2.7GHz高速接口电路的ESD电路设计及仿真分析
摘要
随着技术的进步,工艺的改进,一方面集成电路的集成度越来越高,另一方面芯片之间数据传输的速度也越来越快。工艺的进步,使得芯片的尺寸越来越小,介质氧化层越来越薄,结深越来越浅,而静电并不会因为这些改变而减弱,从而会造成芯片承受静电的能力越来越差。在每年失效的大量芯片中,由静电放电所引起的占据了一半的比例。因此集成电路的可靠性在很大程度上依赖于静电放电保护电路的性能。对于深亚微米的集成电路设计来说,设计出有效的ESD保护电路变得尤为重要。
半导体器件的制造和芯片级的测试,极大程度上依赖于精密的设备。众所周知,微电子行业的相关设备价格昂贵,测试需要的各种损耗品也价格不菲,而借助软件对器件进行模拟分析,可以快速精确的得到器件的各种性能,而且可以对器件结构进行优化,以获得更加理想的特性,从而降低研发费用。常用的有电路级仿真工具Hspice和器件级仿真工具MEDICI。
基于高速串行SerDes接口,设计出了具有高速性能的ESD保护电路。采用台积电(TSMC)0.13μm工艺,实现了一种既能满足2.7Gbps高速的要求,又能满足耐压达2000V的ESD保护电路。在设计中对于高速的要求是通过建立Hspice模型,使用Hspice在正常输入信号的情况下进行仿真,在高速方面得到了理想的结果;对于耐压的要求,则是通过二维器件仿真工具MEDICI从器件角度来仿真验证的。通过建立器件模型,并对器件模型进行优化,对于人体模型达到了耐压2000V的要求。
本文设计的ESD保护电路既实现了2.7Gbps的高速要求,也实现了耐压2000V的要求,满足了芯片正常的使用的要求。
With the development of technology and improvement of process, on the one hand, the integrated level of ICs becomes higher and higher; on the other hand, the data rate between chips becomes faster and faster .The advancement of progress leads to smaller chips, thinner gate oxide, shallower junction depth.Unfortunately ,the electrostatic will not be weakened because of these changes.As a result,the ablitity of electrostatic that Ics should bare is getting worse.We can see from the statistics,the proportion of failure chips caused by electrostatic in a large number of chips per year accounted for half of the ratio. Therefore, the reliability of integrated circuits is heavily depend on the performance of ESD protection circuits. For deep sub-micron integrated circuit design, the design of effective ESD protection circuit has becomes particularly significant.
The manufacture of semiconductor devices and chip-level testing are greatly depend on sophisticated equipment, we all know, the microelectronics industry-related equipments are too expensive,and the loss products that testing should need are also too expensive, so we can emply software to simulate and analyse the devices and circuits, As a result,the various paraters of the device properties can be quickly and accurately acquired.Furthermore,we can optimize the device structure to obtain more desirable properties,witch can reduce development costs. Commonly used circuit-level simulation tools and device-level simulation tools are Hspice and MEDICI.
Based on the design of high-speed SerDes interface, the ESD protection circuit with high performance is designed. The protection circuit based on TSMC (TSMC) 0.13μm process,the ESD protection circuit whitch can meet needs for both 2.7Gbps high speed and 2000V breakdown voltage.In the design requirements for high speed through the establishment of Hspice model, its simulation using Hspice, including the normal input signal as well as an example to 2000V Human Body Model simulation, the ideal high-speed aspects of the results obtained. As for breakdown voltage it is using the two-dimensional device simulation tool MEDICI to simulate from the perspective of the device, through the establishment and optimiztion of the device model,2000V breakdown voltage of human body model has been achieved.
Above all,the ESD protection circuit design not only achieve 2.7Gbps high-speed requirements, but also meets the requirement of 2000V breakdown voltage.
半导体器件的制造和芯片级的测试,极大程度上依赖于精密的设备。众所周知,微电子行业的相关设备价格昂贵,测试需要的各种损耗品也价格不菲,而借助软件对器件进行模拟分析,可以快速精确的得到器件的各种性能,而且可以对器件结构进行优化,以获得更加理想的特性,从而降低研发费用。常用的有电路级仿真工具Hspice和器件级仿真工具MEDICI。
基于高速串行SerDes接口,设计出了具有高速性能的ESD保护电路。采用台积电(TSMC)0.13μm工艺,实现了一种既能满足2.7Gbps高速的要求,又能满足耐压达2000V的ESD保护电路。在设计中对于高速的要求是通过建立Hspice模型,使用Hspice在正常输入信号的情况下进行仿真,在高速方面得到了理想的结果;对于耐压的要求,则是通过二维器件仿真工具MEDICI从器件角度来仿真验证的。通过建立器件模型,并对器件模型进行优化,对于人体模型达到了耐压2000V的要求。
本文设计的ESD保护电路既实现了2.7Gbps的高速要求,也实现了耐压2000V的要求,满足了芯片正常的使用的要求。
With the development of technology and improvement of process, on the one hand, the integrated level of ICs becomes higher and higher; on the other hand, the data rate between chips becomes faster and faster .The advancement of progress leads to smaller chips, thinner gate oxide, shallower junction depth.Unfortunately ,the electrostatic will not be weakened because of these changes.As a result,the ablitity of electrostatic that Ics should bare is getting worse.We can see from the statistics,the proportion of failure chips caused by electrostatic in a large number of chips per year accounted for half of the ratio. Therefore, the reliability of integrated circuits is heavily depend on the performance of ESD protection circuits. For deep sub-micron integrated circuit design, the design of effective ESD protection circuit has becomes particularly significant.
The manufacture of semiconductor devices and chip-level testing are greatly depend on sophisticated equipment, we all know, the microelectronics industry-related equipments are too expensive,and the loss products that testing should need are also too expensive, so we can emply software to simulate and analyse the devices and circuits, As a result,the various paraters of the device properties can be quickly and accurately acquired.Furthermore,we can optimize the device structure to obtain more desirable properties,witch can reduce development costs. Commonly used circuit-level simulation tools and device-level simulation tools are Hspice and MEDICI.
Based on the design of high-speed SerDes interface, the ESD protection circuit with high performance is designed. The protection circuit based on TSMC (TSMC) 0.13μm process,the ESD protection circuit whitch can meet needs for both 2.7Gbps high speed and 2000V breakdown voltage.In the design requirements for high speed through the establishment of Hspice model, its simulation using Hspice, including the normal input signal as well as an example to 2000V Human Body Model simulation, the ideal high-speed aspects of the results obtained. As for breakdown voltage it is using the two-dimensional device simulation tool MEDICI to simulate from the perspective of the device, through the establishment and optimiztion of the device model,2000V breakdown voltage of human body model has been achieved.
Above all,the ESD protection circuit design not only achieve 2.7Gbps high-speed requirements, but also meets the requirement of 2000V breakdown voltage.
引文
[1] USPATENT 6,034,552,Hun-hsin Chang,Ming-Dou Ker and Kuo-Tsai Lee,Output ESD protection using dynamic-floating-gate arrangement,Mar.7,2000:76-78.
[2] C.Duvvury,R.Rountree and D.Baglee,A. Hyslop,L. White,ESD design consider for ULSI,Proc. 7th EOS/ESD Symposium,1985:45-48.
[3] R.G. Wagner, J. M. Soden, and C. F. Hawkins, Extent and cost of EOS/ESD damage in an IC manufacturing process, Proc. EOS/ESD Symp. Vol. EOS-15, 1993:49-55.
[4] C. Duvvury and R. N. Rountree and L.S. White, A summary of most effective electrostatic protection circuits for MOS memories and their observed failure modes, Proc. 5th EOS/ESD Symposium, 1983:181-184.
[5] C. Duvvury, R. McpPHee, D. Baglee, and R. Rountree, ESD protection reliability in 1-um CMOS circuit performance, Proc. 24th IRPS, 1986:199-208.
[6] A. Chatterjee, J.A. Seitchik, J.-H. Chern, P. Wang and C.-C. Wei, Direct evidence supporting the premises of a two-dimensional diode model for the parasitic thyristor in CMOS citcuits built on thin Epi, IEEE Electr. Device Lett, EDL-9,1988:509-511.
[7] A Amerasekera,C Duvvury,V Reddy,et a1.Substrate Triggering and Silicide Effects on ESD Performance and Protection Circuit Design in Deep submicron CMOS Processes,Tcch.Dig.IEDM,1995:547-550.
[8] H.Gieser,Verfahren ZUl"Charakterisienmg von integrierten Schaltungen mit sehr schnellen Hochstromimpulsen(Methods for the characterization of integrated circuits employing very fast high current impulses),Dissertation Technische Universitaet Muenchen TUM,Shaker-Verlag,Aachen,Germany 1999:59-66.
[9] Louis Luh-John Choma,and Jeffrey Draper,A zener-diode-activated ESD protection circuit for sub-micron CMOS process,IEEE,2000:65-68.
[10] V.Vassilev,G.Groeseneken,M.Steyaert and H.Maes,Dynamic substrate resistance snapback triggering of ESD protection devices,IEEE,2003:256-260.
[11] Louis Luh-John Choma,and Jeffrey Draper,A zener-diode-activated ESD protection circuit for sub-micron CMOS process,IEEE,2000:65-68.
[12] Ming-Dou Ker,http://twww.ics.ce.nem.edu.tw/-mdker/ESD/index.html.
[13] M.-D.Ker,T.-Y.Chen,and C.-Y.WU Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC’with substrate-triggering technique,Proc.of IEEE Int.ASIC Cone and Exhibit,PP.287-290,1 997.
[14] C.Duvvury,S.Ramaswamy,A.Amerasekera et al,Substrate pump NMOS for ESD protection applications,in Proc.EOS/ESD Symposium,2000:122-126.
[15] Ming-Dou Ker and Jia-Huei Chen,Self-substrate-triggered technique to enhance trim-on uniformity ofmulti-finger ESD protection devices , IEEE Journal ofSolid-State Circuits,v01.41,no.1 1,PP.2006:2601-2609.
[16] C.Russ,M.Mergens,J.An-her,C.Jozwiak,G.Kolluri,L.Avery and k Verhaege, GGSCRs :GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submieron CMOS processes,Proc.23rd EOS/ESD Symposium,2001:22-31.
[17] k Kunz,C.Duvvury and H.Shichijo,5-Volt tolerant fail-safe ESD solutions for a O.1 89m logic CMOS process,Proc.23rd EOS/ESD Symposium,2001:.12-21.
[18] A.Chatterjee,T.Polgrcen and A.Amcrasekera,Design and simulation of a 4 kV ESD protection circuit,in Tech.Dig.IEDM,1991:913-916.
[19] Ming-Dou Ker,Hun-Hsien chang and Chung-Yu Wu,A gated-couple PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC’S,IEEE,1997:38-51.
[20] Sten Hellstr6m,ESD:”The Scourge of Electronics,Berlin;NewYork”:Springer.1998.
[21]马晓慧.多电源和多地的片上ESD保护.半导体技术,2010:26(10)25-26.
[22] MIL-STD-883E, Methode 3015.7, Electrostatic Discharge Sensitivity Classification, Dept. of Defence, Test Method Standard, microcircuits, 1989:99-102.
[23] ESDSTM5.1-1998 Revised, Electrostatic Discharge Sensitivity Testing-Human Body Model Component Level, the ESD Association, 1998:65-70.
[24] JEDEC JESD22-A114-B, Electrostatic Discharge Sensitivity Testing Human Body Model, the Electronics Industries Alliance, June 2000:57-60.
[25] AEC-Q100-002 Rev-C, Human Body Model Electrostatic Discharge Test, the Automotive Electronics Council, October 1998:57-66.
[26] ESD STM5.2-1999 Revised, Electrostatic Discharge Sensitivity Testing-Machine Model Component Level, the ESD Association, 1999:87-92.
[27] JEDEC JESD22-A115-A, Electrostatic Discharge Sensitivity Testing Machine Model, the Electronics Industries Alliance, October 1997:22-28.
[28] AEC-Q100-003 Rev-E, Machine Model Electrostatic Discharge Test, the AutomotiveElectronics Council, January 2001:43-45.
[29] ESD STM5.3.1-1999 Revised, Electrostatic Sensitivity Testing-Charged Device Model Component Level, the ESD Association, 1999:23-31.
[30] ESD STM5.3.1-1999 Revised, Electrostatic Sensitivity Testing-Charged Device Model Component Level, the ESD Association, 1999:34-39.
[31] JEDEC JESD22-C101-A, Field-Induced Charged-Device Model test Method for Electrostatic Discharge-Withstand Thresholds of Microelectronic Components, the Electronics Industries Alliance, June 2000:66-70.
[32] AEC-Q100-011 Rev-A, Charged-Device Model Electrostatic Discharge Test, the Automotive Electronics Council, January 2001:44-47.
[33] Ming-Dou Ker "ESD (Electrostatic Discharge) Protection in CMOS Integrated Circuits"
[34] S Mallat, Z Zhang. Maching Pursuit Time-freqency Distributions. IEEE Trans.Signal Processing,1993,41(12):3397-3415. ?
[2] C.Duvvury,R.Rountree and D.Baglee,A. Hyslop,L. White,ESD design consider for ULSI,Proc. 7th EOS/ESD Symposium,1985:45-48.
[3] R.G. Wagner, J. M. Soden, and C. F. Hawkins, Extent and cost of EOS/ESD damage in an IC manufacturing process, Proc. EOS/ESD Symp. Vol. EOS-15, 1993:49-55.
[4] C. Duvvury and R. N. Rountree and L.S. White, A summary of most effective electrostatic protection circuits for MOS memories and their observed failure modes, Proc. 5th EOS/ESD Symposium, 1983:181-184.
[5] C. Duvvury, R. McpPHee, D. Baglee, and R. Rountree, ESD protection reliability in 1-um CMOS circuit performance, Proc. 24th IRPS, 1986:199-208.
[6] A. Chatterjee, J.A. Seitchik, J.-H. Chern, P. Wang and C.-C. Wei, Direct evidence supporting the premises of a two-dimensional diode model for the parasitic thyristor in CMOS citcuits built on thin Epi, IEEE Electr. Device Lett, EDL-9,1988:509-511.
[7] A Amerasekera,C Duvvury,V Reddy,et a1.Substrate Triggering and Silicide Effects on ESD Performance and Protection Circuit Design in Deep submicron CMOS Processes,Tcch.Dig.IEDM,1995:547-550.
[8] H.Gieser,Verfahren ZUl"Charakterisienmg von integrierten Schaltungen mit sehr schnellen Hochstromimpulsen(Methods for the characterization of integrated circuits employing very fast high current impulses),Dissertation Technische Universitaet Muenchen TUM,Shaker-Verlag,Aachen,Germany 1999:59-66.
[9] Louis Luh-John Choma,and Jeffrey Draper,A zener-diode-activated ESD protection circuit for sub-micron CMOS process,IEEE,2000:65-68.
[10] V.Vassilev,G.Groeseneken,M.Steyaert and H.Maes,Dynamic substrate resistance snapback triggering of ESD protection devices,IEEE,2003:256-260.
[11] Louis Luh-John Choma,and Jeffrey Draper,A zener-diode-activated ESD protection circuit for sub-micron CMOS process,IEEE,2000:65-68.
[12] Ming-Dou Ker,http://twww.ics.ce.nem.edu.tw/-mdker/ESD/index.html.
[13] M.-D.Ker,T.-Y.Chen,and C.-Y.WU Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC’with substrate-triggering technique,Proc.of IEEE Int.ASIC Cone and Exhibit,PP.287-290,1 997.
[14] C.Duvvury,S.Ramaswamy,A.Amerasekera et al,Substrate pump NMOS for ESD protection applications,in Proc.EOS/ESD Symposium,2000:122-126.
[15] Ming-Dou Ker and Jia-Huei Chen,Self-substrate-triggered technique to enhance trim-on uniformity ofmulti-finger ESD protection devices , IEEE Journal ofSolid-State Circuits,v01.41,no.1 1,PP.2006:2601-2609.
[16] C.Russ,M.Mergens,J.An-her,C.Jozwiak,G.Kolluri,L.Avery and k Verhaege, GGSCRs :GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submieron CMOS processes,Proc.23rd EOS/ESD Symposium,2001:22-31.
[17] k Kunz,C.Duvvury and H.Shichijo,5-Volt tolerant fail-safe ESD solutions for a O.1 89m logic CMOS process,Proc.23rd EOS/ESD Symposium,2001:.12-21.
[18] A.Chatterjee,T.Polgrcen and A.Amcrasekera,Design and simulation of a 4 kV ESD protection circuit,in Tech.Dig.IEDM,1991:913-916.
[19] Ming-Dou Ker,Hun-Hsien chang and Chung-Yu Wu,A gated-couple PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC’S,IEEE,1997:38-51.
[20] Sten Hellstr6m,ESD:”The Scourge of Electronics,Berlin;NewYork”:Springer.1998.
[21]马晓慧.多电源和多地的片上ESD保护.半导体技术,2010:26(10)25-26.
[22] MIL-STD-883E, Methode 3015.7, Electrostatic Discharge Sensitivity Classification, Dept. of Defence, Test Method Standard, microcircuits, 1989:99-102.
[23] ESDSTM5.1-1998 Revised, Electrostatic Discharge Sensitivity Testing-Human Body Model Component Level, the ESD Association, 1998:65-70.
[24] JEDEC JESD22-A114-B, Electrostatic Discharge Sensitivity Testing Human Body Model, the Electronics Industries Alliance, June 2000:57-60.
[25] AEC-Q100-002 Rev-C, Human Body Model Electrostatic Discharge Test, the Automotive Electronics Council, October 1998:57-66.
[26] ESD STM5.2-1999 Revised, Electrostatic Discharge Sensitivity Testing-Machine Model Component Level, the ESD Association, 1999:87-92.
[27] JEDEC JESD22-A115-A, Electrostatic Discharge Sensitivity Testing Machine Model, the Electronics Industries Alliance, October 1997:22-28.
[28] AEC-Q100-003 Rev-E, Machine Model Electrostatic Discharge Test, the AutomotiveElectronics Council, January 2001:43-45.
[29] ESD STM5.3.1-1999 Revised, Electrostatic Sensitivity Testing-Charged Device Model Component Level, the ESD Association, 1999:23-31.
[30] ESD STM5.3.1-1999 Revised, Electrostatic Sensitivity Testing-Charged Device Model Component Level, the ESD Association, 1999:34-39.
[31] JEDEC JESD22-C101-A, Field-Induced Charged-Device Model test Method for Electrostatic Discharge-Withstand Thresholds of Microelectronic Components, the Electronics Industries Alliance, June 2000:66-70.
[32] AEC-Q100-011 Rev-A, Charged-Device Model Electrostatic Discharge Test, the Automotive Electronics Council, January 2001:44-47.
[33] Ming-Dou Ker "ESD (Electrostatic Discharge) Protection in CMOS Integrated Circuits"
[34] S Mallat, Z Zhang. Maching Pursuit Time-freqency Distributions. IEEE Trans.Signal Processing,1993,41(12):3397-3415. ?