倒装焊及相关问题的研究
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摘要
随着微电子产业的迅猛发展,半导体技术微细加工特征尺寸减小,晶片
    尺寸加大,IC芯片I/O端口数剧增,相应的芯片封装技术向高密度、高可
    靠性和低成本方向发展。倒装焊接技术因为具有近乎理想的封装密度和优异
    的高频性能,极有可能成为未来微电子封装的主流。国外对倒装焊先进封装
    的研究较广泛,涉及结构、材料、工艺和可靠性等等。而国内系统性的研究
    开展不多,本课题组对倒装焊先进封装进行了实验和数值模拟两方面的研
    究,旨在填补国内在这方面的不足,为例装焊在国内的大规模应用提供技术
    积累。
     无损检测是微电子封装可靠性研究领域的重要手段,本实验过程中使用
    高频(230MHz)声学显微镜进行无损检测。结果发现,声学检测不仅对倒装焊
    底充胶分层敏感,而且随着实验过程的进行,相应的C-SAM图象焊点衬度
    变化直接与焊点的热疲劳裂纹萌生与生长程度相关。因此,在可靠性实验过
    程中,观察C-SAM图象中焊点衬度变化,可以在不破坏样品的情况下,定
    性探测到焊点热疲劳损伤程度,从而获得倒装焊可靠性研究中完整、准确和
    细致的信息。
     使用底充胶可以明显提高倒装焊SnPb焊点的热疲劳寿命,但底充胶分
    层会影响焊点的可靠性。对不同参数底充胶试样通过温度循环实验并结合二
    维有限元模拟结果,研究了底充胶分层和SnPb焊点可靠性的联系。研究表
    明,底充胶分层易发生在芯片/底充胶界面边缘处;当底充胶与芯片粘合强
    度较弱时,底充胶的早期分层是焊点中裂纹萌生扩展从而导致失效的直接原
    因;当底充胶与芯片粘合强度较强时,分层可以削弱底充胶对焊点的机械耦
    合作用,从而影响焊点的热循环寿命,此时,焊点热疲劳裂纹是焊点失效的
    直接原因。另外,文中针对降低底充胶分层的发生进行了工艺参数和过程的
    优化。
     通过对不同尺寸倒装焊SnPb焊点进行热循环实验,结合三维全局有限
    元模拟的结果,研究SnPb焊点热疲劳失效机制。结果发现,充胶后焊点内
    塑性应变范围减小近一个量级,从而显著降低焊点的疲劳损伤;由于底充胶
    改变了SnPb焊点应力应变分布,使得充胶前后焊点裂纹位置发生改变;充
    胶后焊点高度对SnPb焊点热疲劳寿命的影响变得不明显。热循环实验后,
    富Pb相和富Sn相都发生非均匀组织粗化,SnPb焊点热疲劳裂纹萌生于粗
    化区域。富Sn、富Pb相的非均匀粗化趋势与模拟给出的剪切应变轴向分布
    相一致。
    
    
     @B
     最后,通过高温高湿实验进行了湿度对倒装焊封装可靠性影响的探索性
    研究。研究结果发现,倒装焊焊点有一定抵御潮热环境的能力。实验过程中
    水汽主要通过基板背面渗入底充胶材料,引起底充胶与芯片界面发生分层,
    并且发现由于吸水导致的肿胀效应可引起分层区域发生动态复合现象。
     本论文由于全程监测了可靠性实验过程,对倒装焊可靠性进行了综合性
    的研究,同时高频声学显微镜为研究过程提供了准确信息,对焊点裂纹萌
    生、生长及底充胶分层、传播等进行了精细的研究,从而对于倒装焊底充胶
    分层与SnPb焊点失效的相关性有了清晰的认识。本论文工作同时为倒装焊
    及相关微电子封装可靠性的研究提供有效的实验手段和方法,具有重要科研
    应用价值。
With the rapid development of microelectronic industries, the reduction of
     feature size, growth in wafer size will continue in semiconductor industry. There
     is a crucial need for IC packaging to move to higher density, higher performance
     and lower cost. Flip Chip technology, by offering almost ideal density and
     superior performance, and could become the mainstream technology in the future.
     There are numerous investigations overseas, focused on the structure, materials,
     processes and reliability, etc. However in China, few systematic investigations
     were reported. In this project, flip chip on board (FCOB) technology was studied
     both experimentally and theoretically. The effort aim is promoting research
     activities in the field. Also it is considered to be important for the coming mass
     production with flip chip technology in the future.
    
     Undestructive inspection is an important technique in the reliability study on
     the microelectronic packaging. The undestructive inspection of high frequency
     (230MHz) scanning acoustic microscopy (SAM) is applied in our experimental
     study. It can be seen that not only the SAM is highly sensitive on the underfill
     delamination, but also the fatigue crack initiation and growth is directly coincide
     to the contrast variation of solder joint in C-SAM images during reliability test.
     Therefore the degree of solder joint fatigue of FCOB can be qualitative detected
     through comparing the contrast variation of the C-SAM images without destruct
     the sample. So the rather precision information in reliability investigation on
     FCOB can be accumulated through SAM inspection.
    
     The thermal fatigue lifetime of SnPb solder joints can be greatly increased by
     applying underfihl encapsulant in FCOB. However, the underfill delamination
     could correspondingly effect the reliability of solder joints. By conducting thermal
     cycling test and two-dimensional finite element simulation on the FCOB with
    
    
    
     different underfihl materials, the relationship between the underfihl delamination
     and the SnPb solder joint reliability is investigated. The results show that the
     underfihl delamination initiates at the edge of chip/underfill interface. If an
     underfihl did not have a good adherence to the chip, the fatigue crack initiation
     and propagation in the solder joints is caused directly by the incipient underfihl
     delamination. On the other hand, if an underftll had a good adherence to the chip,
     the dominant failure mode should be the fatigue crack in the solder joints. It is
     shown that the mechanical coupling effect of the underfihl could be weakened by
     the underfihl delamination, which should influence lifetimes of the solder joints.
     The processes are optimized to decrease the occurring of underfihl delamination.
    
     By conducting thermal cycling test and three-dimensional global finite
     element simulation, the thermal fatigue failure of SnPb solder joints of different
     size FCOB is investigated. The results show that plastic strain range in the solder
     joints is decreased to nearly an order of magnitude after underfihling, therefore
     degrades thermal fatigue failure of the solder joints subsequently. Since the
     thermal stresses and strains in the solder joints are redistributed due to the
     application of underfihl, the locations of thermal fatigue crack initiation and
     propagation in the solder joints are changed. Furthermore the height of the solder
     joint is found irrelevant to the thermal fatigue life of SnPb joints in Flip Chip.
     Heterogeneous coarsening is observed on both Sn-rich and Pb-rich phases after
引文
[1] Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors, 1999.
    [2] R. R. Tummala, E. J. Rymaszewski, A. G. Klopfenstein, in Microelectronics Packaging Handbook, Chapman & Hall, 1997, New York
    [3] Kovac, C. "Plastic Package Fabrication," in Electronic Materials Handbook, ASM International, Materials Park, OH, Vol. 1 Packaging, p. 471-473,1998.
    [4] E .M. Davis, N. E. Harding, R. S. Schwartz and J. J. Corning, "Solid Logic Technology: Versatile High Performance. Microelectronics," IBM J. Res. Devel., 8: p. 102,1964.
    [5] R. R. Tummala, "Next Generation of Packaging beyond BGA, MCM and Flipchip," in Proceeding of IMC, 1996.
    [6] L. S. Goldmann and P. A. Totta, "Chip Level Interconnect: Solder Bumped Flip Chip," in Chip on Board Technologies for Multichip Modules, J. H. Lau, ed., Van Nostrand Reinhold, New York, p. 228-250, 1994.
    [7] J. Giseler, S. Machaga, G. O'Malley, and M. Williams, "Reliability of Flip Chip on Board Assemblies," International TAB/Advance Packaging and Flip Chip Proceedings, p. 127-135, Feb. 1994.
    [8] T. Chung, D. Carey, and B. Gardner, "Development of Large high I/O Flip-Chip Technology," Proceedings of NEPCON West, p.1527-1536, 1994.
    [9] G. Adema, C. Berry, N. Koopman, G. Rinne, E. Yung, and I. Turlik, "Flip Chip Technology: A Method for Providing known Good Die with High Density Interconnections," in Proceedings of the 3rd International Conference & Exhibition on Multichip Modules, p.41-49, 1994.
    [10] E. Ajith Amerasekera, in Failure Mechanism in Semiconductor Devices, John Wiley & Sons, New York, 1997.
    [11] O. L. Anderson, Bell Lab, REC,, Nov., 1957.
    [12] C. G. Peattie, J. D. Adams, S. L. Correl, T. D. George, and M. H. Valela, "Elements of Semiconductor Device Reliabity," Proc. IEEE, Vol. 62, p.149-168, 1974.
    [13] D. S. Deck and C. H. Zierdt, "The reliability of semiconductor device in the Bell System," Proc. IEEE. Vol. 62, p. 85-211, 1974.
    [14] G. L. Schnable and R. S. Keen, "On failure mechanism in largew-scale integrated circuits," Advances in Electronics and Electron Physics, Vol. 30, p. 80-138, 1971.
    [15] Da-Yuan Shih and P. J. Ficalora, "The reduction of Au-Al intermetallic formation and Electromigration in hydrogen environments," IEEE Trans. Electron Devices, ED-26, p. 27-34, 1979.
    
    
    [16] M. P. Lepselter, "Beam Lead Technology," Bell Sys. Tech. J., 45: p.233-253, 1966.
    [17] J. A. Perri, H. S. Lehman, W. A. Pliskin, and J. Riseman, "Surface Protection of Silicon Devices with Glass Filmes," Electrochemical Society Meeting, p. 102, 1961.
    [18] P. A. Totta and R. P. Sopher, "SLT Device Metallurgy and Its Monolithic Extension," IBM J. Res, Devel, 5: p.226-238, 1969.
    [19] P. A. Totta, "Flip-chip Solder Terminals," in 21st Electronics Components Conference, p.275, 1971.
    [20] T. Yamada, K. Otsutani, K. Sahara, and K. Otsuka, "Low Stress Design of Flip Chip Technology for Si on Si Multichip Modula," IEPS, p.551-557,1985.
    [21] L. S. Goldmann, "Self-Alignment Capability of Controlled-Collapse Chip Joining," Proceedings 22nd Electronic Components Conference, 1972, pp. 332.
    [22] Hudeki Tsunetsugu, Tsuyoshi Hayashi, and Kohsuke Katsura, "Accurate, Stable, High-Speed Interconnections Using 20-to 30-m-diameter Microsolder Bumps," IEEE Trans, on CPMT, Vol.20, p.76-82, 1997.
    [23] D. J. Bendz, R. W. Gedney, and J. Rasile, "Cost / Performance Single Chip Module," IBM J. Res. Devel., 26: p.278-285,1982.
    [24] S. E. Greer, "Low Expansivity Organic Substrate for flip-chip Bonding," 28th Electronic Components Conference Proceedings, p. 166-171, 1978.
    [25] W. Weston, "High Density 128 × 128 Area Arrays of Vertical Electrical Internations," 4th Annual Microelectronic Interconnect Conference, 1985.
    [26] Karl J. Puttlitz and William F. Shutler, "C4/CBGA Comparison with other MLC SingleChip Package Alternatives," IEEE Trans, on CPMT, Vol. 18, No. 2, p.250-256, 1995.
    [27] L. F. Miller, "Controlled Collapse Reflow Chip Joining," IBM J. Res. Devel, 1969, vol. 13, pp. 239-250
    [28] Y. Tsukada, "Surface Lamilar Circuit and Flip Chip Attach Packaging," ECTC, 1992
    [29] Taklkashi Nishimori, Hiroshi Yanagihara, Keiji Murayama, Yasunori Kama, and Nakamura, "Characteristics and Potential Application of Polyimide-Core-Bump to Flip Chip," IEEE Trans on CPMT, Vol.19, No.l, p. 18-23, 1996.
    [30] I. Lang, "Surface mounting of Leadless Chip Carriers on Various Printed Circuit Board Type Substrates," Electron. Sci. Technol, 9: p.296, 1982.
    [31] J. D. Leibowitz and W. E. Winters, "Shirline A Coefficient of Thermal Expansion (CTE) Controllable Family of Materials," IEPC, 1982.
    [32] J. Fisher, "Cast Leads for Surface Attachment," ECC, p.219, 1984.
    [33] S. K. Lahiri, H. R. Bickford, P. Geldermans, K. R. Grebe, and P. A. Moskowitz,
    
    "Packaging Technology for Josephson Integrated Circuits," IEEE Components Hybrids Manuf. Technol., CHMT-5(2) : p.271,1982.
    [34] C. Y. Ting, K. Grebe, and D. Waldman, "Controlled Collapse Reflow for Josehpson Chip Bonding," J. Electrochem. Soc., 129(4) : p.859-864, 1982.
    [35] K. R. Grebe, "Orthogonal Solder Interconnects for Josephson Packaging," J. Electrochem. Soc., 127: 1980.
    [36] S. Ahmed, R. Tummala, and H. Potts, "Packaging Technology for IBMs Latest Mainframe Computers (S1390/ES 9000) ," Proc. ECTC, p.682-688, 1991.
    [37] J.M.Meby, in Proc. IEEE 34lh Electronic Component and Technology Conf. (London), 1984, p. 117-123.
    [38] F. Nakano, T. Soga, and S. Amagi, "Resin Insertion Effect on Thermal Cycle Resistivity of Flip Chip Mounted LSI Devices," Proceedings 1987 ISHM Conference, p.536-541, 1987.
    [39] Y. Tsukada, "Surface Lamilar Circuit and Flip Chip Attach Packaging," ECTE, 1992.
    [40] D. Suryanarayana, T. Y. Wu, and J. A. Varcoe, "Encapsulants used in flip-chip package," in Proc. 43rd ECTC, Orlando, FL, 1993.
    [41] C. P. Wong, S. H. Shi and G. Jifferson, "High Performance No-Flow Underfills for Low-Cost Flip-Chip Applications: Material Characterization," IEEE Trans, on CPMT, Vol. 21, p. 450-458, 1998.
    [42] N. W. Pascarella and D. F. Baldwin, "Compression Flow Modeling of Underfill Encapsulants for Low Cost Flip-Chip Assembly," IEEE Trans, on CPMT., Vol. 21, p. 325-335, 1998.
    [43] D. A. Jeannotte, "Solder as a Structral Member for Chip Joining," Electronic Components Conference Proceedings, p.334, 1969.
    [44] Boettiet et al., IEEE Trans, on CHMT, 1986: p. 16-29.
    [45] R.G.Rosset et al.,A,SME.J. Electronic Package, 113(2) 1991, p. 181-185.
    [46] T. Kamei and M. Nakamura, "Hybrid IC Structures Using Solder Reflow Technology," 28th Electronic Components Conference Proceedings, p.172-182, 1978.
    [47] P. M. Hall, "Solder Post Attachment of Ceramic Chip Carriers to Ceramic Film Integrated Circuits," 31st Electronic Components Conference Proceedings, p.172-180, 1981.
    [48] L. S. Goldmann, "Geometric Optimization of Controlled Collapse Interconnections," IBM J. Res. Devel, 3: p.251-265, 1969.
    [49] R. Satoh, M. Ohshima, H. Komura, I. Ishi, and K. Serizawa, "Development of a New Micro-Solder Bonding Method for VLSI," IEPS, p. 455, 1983.
    [50] V. K. Nagesh, "Reliability of Flip Chip Solder Bump Joints," IEEE Proc. IRPS, p.6-15,
    
    1982.
    [51] L. S. Goldmann and P. A. Totta, "Area Array Solder Interconnection for VLSI," Solid State Technol, 1983.
    [52] R. T. Howard, "Optimization of Indium-Lead Alloys for Controlled Collapse Chip Connection Application," IBMJ. Res. Devel, 26(3) : p.372-389, 1982.
    [53] N. Matsui, S. Sasaki, and T. Ohsaki, "VLSI chip interconnection technology using stacked solder bumps," Proc. IEEE 37'h Electronic Components Conf., May 1987, p. 573-578.
    [54] P. Schmid and H. Melchior, "Coplanar flip-chip mounting technology for picosecond devices," Pev. Sci. Insir., Vol. 55, No. 11, p. 1865, 1984.
    [55] K. Lodge, D. Pedder, "The Impact of Packaging on the Reliability of Flip Chip Solder Bonded Devices," Proc. ECTC, p.470-476, 1990.
    [55] L. S. Goldmann, R. J. Herdizk, N. G. Koopman, and V. C. Marcotte, "Lead Indium for Controlled Collapse Chip Joining," 27'h Electronic Components Conference Proceedings, 27: p.25, 1977.
    [56] P. Schmid and H. Melchior, "Coplanar Flip-Chip Mounting Techniques for Picosecond Devices," Rev. Scilnstrum., 55(11) : p.1854, 1984.
    [57] W. Roush and J. Jaspal, "Thermomigration in Lead-Indium Solder," 32nd Electronic Components Conference Proceedings, p.342, 1982.
    [58] S. M. Lee, ASMEJ. Electronic Packaging, 1992, vol. 114, no. 6, pp. 109-111.
    [59] Kazuhide Doi, Naohiko Hirano, Takashi Okada, Yoichi Hiruta, Toshio Sudo, and Minoru Mukai, "Prediction of Thermal Fatigue Life for Encapsulated Flip Chip Interconnection," The International J. Microcircuits and Electronic Packaging, Vol. 19, No.3, p. 231-237, 1990.
    [60] A. Schubert, R. Dudek, D. Vogel, B. Michel, and H. Reichl, "Material Mechanics and Mechanical Reliability of Flip Chip Assemblies on Organic Substrates," Advanced Packaging, p.29-32, July/August, 1997.
    [61] S. C. Machuga, S. E. Lindsey, K. D. Moore, and A. F. Sleipor, "Encapsulation of flip chip structures," in Proc. IEEE/CHMT. Symp., p.53-58, 1992.
    [62] Vadim Gektin, Avram Bar-Cohen, and Jeremy Ames, " Coffin-Manson Fatigue Model of Underfilled Flip Chips," IEEE Trans, on CPMT, Vol. 20, p. 317-325, 1997.
    [63] J Jon B. Nyssether, Pontus Lundstrom, and Johan Liu, (1998) , "Measurements of Solder Bump Lifetime as a Function of Underfill Material Properties ", IEEE Trans. CPMT,Vol. 21, No. 2, pp. 281-287 .
    [64] K. C. Norris, and A. H. Landzberg, "Reliability of Controlled Collapse Interconnections," IBMJ. Res. Devel., 13(3) : p.266-271,1969.
    
    
    [65] P. A. Tobias, N. A. Sinclair, and A. S. Van, "The Reliability of Controlled-Collapse Solder LSI interconnections," ISHM Proc. p.360, 1976.
    [66] E. P.Busso, et al, "Modeling complex inelastic deformation processes in IC packages' solder joints," ASME J of Elect. Pack., Vol. 116(3) , 1994:6.
    [67] S. H. Ju, B. I. Sandor and M. E. Plesha, "Life prediction of solder joints by damage and fracture mechanics," ASMEJ. of Elect. Pack., Vol. 118(6) , 1996:193.
    [68] C. Y. Li, R. Subrahmanyan, J. R. Wilcox and D. Stone, "A damage integral methodology for thermal and mechanical fatigue of solder joints," Solder Joint Reliability, edited by J. H. Lau, van nostand reinhold, New York, 1991:361.
    [69] Z. Guo and H. Conrad, "Fatigue crack growth rate in 63Sn37Pb solder joints," ASMEJ. of Elect. Pack., Vol. 115,1993:1.
    [70] H. D. Solomom and E. D. Tolkadort, "Energy approach to the fatigue of 60/40 solder: part1-Influence of temperature and cycle frequency," ASME J. of Elect. Pack., Vol. 117(3) , 1995:130.
    [71] V. Sarihan, "Energy based Methodology for damage and life prediction of solder joints under thermal cycling," IEEE Trans, on CPMT, Vol. 17(4) , 1994:636.
    [72] S. Vaynman and S. A. Mckeown, "Energy based methodology for the fatigue life prediction of solder materials," in Proc. 41st Components Conf., May 1991:671.
    [73] D. Suryanarayana, R. Hsiao, T. P. Gall, and J. M. McCreary, (1991) ,"Flip chip solder bump fatigue enhanced by polymer encapsulation", IEEE Trans, on CHMT, Vol.14, pp.218-223.
    [74] Zoba and Edwards, "Review of underfill encapsulant development and performance of flip chip application," ISHM'95 Proc., 1995, p.354-358.
    [75] H. Doi, K. Kawano, A. Yasukawa, T. Sato (1998) , "Reliability of Underfill-Encapsulated Flip-Chip With Heat Spreaders"J. Elect. Packag., Vol. 120, pp. 322-327.
    [76] K. Darbha, J. H. Okura, and A. Dasgupta, "Impact of Underfill Filler Particles on Reliability of Flip-Chip Interconnects," IEEE Trans, on CPMT, Vol. 21, No. 2, P.275-279, 1998.
    [77] S. Han and K. K. Wang, "Study on the Pressurized Underfill Encapsulation of Flip Chips," IEEE Trans on CPMT, Vol.20, No.4, p.434-442, 1997.
    [78] C. P. Wang, M. B. Vincent, and S. Shi, "Fast-Flow Underfill Encapsulant: Flow Rate and Coeffient of thermal Expansion," IEEE Trans, on CPMT, Vol.21, No.2, p. 360-363, 1998.
    [79] P. Palaniappan and D. F. Baldwin, "Prelininary in-process stress analysis of flip-chip assemblies during underfill," in Proc. 30th Int. Symp. Microelectro., Philadelphia, PA, Oct. 1997, p. 579-585.
    [80] P. Palaniappan, D. F. Baldwin, P. J. Selman, Jaili Wu, and C. P. Wang, "Correlation of Flip
    
    Chip Underfill Process Parameters and Material Properties with In-Process Stress Generation,"IEEE Trans. on CPMT, Vol. 22, No. 1, p. 53-62, 1999.
    [81]陈柳,博士论文,中科院上海冶金研究所。
    [82]王勖成等,“有限元单元法基本原理和数值方法”,第2版,清华大学出版社,1997.
    [83]D. Gamota and C.Melton, (1997) "Advanced Encapsulant Materials Systems for Flip Chip", Advancing Microelectronics, pp.22-24.
    [84]J. M. Rosson, R. A. Clawson and D. W. Ihms, (1999) ,"Underfill Test Methods for the Harsh Automotive Environment", Adv. Packag., pp.48-53.
    [85]周德俭,潘开林,吴兆华,等,半导体学报,1999,20(1):47.
    [86]卢基存,宗详福,吴建华,等,半导体学报,1999,20(10):906
    [87]T. M. Moore, "Inspecting IC packages with C-mode acoustic microscopy," in Proc. Int.Symp. Testing Failure Anal., 1989, p.41-50.
    [88]J. E. Semmens and L. W. Kessler, "Application of Acoustic Micro Imaging For The Evaluation of Advanced Microelectronic Packaging: An Overview of Experiences from 1973-1996," in Proceedings of the Second International Symposium on Electronic Packaging Technology,Shanghai, P. R. China, p.60-72, December 9-12, 1996.
    [89]J. E. Semmens, S. R. Martell, L. W. Kessler, "Evaluation of Flip Chip Interconnections Using Acoustic Microscopy For Failure Analysis And Process Control Applications," in Proceedings of the International Conference on Multichip Modules, MCM'95, Denver, Colorade,p.279-285, 1995.
    [90]W. Lawton and J. Barrett, "Characterisation of Chip-on-board and Flip Chip packaging Technology by acoustic microscopy," Microelectron. Reliab., Vol. 36, No. 11/12, p. 1803-1806,1996.
    [91]Dishon, A., S. Bobbio, N. Koopman, and G. Rinne, "Plasma Assisted Fluxless Soldering",NEPCON West, Feb. 23-27, 1992.
    [92]Benson,R.C., et al., "Metal Migration Induced by Solder flux Residue in Hybrid Microcircuits", IEEE Transact. Components, Hybrid, Manufact. Technol. 2(4): Dec. 1988.
    [93]J. Partridge and P. Viswanadham, "Organic Carrier Requirements for Flip Chip Assemblies." Proceedings: NEPCN, Reed Exhibition Companies, 11:1519-1526, 1993.
    [94]赵保经主编,《中国集成电路大全——集成电路封装》
    [95]Wu jianhua, Ng Sok Fang and Lu Jicun, "AlPad Corrosion Under Temperature Humidity in Flip-Chip on board"
    [96]E. Suhir, "The Future of Microelectronics and Photonics and the Role of Mechanics and Marerials," J. Elect. Packag., Vol. 120, p.1-11, 1998.
    
    
    [97]E. Madenci, S. Shkarayev, R. Mahajan, "Potential Failure Sites in a Flip-Chip Package With and Without Underfill", J. of Elect. Packag., Vol. 120, p.336-341, 1998.
    [98]G.. O'Malley, J. Giesler and S.Machuge, "The Importance of Material Selection for Flip Chip on Board Asemblies", IEEE Trans. on CPMT, Vol. 17, No.3, p.245-255, 1994.
    [99]L. Anand, Constitutive Equations for Hot Working of Metals, Intern. J. Plasticity, 1985 1:213-231
    [100]T. S. Yeung, and M. M. F. Yuen, "Viscoelastic analysis of IC package warpage", EEP-Vol. 17, Sen., Mod. And Simu. In Emer. Electr. Packag., ASME, p.101-107, 1996.
    [101]S. K. Tran, D. L. Questad, and B. G. Sammakia, "Adhesion Issues in Flip-Chip on Organic Modules", IEEE Trans. on CPMT, Vol.22, No.4, p.519-524, 1999.
    [102]J. H. Lan, IEEE Trans. on CPMT, Vol.19, No.4, p.7-8, 1996.
    [103]S. Rzepka, M. A. Korhonen, E. Meusel, and C. -Y. Li, "The Effect of Underfill and Underfill Delamination on the Thermal Stress in Flip-Chip Solder Joints", J. Elect.Packag.,Vol. 120,p.342-348, 1998.
    [104]H. Solomon, "Fatigue of 60/40 solder",IEEE Trans. Comp., Hybrids, Manufact.,Technol., Vol. CHMT-9, p.423-432, 1986.
    [105]A. C. LeGall, Q. Jianmin, and D. L. McDowell, "Delamination Cracking in Encapsulated Flip Chips", in 46th Electronic Components and Technology Conference Proceedings, IEEE,Piscataway,NJ, p.430-434, 1996.
    [106]J. T. Lynch, M. R. Ford, and A. Boetti, IEEE Trans Components, Hybrids, and Manufacturing Tech,CHMT-6,p.237, 1983.
    [107]R. Yenawine, M. Wolverton, A. Burkett, B. Waller, B. Russel, and D. Spritz, "Today and Tomorrow in Soldering", in Proc 11th Naval Weapons Electronics Manufacturing Seminar, ChinaLake,CA, p.339, 1987.
    [108]R. N. Wild, "Some fatigue properties of solders and solder joints", IBM Report No. 74Z00481, 1975.
    [109]D. Frear, D. Grivas, and J. W. Morris, "A Microstructural Study of the Thermal Fatigues of 60Sn40Pb Solder Joints", J. Elect. Mater.,Vol. 17,No.2,p.171-180, 1988.
    [110]S. S. Manson in "Thermal Stress and Low Cycle Fatigue", McGraw-Hill Book Company,New York, 1966.
    [111]K. Doi, N. Hirano, T.Okada, Y.Hiruta, and T.Sudo, "Prediction of Thermal Fatigue Life for Encapsulated Flip-Chip Interconnection", Intern. J. Microcir. And Elect. Packag., Vol19, pp.231-237,1998.
    [112]王国忠,陈柳,程兆年,“电子封装 SnPb 焊料和底充胶的材料及其应用”,机械工程学报,2000;36(12):33。
    
    
    [113]赵润涛,硕士论文,中科院上海冶金研究所。
    [114]K. Van Doorselear and K. De Zeeuw, "Relation between delamination and temperature cycling induced failures in plastic packaged devices," IEEE Trans. CHMT, Vol. 13, p. 879-882, Dec.1990.
    [115]R. L. Shook and T. R. Conrad, "Accelerated life performance of moisture damaged plastic surface mount devices," in Proc. Int. Ret Physics Syrup., p. 157-168, 1993.
    [116]Y. Ranade, M. G. Pecht, and T. M. Moore, "New Findings in the Occurrence of False-Healing in Plastic Encapsulated Microcircuits using Scanning Acoustic Microscopy," IEEE Trans.on Comp. and Packag. Technol., Vol. 22, No. 2, June 1999.
    [117]康吉娜(音译),硕士论文。

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