USB3.0物理层数据发送器的研究和设计
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摘要
随着数字媒体的日益普及以及传输文件的不断增大,甚至超25GB,快速同步即时传输已经成为必要的性能需求。2007年底,英特尔公司和业界领先的公司一起携手组建了USB 3.0推广组,旨在开发速度超过当今10倍的超高效USB互联技术。该技术是由英特尔,以及惠普(HP)、NEC、NXP半导体以及德州仪器(Texas Instruments)等公司共同开发的,应用领域包括个人计算机、消费及移动类产品的快速同步即时传输。USB 3.0具有后向兼容标准,并兼具传统USB技术的易用性和即插即用功能。该技术的目标是推出比目前连接水平快10倍以上的产品,采用与有线USB相同的架构。除对USB 3.0规格进行优化以实现更低的能耗和更高的协议效率之外,USB 3.0的端口和线缆能够实现向后兼容,以及支持未来的光纤传输。
论文主要分成两大部分,分别对USB3.0物理层模块中时钟发生器和数据发送器的设计进行研究和设计,这两个电路也是物理层中非常核心的部分。按照USB 3.0协议的要求,时钟发生器需要具备扩频时钟功能(Spread Spectrum Clocking),本文中的设计是基于锁相环技术和ΣΔ调制器技术实现的,首先分析了常用的时钟发生器的设计方法,并确定采用ΣΔ分数分频的锁相环来实现扩频时钟发生器,然后研究了锁相环的系统线性模型以及锁相环中PFD/CP的非线性特性与鉴相死区、VCO的相位噪声特性、ΣΔ调制器的噪声整形原理和三角波发生器电路,并对每个电路模块以及整个时钟发生器进行了仿真。本文的另外一部分,对高速并串转换电路的两种结构进行了比较和分析,从功耗和版图复杂性的折中考虑本文采取两种结构级连的方式最后实现5Gbps的40到1的并串转换器。接着再对线驱动器的结构和预均衡设计做了研究和分析,并做了整体的仿真和结果分析。
本文使用的是SMIC 90nm CMOS Mix Signal工艺,仿真结果表明,时钟发生器输出频率可以达到5GHz,高速并串转换和线驱动器也能够到到5Gbps的数据率。整个版图的面积是890μm×810μm。
With the ever prevailing application of digital media and increasing volume, which sometimes exceeds 25 GB, of digital files being transferred, synchronized real time transmission has become an imperative feature of digital data transmission product nowadays. In 2007, Intel and other leading companies in the digital industry launched the USB 3.0 team to develop high speed USB transmission technology that is 10 times faster and more efficient than the current technology. This technology was co-developed by Intel, Hewlett-Packard (HP), NEC, NXP Semiconductors and Texas Instruments. It applies to synchronized real time transmission in personal computers, consumer electronics and mobile electronics. While the USB 3.0 is backward compatible, it is also easy to use and can be hot plugged as traditional USB technology. The goal of this technology is to deliver speed that is 10 times faster than the current technology based on the same structure as the current USB. Besides being more energy efficient by optimizing the specifications, USB 3.0 has connectors and cables that are backward compatible and supports fiber transmissions in the future.
This article divides into two parts, which respectively focus on the Clock Generator and the Transmitter in the PHY micro cell of USB 3.0. These two circuits are also the most important technologies in the PHY micro cell. According to the specifications of USB 3.0, the clock generator should have the feature of Spread Spectrum Clocking, which in this article is implemented based on a combination of Phase Locked Loop andΣΔModulator. The article first discusses popular design methods on clock generators, among which there is the sigma-delta fractional-N phase locked loop that enables the Spread Spectrum Clocking. The article then discusses the system linear model and of the phase locked loop and the non-linearity and dead zone of the PFD/CP, the phase noise of the VCO, the noise shaping of theΣΔModulator and triangle wave generator. The article also describes the simulation results of each block and the whole circuit. The two structures of the high speed serializer are compared and analyzed. In order to balance the power consumption and the complexity of the layout, cascading of two structures is utilized to realize 5Gbps 40 to 1 serializer. The article finally researches and analyzes the structure of the line driver and the pre-emphasis. The simulation results are also analyzed. SMIC 90mm CMOS Mix Signal process is used to implement the design. The simulation results show that, the output frequency of the clock generator can reach 5GHz, and the high speed serializer and line driver can reach the same speed as well. The size of the whole chip is890μm×810μm.
论文主要分成两大部分,分别对USB3.0物理层模块中时钟发生器和数据发送器的设计进行研究和设计,这两个电路也是物理层中非常核心的部分。按照USB 3.0协议的要求,时钟发生器需要具备扩频时钟功能(Spread Spectrum Clocking),本文中的设计是基于锁相环技术和ΣΔ调制器技术实现的,首先分析了常用的时钟发生器的设计方法,并确定采用ΣΔ分数分频的锁相环来实现扩频时钟发生器,然后研究了锁相环的系统线性模型以及锁相环中PFD/CP的非线性特性与鉴相死区、VCO的相位噪声特性、ΣΔ调制器的噪声整形原理和三角波发生器电路,并对每个电路模块以及整个时钟发生器进行了仿真。本文的另外一部分,对高速并串转换电路的两种结构进行了比较和分析,从功耗和版图复杂性的折中考虑本文采取两种结构级连的方式最后实现5Gbps的40到1的并串转换器。接着再对线驱动器的结构和预均衡设计做了研究和分析,并做了整体的仿真和结果分析。
本文使用的是SMIC 90nm CMOS Mix Signal工艺,仿真结果表明,时钟发生器输出频率可以达到5GHz,高速并串转换和线驱动器也能够到到5Gbps的数据率。整个版图的面积是890μm×810μm。
With the ever prevailing application of digital media and increasing volume, which sometimes exceeds 25 GB, of digital files being transferred, synchronized real time transmission has become an imperative feature of digital data transmission product nowadays. In 2007, Intel and other leading companies in the digital industry launched the USB 3.0 team to develop high speed USB transmission technology that is 10 times faster and more efficient than the current technology. This technology was co-developed by Intel, Hewlett-Packard (HP), NEC, NXP Semiconductors and Texas Instruments. It applies to synchronized real time transmission in personal computers, consumer electronics and mobile electronics. While the USB 3.0 is backward compatible, it is also easy to use and can be hot plugged as traditional USB technology. The goal of this technology is to deliver speed that is 10 times faster than the current technology based on the same structure as the current USB. Besides being more energy efficient by optimizing the specifications, USB 3.0 has connectors and cables that are backward compatible and supports fiber transmissions in the future.
This article divides into two parts, which respectively focus on the Clock Generator and the Transmitter in the PHY micro cell of USB 3.0. These two circuits are also the most important technologies in the PHY micro cell. According to the specifications of USB 3.0, the clock generator should have the feature of Spread Spectrum Clocking, which in this article is implemented based on a combination of Phase Locked Loop andΣΔModulator. The article first discusses popular design methods on clock generators, among which there is the sigma-delta fractional-N phase locked loop that enables the Spread Spectrum Clocking. The article then discusses the system linear model and of the phase locked loop and the non-linearity and dead zone of the PFD/CP, the phase noise of the VCO, the noise shaping of theΣΔModulator and triangle wave generator. The article also describes the simulation results of each block and the whole circuit. The two structures of the high speed serializer are compared and analyzed. In order to balance the power consumption and the complexity of the layout, cascading of two structures is utilized to realize 5Gbps 40 to 1 serializer. The article finally researches and analyzes the structure of the line driver and the pre-emphasis. The simulation results are also analyzed. SMIC 90mm CMOS Mix Signal process is used to implement the design. The simulation results show that, the output frequency of the clock generator can reach 5GHz, and the high speed serializer and line driver can reach the same speed as well. The size of the whole chip is890μm×810μm.
引文
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[3]Ranasinghe DC, Leong KS, Ng ML, et al. A distributed architecture for a ubiquitous RFID sensing network[C], Melbourne, Australia:Inst. of Elec. and Elec. Eng. Computer Society,2005:7-12.
[4]Want R. Enabling ubiquitous sensing with RFID[J]. Computer,2004,37 (4): 84-86.
[5]Mak P-I, U S-P, Martins RP. Transceiver architecture selection:Review, state-of-the-art survey and case study[J]. IEEE Circuits and Systems Magazine, 2007,7 (2):6-24.
[6]赵晖.基于锁相环结构的900MHz CMOS频率综合器设计[D].上海：复旦大学,2003.
[7]池保勇,余志平,石秉学.CMOS射频集成电路分析与设计[M].北京：清华大学出版社,2006.
[8]Razavi B. Design considerations for direct-conversion receivers[J]. IEEE Transactions on Circuits and Systems Ⅱ:Analog and Digital Signal Processing, 1997,44 (6):428-435.
[9]Shu K, Sanchez-Sinencio E. CMOS PLL Synthesizers:Analysis and Design[M]. Springer,2005.
[10]De Muer B, Steyaert MSJ. A CMOS monolithic-ΔΣ controlled fractional-N frequency synthesizer for DCS-1800[J]. IEEE Journal of Solid-State Circuits, 2002,37 (7):835-844.
[11]Rhee W. Multi-Bit Delta-Sigma Modulatotion Technique For Fractional-N Frequency Synthesizers[D]. Urbana:University of Illinois at Urbana-Champaign,2001.
[12]Sheng N-H, Pierson RL, Wang K-C, et al. A high-speed multimodulus HBT prescaler for frequency synthesizer applications[J]. IEEE Journal of Solid-State Circuits,1991,26(10):1362-1367.
[13]Gardner FM.锁相环技术[M].姚剑清译.北京：人民邮电出版社,2007.
[14]Razavi B.模拟CMOS集成电路[M].陈贵灿,程军,张瑞智译.西安：西安交通大学,2003.
[15]Gardner FM. CHARGE-PUMP PHASE-LOCK LOOPS[J]. IEEE transactions on communications systems,1980,COM-28(11):1849-1858.
[16]Hanumolu PK, Brownlee M, Mayaram K, et al. Analysis of charge-pump phase-locked loops[J]. IEEE Transactions on Circuits and Systems I:Regular Papers,2004,51 (9):1665-1674.
[17]Hein JP, Scott JW. Z-domain model for discrete-time PLL's[J]. IEEE transactions on circuits and systems,1988,35 (11):1393-1400.
[18]Lu J, Grung B, Anderson S, et al. Discrete z-domain analysis of high order phase locked loops[C]. Sydney, NSW, Australia:Institute of Electrical and Electronics Engineers Inc.,2001:260-263.
[19]Rategh HR, Samavati H, Lee TH. A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver[J]. Solid-State Circuits, IEEE Journal of,2000,35 (5):780-787.
[20]Banaerjee.D. PLL Performance,Simulation and Design[M]. National Semiconductor,2006.
[21]Johansson HO. A simple precharged CMOS phase frequency detector[J]. IEEE Journal of Solid-State Circuits,1998,33 (2):295-299.
[22]Kondoh H, Notani H, Yoshimura T, et al. A 1.5-V 250-MHz to 3.0-V 622-MHz operation CMOS phase-locked loop with precharge type phase-frequency detector[J]. IEICE Transactions on Electronics,1995, E78-C (4):381-388.
[23]Lee GB, Chan PK, Siek L. A CMOS Phase Frequency Detector for charge pump phase-locked loop[C]. Las Cruces, NM, USA:IEEE,1999:601-604.
[24]Won-Hyo L, Jun-Dong C, Sung-Dae L. A high speed and low power phase-frequency detector and charge-pump[C],1999:269-272 vol.261.
[25]Larsson P. Skew safety and logic flexibility in a true single phase clocked system[C]. Seattle, WA, USA:IEEE,1995:941-944.
[26]El-Hage M, Yuan F. Architectures and Design Considerations of CMOS Charge Pumps for Phase-Locked Loops[C]. Montreal, Canada:Institute of Electrical and Electronics Engineers Inc.,2003:223-226.
[27]Rhee W. Design of high-performance CMOS charge pumps in phase-locked loops[J]. Proceedings-IEEE International Symposium on Circuits and Systems, 1999,2:Ⅱ-545-Ⅱ-548.
[28]Arshak K, Abubaker O, Jafer E. Improved charge pump for reduced clock feed through and charge sharing suppression[C]. Dominican republic:Institute of Electrical and Electronics Engineers Inc.,2004:192-194.
[29]Baki RA, El-Gamal MN. A new CMOS charge pump for low-voltage (1V) high-speed PLL applications[C]. Bangkok, Thailand:Institute of Electrical and Electronics Engineers Inc.,2003:1657-1660.
[30]Choi Y-S, Han D-H. Gain-boosting charge pump for current matching in phase-locked loop[J]. IEEE Transactions on Circuits and Systems Ⅱ:Express Briefs,2006,53 (10):1022-1025.
[31]Lee J-S, Keel M-S, Lim S-I, et al. Charge pump with perfect current matching characteristics in phase-locked loops[J]. Electronics Letters,2000,36 (23): 1907-1908.
[32]Shanfeng C, Haitao T, Silva-Martinez J, et al. Design and analysis of an ultrahigh-speed glitch-free fully differential charge pump with minimum output current variation and accurate matching[J]. IEEE Transactions on Circuits and Systems Ⅱ:Express Briefs,2006,53 (9):843-847.
[33]Zhang T, Zou X, Zhao G, et al. Design of a CMOS adaptive charge pump with dynamic current matching[J]. Wuhan University Journal of Natural Sciences, 2006,11 (2):405-408.
[34]Hajimiri A, Lee TH. Design issues in CMOS differential LC oscillators[J]. IEEE Journal of Solid-State Circuits,1999,34 (5):717-724.
[35]Leeson DB. A SIMPLE MODEL OF FEEDBACK OSCILLATOR NOISE SPECTRUM[J]. Proceedings of the Institute of Electrical and Electronics Engineers,1966,54 (2):329-&.
[36]Rael JJ, Abidi AA. Physical processes of phase noise in differential LC oscillators[C]. Orlando, FL, USA:IEEE,2000:569-572.
[37]Hajimiri A, Lee TH. A general theory of phase noise in electrical oscillators [J]. IEEE Journal of Solid-State Circuits,1998,33 (2):179-194.
[38]Razavi B. A study of phase noise in CMOS oscillators [J]. IEEE Journal of Solid-State Circuits,1996,31 (3):331-343.
[39]Hegazi E, Abidi AA. Varactor characteristics, oscillator tuning curves, and AM-FM co0nversion[J]. IEEE Journal of Solid-State Circuits,2003,38 (6): 1033-1039.
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