基于IZAS图像放大处法的SONY47万像素数字视频展台系统
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摘要
本文给出了一种数字视频展台的基于IZAS图像放大算法的设计方案。视频展台可将文档、图片、实物等信息转换成图像信号输出在投影机、监视器等显示设备上,广泛应用于教学、会议、产品展示等场合。
     传统的模拟展台图像不够清晰、画面抖动、图像质量受环境影响较大。为此,本文研究视频展台的图像处理方法和FPGA实现方案,并给出了基于FPGA的实际应用系统,有效的解决目前存在的问题。
     本文的主要内容为:
     (1)研究用FPGA实现图像实时放大的处理方法,选择能满足视频展台要求的缩放算法为研究对象,利用给定的放大比例寻找一个简单、易于实现且有较高精度的核函数。对核函数连续模型重新采样得到放大后的像素值。采用滤波器结构进行计算仅使用FPGA内部的3个双端口RAM缓冲图像数据,将原图像有效分辨率为738×575放大到1024×768。
     (2)给出一种基于色空变换的色彩调制方法,将图像传感器输出的PAL制数字YUV(4:2:2)格式信号换成RGB(5:6:5)格式。
     (3)设计一种针对视频展台的更为简洁的隔行转逐行扫描的实现方案,仅使用一块SDRAM作为帧缓存,利用场间插值算法,并将帧率由25Hz提升到60Hz。
     (4)FPGA完成了光学镜头中步进电机的驱动;同时实现了PS/2鼠标的驱动及其显示、图像冻结、负片显示、图像\文本选择、黑白\彩色图像言袷涑龅裙δ堋?
     上述实现的功能在ISE8.1开发环境下,采用VHDL语言描述,并在Xilinx(赛灵思)公司Spartan3E系列FPGA XC3S250E上实现。
The paper brought forward a new design of digital video presenter on baseof FPGA. The video presenter converts manuscript, picture, object andinformationin in other forms into image signal and outputs to projecter, monitorand other display equipment. Therefore it owns such a large utilization in fieldsof education, conference, product presention and so on. Whileconventioanl Analog video prenster is not satisfied for its unclear and non-stableand glint picture, furthermore its image is remarkbaly subject to the enviroment.In this thesis, the reserch focused on image processing technique and the FPGArealization along with an application system based on FPGA and thus solvingthe problems.
     Firstly, the technique of image real-time magnification by FPGA is adopted in this research. The zoom arithmetic which could fulfill the demands of the video presenter is chosen to be the research objects. By using the assured zoom scale search a simple,higher precision core function of easily implementing. Re-sampling to its continuity model can obtain the zoomed pixel value and then the original image will be effectively magnified from 738x575 to 1024x768, just using 3 double port RAM embedded in the FPGA as the image signal buffers.
     Secondly, The PAL format YUV(4:2:2) signal from image sensor, a kind of measure of colour space transformation is used in, then is converted into RGB(5:6:5) format.
     Thirdly, the paper also carried out a kind of more compact scheme for video presenter which could transform interleved scan into linered scan, just by using one SDRAM as frame buffers, the image signal is de-interlaced with the field interpolation algorithm and the frame rate is speed up to 60Hz from 25Hz.
     At the same time, in FPGA, realizes the driving to optic lens'step motor and PS/2 mouse, so the mouse cursor can be displayed on the screen. It also realizes the function of image freezing, negative image display, color/black switching and image/text switching. The whole design is written in VHDL, and it is fulfilled in the Xilinx Spartan3E series FPGA XC3S250E with the developing environment of ISE8.1.
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