PXI示波器DDR SDRAM控制器的设计
摘要
存储器的性能在很多数字化系统中占据着重要的地位,是决定系统性能的关键之一。DDR SDRAM具有容量大、读写速度快、运行稳定性强、技术成熟以及高性价比等优点,得到了广泛的应用。因而对DDR SDRAM存储控制器的研究具有重要的意义。
本文研究设计的DDR SDRAM控制器主要应用于PXI高速虚拟数字示波器。由于该示波器对数据的存取速度有着很高的要求,读写速度要求达到2Gbyte/s。虽然DDR SDRAM可以进行高速数据的读写,但是由于本身时序及控制操作的复杂性,要想达到2Gbyte/s的读写速度,就对控制器的设计提出了更高的要求。传统的DDR SDRAM控制器一般采用MCU,DSP实现,由于它们本身集成的资源有限,对于设计复杂的数字系统,实现高速存储就会很困难。为了达到2Gbyte/s的读写速度,本文提出了新的控制器设计思想,即用FPGA对DDR SDRAM的四个BANK进行循环控制,同一时刻保证会有一个BANK是在存取数据,通过对四片DDR SDRAM同时进行如上操作,进而达到2Gbyte/s的数据读写速率。
本文主要进行了如下工作,首先对DDR SDRAM控制器设计的基本理论和关键技术进行了研究和分析。并对DDR SDRAM的控制器的硬件部分进行了设计实现。接着对DDR SDRAM控制器的控制部分用硬件描述语言VHDL,采用自顶向下(Top-To-Down)的设计思想和模块化的设计方法,对控制器进行模块化设计,最后对设计进行仿真,并对硬件电路进行了测试验证。验证得到的信号仿真波形显示本控制器的设计满足本设计系统的需要。
The performance of memory is important in many digital systems, it mostly determines the system performance. The DDR SDRAM characterized by large memory capacity, high access speed, good stability, mature technology and high cost-effective, and it has been widely used in many storage systems.
In this paper, the DDR SDRAM controller is mainly used in the PXI digital virtual oscilloscope, and it requests high speed data access, which needs to achieve 2Gbyte/s.Although the DDR SDRAM has High-speed access rate, the timing and control operation are very complex, so it needs a higher request to the design of the controller. The design of traditional DDR SDRAM controller is mostly based on MCU and DSP, but it is difficult to achieve high-speed storage in the complex digital systems for their own limited resources which have been integrated inside. And for that reason, this paper presents a new controller design; it controls the four BANK of DDR SDRAM circularly with FPGA at the same time, and ensures that there will be one BANK at least in reading or writing process. Then do the same operation to four DDR SDRAM at the same time, and eventually we will reach the request of rate about 2Gbyte/s.
The paper has done the following work. Firstly, it has researched the basic theories and key technologies of DDR SDRAM controller design. Secondly, it has designed the hardware part of the controller, and it is mostly about the peripheral circuits. Thirdly, it has completed the design about control section of DDR SDRAM controller with hardware description language VHDL, which used the design idea of Top-To-Down and modular design method. And finally it has done simulation to the design and tested the hardware, and the wave of the simulation shows that the design completely meets the request of the design system.
本文研究设计的DDR SDRAM控制器主要应用于PXI高速虚拟数字示波器。由于该示波器对数据的存取速度有着很高的要求,读写速度要求达到2Gbyte/s。虽然DDR SDRAM可以进行高速数据的读写,但是由于本身时序及控制操作的复杂性,要想达到2Gbyte/s的读写速度,就对控制器的设计提出了更高的要求。传统的DDR SDRAM控制器一般采用MCU,DSP实现,由于它们本身集成的资源有限,对于设计复杂的数字系统,实现高速存储就会很困难。为了达到2Gbyte/s的读写速度,本文提出了新的控制器设计思想,即用FPGA对DDR SDRAM的四个BANK进行循环控制,同一时刻保证会有一个BANK是在存取数据,通过对四片DDR SDRAM同时进行如上操作,进而达到2Gbyte/s的数据读写速率。
本文主要进行了如下工作,首先对DDR SDRAM控制器设计的基本理论和关键技术进行了研究和分析。并对DDR SDRAM的控制器的硬件部分进行了设计实现。接着对DDR SDRAM控制器的控制部分用硬件描述语言VHDL,采用自顶向下(Top-To-Down)的设计思想和模块化的设计方法,对控制器进行模块化设计,最后对设计进行仿真,并对硬件电路进行了测试验证。验证得到的信号仿真波形显示本控制器的设计满足本设计系统的需要。
The performance of memory is important in many digital systems, it mostly determines the system performance. The DDR SDRAM characterized by large memory capacity, high access speed, good stability, mature technology and high cost-effective, and it has been widely used in many storage systems.
In this paper, the DDR SDRAM controller is mainly used in the PXI digital virtual oscilloscope, and it requests high speed data access, which needs to achieve 2Gbyte/s.Although the DDR SDRAM has High-speed access rate, the timing and control operation are very complex, so it needs a higher request to the design of the controller. The design of traditional DDR SDRAM controller is mostly based on MCU and DSP, but it is difficult to achieve high-speed storage in the complex digital systems for their own limited resources which have been integrated inside. And for that reason, this paper presents a new controller design; it controls the four BANK of DDR SDRAM circularly with FPGA at the same time, and ensures that there will be one BANK at least in reading or writing process. Then do the same operation to four DDR SDRAM at the same time, and eventually we will reach the request of rate about 2Gbyte/s.
The paper has done the following work. Firstly, it has researched the basic theories and key technologies of DDR SDRAM controller design. Secondly, it has designed the hardware part of the controller, and it is mostly about the peripheral circuits. Thirdly, it has completed the design about control section of DDR SDRAM controller with hardware description language VHDL, which used the design idea of Top-To-Down and modular design method. And finally it has done simulation to the design and tested the hardware, and the wave of the simulation shows that the design completely meets the request of the design system.
引文
1陈昊. DDR存储控制器的设计与应用.国防科技大学硕士论文. 2006.03: 1~5.
2石振明,王成,陈蜀宇.基于FPGA的DDR SDRAM控制器设计.微处理机. 2008.6: 22~23.
3张楠,张佩衍,刘新春,江先阳.基于FPGA的DDR SDRAM控制器设计与实现.计算机工程与应用. 2006(24): 89~93.
4 JEDEC DDR SDRAM SPECIFICATION. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, 2006: 1~7.
5 JEDEC solid state technology association, JEDEC STANDARD. DDRII SDRAM specification, Jan 2005: 2~14.
6 Micron technology Inc, 1GB、2GB、512Mb DDRII SDRAM datasheet,2004.
7 256Mb H-die DDR SDRAM Specification. Samsung Electronics. January 2006: 2~24
8 http://www.jedec.org/.
9 Rufino Olay. Designing a Spartan-3 FPGA DDR Memory Interface.. Xcell Journal. Second Quarter 2005.
10 Denali Software, Inc, Denali Databahn Memory Controller, 2005.
11 Burchardt A, Hekstra-Nowacka E, Chauhan A. A real-time streaming memory controller. Proceedings Design of Automation and Test in Europe. 2005(3): 20~25.
12 Zude Zhou, Songlin Cheng, Quan Liu. Application of DDR Controller for High-speed Data Acquisition Board. First International Conference on Innovative Computing. Information and Control. 2006: 611~614.
13 Zhang Bo, Zhang Gang. Research on Dual-Processor Sharing Pair of Symmetric DRAM. Second International Conference on Intelliqent Computation Technology and Automation. 2009: 138~141.
14 Xie Yizhuang, Long Teng. Implementation of two dimensional pulse compression based on embedded processor in FPGA. Radar Conference, 2009 IET International Publication Vear 2009: 1~4.
15 Donchev B, Kuzmanov G, Gaydadjiev G.N. External Memory Controller for Virtex II Pro. International Symposium on System-on-chip. 2006: 1~4.
16 Jinqiu Xiao, Xinglong Wang, Yi Feng. High-speed real-time data acquisition system based on FPGA. International Conference on Electronic Measurement & Instruments. 2009: 378~381.
17 Whitty S, Ernst R. A bandwidth optimized SDRAM controller for theMORPHEUS reconfigurable architecture. IEEE International Symposium on Parallel and Distributed Processing. 2008: 1~8.
18 GUO Li, ZHAN G Ying. The Feature of ddr SDRAM and the Implementation of ddr SDRAM Controllers via VHDL. School of Information Engineering, Beijing University of Posts and Telecommunications, Mar.2002: 2~9.
19 Jie Guo. Yibing Shi, Zhigang Wang. A Novel Design of DDR-based Data Acquisition Storage Module in a Digitizer. International Conference on Communications of Circuits and Systems. 2007: 995~998.
20朱明强.基于微处理器及CPLD的数字存储示波器的研究与实现.北京交通大学硕士论文. 2008.06.
21詹赞.基于虚拟仪器思想的数字存储示波器系统的研究与实现.武汉科技大学硕士论文. 2002: 1~7.
22秦云川,徐大令,李彤.测量仪器总线技术的发展与现状[J].中国仪器仪表. 2005(8): 48-52.
23赵会兵.虚拟仪器技术规范与系统集成.清华大学出版社. 2003: 1~123.
24美国国家仪器(NI)有限公司.虚拟仪器白皮书.美国国家仪器(NI)有限公司. 2006: 1~34.
25 EIDSON J C. IEEE 1588. Applications in Measurement. Control and Communication. 2005.
26 TC9 -Technical Committee on Sensor Technology, 1588 IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems.2002.
27 Zhao B. High speed DDR memory interface design. IEEE 8th International Conference on Digutal Object Identifier. 2009: 11.
28 Chen Shuangyan, Wang Donghui, Shan Rui, Hou Chao-huan. An innovative design of the DDR/DDR2 SDRAM compatible controller. 6th International Conference On ASIC. 2005: 62~66.
29 Fleming Patrick, Ostropolski Pawel, Algorithm for adjustment of DDR write interface timing. IET Irish of Signal and Systems Conference. 2008: 216~219.
30 Altera Corporation. DDR SDRAM Controller White Paper. 2000: 1~19.
31 Changsik Yoo. High Speed DRAM Interface.DRAM Desugn 3, Samsung Samsung Electronics. DDR SDRAM Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die with 64/72-bit ECC/.Korea: Samsung Electronics, October.2004.
32 Altera Corporation. DDR&DDR2 SDRAM Controller Compiler User Guide. Altera Corporation, April 2005.
33 HOJUN SHIM, YONGSOO JOO. Low-Energy Off-Chip SDRAM MemorySystems for Embedded Applications. Seoul National University, February. 2003.
34 Takeshi Hamamoto, Satoshi Kawasaki. A skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs. VLSI Development Center, Mitsubishi Electric Corporation, 2000.
35谭博学,苗汇静.集成电路原理及应用.电子工业出版社, 2008: 1~8.
36姜岩峰.集成电路设计实例.电子工业出版社, 2008: 3~12.
37刘福奇. FPGA嵌入式项目开发实战.电子工业出版社. 2009: 3~42.
38罗力帆,常春藤.基于VHDL的FPGA开发快速入门.技巧.实例.人民邮电出版社. 2009: 1~13.
39潘松,王国栋. VHDL实用教程.电子科技大学出版社. 2001: 1~180.
40 IEEE standard VHDL hardware description language. IEEE computer society. IEEE.NY, IEEE std 1364-2001.
41刘韬,楼兴华. FPGA数字系统设计与开发实例导航.人民邮电出版社, 2005.
42 Douglas L. Perry. VHDL编程实例.杨承恩,谭克俊,颜德文译.第四版.电子工业出版社. 2009: 24~32.
43张延鹏,张芝贤,尹常永. VHDL与可编程器件的应用.航空工业出版社. 2006: 1~266.
44陈耀和. VHDL语言设计技术.电子工业出版社. 2005:7~30.
45侯伯亨,顾新. VHDL硬件描述语言与数字逻辑电路设计.第二版.西安电子科技大学出版社.2002: 1~119
46周祖成. VHDL电子设计硬件描述语言.清华大学出版社. 1994: 1~200.
47 http://www.micron.com/.
48 Wayne Wolf. FPGA-based system design. China Machine Press, 2005.
49 Altera公司. ASIC设计可选方案:运用低成本FPGA进行系统集成.世界电子元器件. 2004.
50 High-Speed Board Layout Guidelines. Altera Corporation. August 2009:1~10, 23~25.
51 Edward Chan, Chee Yee Chung. High speed DDR performance in 4 vs 6 layer FCBGA package design. NVIDIA Corp, 2005.
52王诚,吴继华,范丽珍,薛宁,薛小刚. Altera FPGA/CPLD设计(基础篇).人民邮电出版社. 2008: 7~27.
53 Cyclone III Device Handbook, Volume1. Altera Corporation. October 2008: 16~84.
2石振明,王成,陈蜀宇.基于FPGA的DDR SDRAM控制器设计.微处理机. 2008.6: 22~23.
3张楠,张佩衍,刘新春,江先阳.基于FPGA的DDR SDRAM控制器设计与实现.计算机工程与应用. 2006(24): 89~93.
4 JEDEC DDR SDRAM SPECIFICATION. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, 2006: 1~7.
5 JEDEC solid state technology association, JEDEC STANDARD. DDRII SDRAM specification, Jan 2005: 2~14.
6 Micron technology Inc, 1GB、2GB、512Mb DDRII SDRAM datasheet,2004.
7 256Mb H-die DDR SDRAM Specification. Samsung Electronics. January 2006: 2~24
8 http://www.jedec.org/.
9 Rufino Olay. Designing a Spartan-3 FPGA DDR Memory Interface.. Xcell Journal. Second Quarter 2005.
10 Denali Software, Inc, Denali Databahn Memory Controller, 2005.
11 Burchardt A, Hekstra-Nowacka E, Chauhan A. A real-time streaming memory controller. Proceedings Design of Automation and Test in Europe. 2005(3): 20~25.
12 Zude Zhou, Songlin Cheng, Quan Liu. Application of DDR Controller for High-speed Data Acquisition Board. First International Conference on Innovative Computing. Information and Control. 2006: 611~614.
13 Zhang Bo, Zhang Gang. Research on Dual-Processor Sharing Pair of Symmetric DRAM. Second International Conference on Intelliqent Computation Technology and Automation. 2009: 138~141.
14 Xie Yizhuang, Long Teng. Implementation of two dimensional pulse compression based on embedded processor in FPGA. Radar Conference, 2009 IET International Publication Vear 2009: 1~4.
15 Donchev B, Kuzmanov G, Gaydadjiev G.N. External Memory Controller for Virtex II Pro. International Symposium on System-on-chip. 2006: 1~4.
16 Jinqiu Xiao, Xinglong Wang, Yi Feng. High-speed real-time data acquisition system based on FPGA. International Conference on Electronic Measurement & Instruments. 2009: 378~381.
17 Whitty S, Ernst R. A bandwidth optimized SDRAM controller for theMORPHEUS reconfigurable architecture. IEEE International Symposium on Parallel and Distributed Processing. 2008: 1~8.
18 GUO Li, ZHAN G Ying. The Feature of ddr SDRAM and the Implementation of ddr SDRAM Controllers via VHDL. School of Information Engineering, Beijing University of Posts and Telecommunications, Mar.2002: 2~9.
19 Jie Guo. Yibing Shi, Zhigang Wang. A Novel Design of DDR-based Data Acquisition Storage Module in a Digitizer. International Conference on Communications of Circuits and Systems. 2007: 995~998.
20朱明强.基于微处理器及CPLD的数字存储示波器的研究与实现.北京交通大学硕士论文. 2008.06.
21詹赞.基于虚拟仪器思想的数字存储示波器系统的研究与实现.武汉科技大学硕士论文. 2002: 1~7.
22秦云川,徐大令,李彤.测量仪器总线技术的发展与现状[J].中国仪器仪表. 2005(8): 48-52.
23赵会兵.虚拟仪器技术规范与系统集成.清华大学出版社. 2003: 1~123.
24美国国家仪器(NI)有限公司.虚拟仪器白皮书.美国国家仪器(NI)有限公司. 2006: 1~34.
25 EIDSON J C. IEEE 1588. Applications in Measurement. Control and Communication. 2005.
26 TC9 -Technical Committee on Sensor Technology, 1588 IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems.2002.
27 Zhao B. High speed DDR memory interface design. IEEE 8th International Conference on Digutal Object Identifier. 2009: 11.
28 Chen Shuangyan, Wang Donghui, Shan Rui, Hou Chao-huan. An innovative design of the DDR/DDR2 SDRAM compatible controller. 6th International Conference On ASIC. 2005: 62~66.
29 Fleming Patrick, Ostropolski Pawel, Algorithm for adjustment of DDR write interface timing. IET Irish of Signal and Systems Conference. 2008: 216~219.
30 Altera Corporation. DDR SDRAM Controller White Paper. 2000: 1~19.
31 Changsik Yoo. High Speed DRAM Interface.DRAM Desugn 3, Samsung Samsung Electronics. DDR SDRAM Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die with 64/72-bit ECC/.Korea: Samsung Electronics, October.2004.
32 Altera Corporation. DDR&DDR2 SDRAM Controller Compiler User Guide. Altera Corporation, April 2005.
33 HOJUN SHIM, YONGSOO JOO. Low-Energy Off-Chip SDRAM MemorySystems for Embedded Applications. Seoul National University, February. 2003.
34 Takeshi Hamamoto, Satoshi Kawasaki. A skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs. VLSI Development Center, Mitsubishi Electric Corporation, 2000.
35谭博学,苗汇静.集成电路原理及应用.电子工业出版社, 2008: 1~8.
36姜岩峰.集成电路设计实例.电子工业出版社, 2008: 3~12.
37刘福奇. FPGA嵌入式项目开发实战.电子工业出版社. 2009: 3~42.
38罗力帆,常春藤.基于VHDL的FPGA开发快速入门.技巧.实例.人民邮电出版社. 2009: 1~13.
39潘松,王国栋. VHDL实用教程.电子科技大学出版社. 2001: 1~180.
40 IEEE standard VHDL hardware description language. IEEE computer society. IEEE.NY, IEEE std 1364-2001.
41刘韬,楼兴华. FPGA数字系统设计与开发实例导航.人民邮电出版社, 2005.
42 Douglas L. Perry. VHDL编程实例.杨承恩,谭克俊,颜德文译.第四版.电子工业出版社. 2009: 24~32.
43张延鹏,张芝贤,尹常永. VHDL与可编程器件的应用.航空工业出版社. 2006: 1~266.
44陈耀和. VHDL语言设计技术.电子工业出版社. 2005:7~30.
45侯伯亨,顾新. VHDL硬件描述语言与数字逻辑电路设计.第二版.西安电子科技大学出版社.2002: 1~119
46周祖成. VHDL电子设计硬件描述语言.清华大学出版社. 1994: 1~200.
47 http://www.micron.com/.
48 Wayne Wolf. FPGA-based system design. China Machine Press, 2005.
49 Altera公司. ASIC设计可选方案:运用低成本FPGA进行系统集成.世界电子元器件. 2004.
50 High-Speed Board Layout Guidelines. Altera Corporation. August 2009:1~10, 23~25.
51 Edward Chan, Chee Yee Chung. High speed DDR performance in 4 vs 6 layer FCBGA package design. NVIDIA Corp, 2005.
52王诚,吴继华,范丽珍,薛宁,薛小刚. Altera FPGA/CPLD设计(基础篇).人民邮电出版社. 2008: 7~27.
53 Cyclone III Device Handbook, Volume1. Altera Corporation. October 2008: 16~84.