纳米集成电路软错误分析与缓解技术研究
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摘要
随着微电子制造工艺的发展,集成电路的特征尺寸逐渐缩小,目前已经进入纳米时代。纳米集成电路具有出色的性能、强大的功能和较低的功耗,广泛应用于电子通信、计算机、航空、航天、军事和消费电子等设备中。然而,纳米集成电路中不断降低的电源电压、越来越高的工作频率、持续减小的节点电容和高速增长的芯片复杂度使得电路对环境的影响越来越敏感。当电路受到高能粒子及外界噪声等干扰时,这些因素可能破坏芯片的内部状态,使集成电路发生错误。由于这种错误具有瞬态、随机和可恢复的特点,因此被称为“软错误”。
在纳米级工艺条件下,软错误是引起集成电路失效的主要原因。频繁发生的软错误将导致集成电路的可靠性降低,严重影响了系统的稳定性。随着工艺的进步,纳米集成电路中的软错误问题越来越突出,可能引起数据误差和运行错误,甚至导致整个系统崩溃。特别对于应用在航空、航天和军事等设备中的集成电路,由于所处环境复杂、可靠性要求很高,软错误问题更是设计中最严峻的挑战之一,需要采取特别措施进行保护。
本文面向纳米级工艺,深入研究了集成电路中软错误的分析和缓解技术。研究对象主要包括对集成电路整体软错误率影响较大且难以保护,或保护开销较大、成本较高的组成部件或电路结构。研究目的并不是要完全消除纳米集成电路中的软错误,而是希望以较低的代价尽可能缓解软错误对集成电路可靠性的影响,强调高效率、低开销的保护技术。本文针对以上内容展开研究,主要取得以下研究成果:
一、相联存储器软错误分析与缓解技术研究。相联存储器是集成电路中对软错误最敏感的部件之一,但是其结构特点决定了不能使用错误保护码等传统容错方法进行保护。论文分析了相联存储器中软错误发生的机理和概貌,研究了将稳定结构应用于相联存储器单元的加固方法,并提出两种基于双单元冗余的可靠单元结构——双单元反馈和双单元保持可靠CAM单元,以及一种基于双单元结构的错误保护机制——抛弃机制。针对相联存储器单元加固的限制,论文还提出一种基于三值匹配线的容软错误相联存储器结构,能够检测相联存储器中的任意一位错误,结构简单高效。实验表明,所提出的技术能够以较小的开销有效地缓解相联存储器中的软错误问题。
二、高效的时序电路软错误缓解技术研究。时序电路是集成电路的重要组成部分。在纳米级工艺下,时序电路对软错误变得非常敏感。传统基于冗余的加固方法虽然可以解决时序电路的软错误问题,但是加固效率较低,面积开销偏大。论文对不同结构寄存器的可靠性进行分析和比较,并设计了一种低开销的可靠动态寄存器DMTS-DR。论文还提出一种基于贪婪算法的时序电路敏感寄存器替换技术,只需将对电路软错误率影响最大的部分敏感寄存器替换为冗余寄存器,就能够有效降低电路的软错误率。针对贪婪算法有时不能达到可靠性和开销整体最优的局限,进一步提出可靠性-开销最优的启发式替换算法。实验表明,所提出的技术在可靠性和面积开销间达到了很好的折中,效率较高。
三、动态电路软错误易感性分析与优化技术研究。动态电路具有突出的性能优势,广泛应用于高速电路的设计中。然而动态电路对软错误非常敏感,严重限制了其应用。目前针对动态电路软错误问题的研究较少。论文分析了动态电路的软错误敏感性,并对软错误敏感性最高的几种情况推导出临界电荷的解析分析模型。针对该分析模型计算复杂性较大的问题,论文对模型进行适当近似,得到线性的简化模型,不仅可以用于手工分析动态电路的软错误易感性,还可降低自动化分析工具的计算量。基于简化分析模型的指导,论文提出五种动态电路软错误易感性优化技术,并进行分析和比较。实验表明,所提出的模型达到了较高的精度,优化技术在一定程度上缓解了动态电路软错误率较高的问题。
四、低开销的运算单元软错误缓解技术研究。运算单元是微处理器和集成电路中的核心元件,其正确性直接影响系统的可靠性。在纳米级工艺下,运算单元中的软错误将不可忽视。传统的运算单元软错误保护方法会带来较大的开销。针对这个问题,论文提出利用运算单元中大量存在的固有冗余资源进行容错而降低开销的方法,并以一个并行加法器为例研究具体的实现技术。论文提出了一种开发加法器中固有硬件和时间冗余资源用于容软错误的并行加法器结构STPA,并针对该结构研究了一种基于故障注入的高效软错误评估方法。实验表明,所提出的技术充分开发了电路的固有冗余资源,能够较好地缓解运算单元中的软错误问题,开销很小。
以上研究成果为分析和缓解纳米集成电路的软错误问题探索了一些可行的方法,为进一步提高纳米集成电路的可靠性提供了理论和实践基础。
With the technology scaling, the microelectronic manufacturing process has entered nanometer era. Because of its excellent performance and low power consumption, nanometer scale integrated circuits have been widely used in electronic communications, computer, aerospace, military and consumer electronics devices. On the other hand, due to the great reduction in supply, increasing frequency, continuous decreasing of node capacitances and the rapid growing of chip complexity, nanometer scale integrated circuits become more and more sensitive to the environment. When hit by high-energy particles or interfered by external noise, the nano-integrated circuits’internal state can be destroyed and this can further lead to the circuit error. Since this type of error is transient, random and recoverable, it is called“Soft Error”.
In nanometer technology, soft errors are the mainly reason for integrated circuits failure. Frequent occurrences of soft errors will lead to an unstable system and seriously affect the reliability of integrated circuits. To make things worse, soft error becomes more and more seriously as the technology scales down and can cause many problems, such as date corruption, execution error, and even system crash in the worst case. So it should be paid to enough attention, especially in the cases of aviation, aerospace and military which demands high reliability because of their poor environment. Nowadays, soft error becomes one of the most serious challenges which require particularly consideration.
This thesis mainly studies techniques of soft error analysis and mitigation in nanometer scale integrated circuits. This study primarily focuses on units or structures which are difficult or costly to protect and have a significant influence on the system soft error rate. The purpose of this thesis is not to completely eliminate soft errors in nanometer scale integrated circuits, but to develop a lower cost mitigation technique and enhance the system’s reliability, and to emphasize high efficiency and low overheads. The innovations of this thesis are as follows:
1. Soft error analysis and mitigation techniques of content addressable memories (CAM). In the integrated circuits, CAM is one of the most sensitive units to soft errors, but the traditional fault-tolerant technique, such as error-correcting coding techniques, can’t apply to it due to its special structure. To address the problem, after analyzing soft error mechanism and profile of CAMs, this thesis introduces a method that uses stable structure to enhance CAM cells. Furthermore, this thesis also introduces two reliable CAM cells and a soft error protection mechanism. The two structures, Dual Cell Feedback Reliable CAM and Dual Cell Keeping Reliable CAM, are based on dual cell redundancy. The mechanism called Ignore Mechanism is an fault protection scheme based on dual cell CAM structure. Due to the limitation of the CAM cell hardening, this thesis proposed a simple but effective soft error tolerant structure which is based on the triple-value match line and can detect any one bit error in the CAM. Experiment results show that the proposed techniques can effectively mitigate the soft error problem at the cost of very low overheads.
2. Cost effective soft error mitigation techniques of sequential circuits. Sequential circuits are an important component of the integrated circuits. In the nano-technology, the sequential circuit becomes very sensitive to soft errors. Although the traditional redundancy-based enhancing technique can migrate the soft error effectively, it brings considerable area overhead as well. This thesis firstly investigated the reliabilities of different register structures, and then designed a soft error immunity register, DMTS-DR. To mitigate the circuits’soft errors, a greedy-based sensitive register replacement algorithm is proposed. Its main idea is to replace the most sensitive registers with redundancy structures. Since the greedy algorithm is sometimes a sub-optimal solution, this thesis proposed another heuristic algorithm. Experimental results prove that the proposed techniques achieve a good trade-off between reliability and area overhead.
3. Soft error analysis and vulnerability optimization techniques of dynamic circuits. Dynamic circuits, owing to its outstanding performance, are widely used in high-speed circuit design. However, dynamic circuits are very sensitive to soft errors, and this severely limits its application. This thesis analyzes the soft error sensitivity of dynamic circuits, and develops an critical charge analytical model for some of the highest vulnerable cases. Due to the accurate analytical model is too complex to calculate, this thesis, by using an approximate method, finally present another simplified linear model which can be used both in the vulnerability analyzing and automatic CAD tools. Based on the analysis model above, five techniques are designed to mitigate soft error vulnerability of the dynamic circuits and each of them has been evaluated carefully. Experimental results demonstrate that the proposed model has high accuracy, and the optimization techniques can mitigate soft errors in dynamic circuits.
4. Low overheads soft error mitigation technique for arithmetic units. Arithmetic unit is the most important component both in the microprocessors and integrated circuits, and its validity may directly affects the system’s reliability. In nanometer technology, the soft errors in the arithmetic unit can’t be ignored. Since the tradition mitigation technique’s area overhead is too large, this thesis introduces the idea of exploiting the inherent redundancy resources to mitigate the soft errors. After investigating the inherent redundancy in the parallel adders, a soft error tolerant adder STPA was designed. An effective fault injection-based soft error estimation method is also proposed for the proposed adder. Experiments prove that the proposed structures sufficiently exploit the circuits’inherent reluctant resources and can effectively mitigate the soft errors problem of the arithmetic unit while only with small overheads.
To summary, this thesis provides an effective solution for the soft error problems in the nanometer scale circuits, and further gives a theory and practicable foundation to improve the reliability of the nanometer scale circuits.
在纳米级工艺条件下,软错误是引起集成电路失效的主要原因。频繁发生的软错误将导致集成电路的可靠性降低,严重影响了系统的稳定性。随着工艺的进步,纳米集成电路中的软错误问题越来越突出,可能引起数据误差和运行错误,甚至导致整个系统崩溃。特别对于应用在航空、航天和军事等设备中的集成电路,由于所处环境复杂、可靠性要求很高,软错误问题更是设计中最严峻的挑战之一,需要采取特别措施进行保护。
本文面向纳米级工艺,深入研究了集成电路中软错误的分析和缓解技术。研究对象主要包括对集成电路整体软错误率影响较大且难以保护,或保护开销较大、成本较高的组成部件或电路结构。研究目的并不是要完全消除纳米集成电路中的软错误,而是希望以较低的代价尽可能缓解软错误对集成电路可靠性的影响,强调高效率、低开销的保护技术。本文针对以上内容展开研究,主要取得以下研究成果:
一、相联存储器软错误分析与缓解技术研究。相联存储器是集成电路中对软错误最敏感的部件之一,但是其结构特点决定了不能使用错误保护码等传统容错方法进行保护。论文分析了相联存储器中软错误发生的机理和概貌,研究了将稳定结构应用于相联存储器单元的加固方法,并提出两种基于双单元冗余的可靠单元结构——双单元反馈和双单元保持可靠CAM单元,以及一种基于双单元结构的错误保护机制——抛弃机制。针对相联存储器单元加固的限制,论文还提出一种基于三值匹配线的容软错误相联存储器结构,能够检测相联存储器中的任意一位错误,结构简单高效。实验表明,所提出的技术能够以较小的开销有效地缓解相联存储器中的软错误问题。
二、高效的时序电路软错误缓解技术研究。时序电路是集成电路的重要组成部分。在纳米级工艺下,时序电路对软错误变得非常敏感。传统基于冗余的加固方法虽然可以解决时序电路的软错误问题,但是加固效率较低,面积开销偏大。论文对不同结构寄存器的可靠性进行分析和比较,并设计了一种低开销的可靠动态寄存器DMTS-DR。论文还提出一种基于贪婪算法的时序电路敏感寄存器替换技术,只需将对电路软错误率影响最大的部分敏感寄存器替换为冗余寄存器,就能够有效降低电路的软错误率。针对贪婪算法有时不能达到可靠性和开销整体最优的局限,进一步提出可靠性-开销最优的启发式替换算法。实验表明,所提出的技术在可靠性和面积开销间达到了很好的折中,效率较高。
三、动态电路软错误易感性分析与优化技术研究。动态电路具有突出的性能优势,广泛应用于高速电路的设计中。然而动态电路对软错误非常敏感,严重限制了其应用。目前针对动态电路软错误问题的研究较少。论文分析了动态电路的软错误敏感性,并对软错误敏感性最高的几种情况推导出临界电荷的解析分析模型。针对该分析模型计算复杂性较大的问题,论文对模型进行适当近似,得到线性的简化模型,不仅可以用于手工分析动态电路的软错误易感性,还可降低自动化分析工具的计算量。基于简化分析模型的指导,论文提出五种动态电路软错误易感性优化技术,并进行分析和比较。实验表明,所提出的模型达到了较高的精度,优化技术在一定程度上缓解了动态电路软错误率较高的问题。
四、低开销的运算单元软错误缓解技术研究。运算单元是微处理器和集成电路中的核心元件,其正确性直接影响系统的可靠性。在纳米级工艺下,运算单元中的软错误将不可忽视。传统的运算单元软错误保护方法会带来较大的开销。针对这个问题,论文提出利用运算单元中大量存在的固有冗余资源进行容错而降低开销的方法,并以一个并行加法器为例研究具体的实现技术。论文提出了一种开发加法器中固有硬件和时间冗余资源用于容软错误的并行加法器结构STPA,并针对该结构研究了一种基于故障注入的高效软错误评估方法。实验表明,所提出的技术充分开发了电路的固有冗余资源,能够较好地缓解运算单元中的软错误问题,开销很小。
以上研究成果为分析和缓解纳米集成电路的软错误问题探索了一些可行的方法,为进一步提高纳米集成电路的可靠性提供了理论和实践基础。
With the technology scaling, the microelectronic manufacturing process has entered nanometer era. Because of its excellent performance and low power consumption, nanometer scale integrated circuits have been widely used in electronic communications, computer, aerospace, military and consumer electronics devices. On the other hand, due to the great reduction in supply, increasing frequency, continuous decreasing of node capacitances and the rapid growing of chip complexity, nanometer scale integrated circuits become more and more sensitive to the environment. When hit by high-energy particles or interfered by external noise, the nano-integrated circuits’internal state can be destroyed and this can further lead to the circuit error. Since this type of error is transient, random and recoverable, it is called“Soft Error”.
In nanometer technology, soft errors are the mainly reason for integrated circuits failure. Frequent occurrences of soft errors will lead to an unstable system and seriously affect the reliability of integrated circuits. To make things worse, soft error becomes more and more seriously as the technology scales down and can cause many problems, such as date corruption, execution error, and even system crash in the worst case. So it should be paid to enough attention, especially in the cases of aviation, aerospace and military which demands high reliability because of their poor environment. Nowadays, soft error becomes one of the most serious challenges which require particularly consideration.
This thesis mainly studies techniques of soft error analysis and mitigation in nanometer scale integrated circuits. This study primarily focuses on units or structures which are difficult or costly to protect and have a significant influence on the system soft error rate. The purpose of this thesis is not to completely eliminate soft errors in nanometer scale integrated circuits, but to develop a lower cost mitigation technique and enhance the system’s reliability, and to emphasize high efficiency and low overheads. The innovations of this thesis are as follows:
1. Soft error analysis and mitigation techniques of content addressable memories (CAM). In the integrated circuits, CAM is one of the most sensitive units to soft errors, but the traditional fault-tolerant technique, such as error-correcting coding techniques, can’t apply to it due to its special structure. To address the problem, after analyzing soft error mechanism and profile of CAMs, this thesis introduces a method that uses stable structure to enhance CAM cells. Furthermore, this thesis also introduces two reliable CAM cells and a soft error protection mechanism. The two structures, Dual Cell Feedback Reliable CAM and Dual Cell Keeping Reliable CAM, are based on dual cell redundancy. The mechanism called Ignore Mechanism is an fault protection scheme based on dual cell CAM structure. Due to the limitation of the CAM cell hardening, this thesis proposed a simple but effective soft error tolerant structure which is based on the triple-value match line and can detect any one bit error in the CAM. Experiment results show that the proposed techniques can effectively mitigate the soft error problem at the cost of very low overheads.
2. Cost effective soft error mitigation techniques of sequential circuits. Sequential circuits are an important component of the integrated circuits. In the nano-technology, the sequential circuit becomes very sensitive to soft errors. Although the traditional redundancy-based enhancing technique can migrate the soft error effectively, it brings considerable area overhead as well. This thesis firstly investigated the reliabilities of different register structures, and then designed a soft error immunity register, DMTS-DR. To mitigate the circuits’soft errors, a greedy-based sensitive register replacement algorithm is proposed. Its main idea is to replace the most sensitive registers with redundancy structures. Since the greedy algorithm is sometimes a sub-optimal solution, this thesis proposed another heuristic algorithm. Experimental results prove that the proposed techniques achieve a good trade-off between reliability and area overhead.
3. Soft error analysis and vulnerability optimization techniques of dynamic circuits. Dynamic circuits, owing to its outstanding performance, are widely used in high-speed circuit design. However, dynamic circuits are very sensitive to soft errors, and this severely limits its application. This thesis analyzes the soft error sensitivity of dynamic circuits, and develops an critical charge analytical model for some of the highest vulnerable cases. Due to the accurate analytical model is too complex to calculate, this thesis, by using an approximate method, finally present another simplified linear model which can be used both in the vulnerability analyzing and automatic CAD tools. Based on the analysis model above, five techniques are designed to mitigate soft error vulnerability of the dynamic circuits and each of them has been evaluated carefully. Experimental results demonstrate that the proposed model has high accuracy, and the optimization techniques can mitigate soft errors in dynamic circuits.
4. Low overheads soft error mitigation technique for arithmetic units. Arithmetic unit is the most important component both in the microprocessors and integrated circuits, and its validity may directly affects the system’s reliability. In nanometer technology, the soft errors in the arithmetic unit can’t be ignored. Since the tradition mitigation technique’s area overhead is too large, this thesis introduces the idea of exploiting the inherent redundancy resources to mitigate the soft errors. After investigating the inherent redundancy in the parallel adders, a soft error tolerant adder STPA was designed. An effective fault injection-based soft error estimation method is also proposed for the proposed adder. Experiments prove that the proposed structures sufficiently exploit the circuits’inherent reluctant resources and can effectively mitigate the soft errors problem of the arithmetic unit while only with small overheads.
To summary, this thesis provides an effective solution for the soft error problems in the nanometer scale circuits, and further gives a theory and practicable foundation to improve the reliability of the nanometer scale circuits.
引文
[1] O’Gorman T J. The Effect of Cosmic Rays on the Soft Error Rate of a DRAM at Ground Level [J]. IEEE Transactions on Electron Devices, 1994, 41(4): 553~557.
[2] Mueller S M, Paul W J. Computer Architecture - Complexity and Correctness [M]. Springer, 2000.
[3] Colinge J P. Silicon-on-Insulator Technology: Materials to VLSI [M]. Kluwer Academic Publishers, 1997.
[4] Mahmoodi H, Tirumalashetty V, Cooke M, Roy K. Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 17(1): 33~44.
[5]王永文.高性能微处理器体系结构级功耗估算与优化技术研究[D].博士学位论文.长沙:国防科学技术大学,2004.
[6]张承义.超深亚微米微处理器漏流功耗的体系结构级优化技术研究[D].博士学位论文.长沙:国防科学技术大学,2006.
[7]周宏伟.微处理器中Cache漏流功耗的体系结构级优化技术研究[D].博士学位论文.长沙:国防科学技术大学,2007.
[8] Hennessy J L, Patterson D A. Computer Architecture: a Quantitative Approach [M]. Elsevier, 2007.
[9] Mukherjee M. Architecture Design for Soft Errors [M]. Elsevier, 2008.
[10] V?yrynen M. Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-On-Chips [D]. Link?ping: Link?ping University, 2009.
[11] Shivakumar P, Kistler M, Keckler S W, Burger D, Alvisi L. Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic [C]. Proceedings of the International Conference on Dependable Systems Networks, 2002: 389~398.
[12]龚锐.多核微处理器容软错误设计关键技术研究[D].博士学位论文.长沙:国防科学技术大学,2008.
[13] Mitra S, Seifert N, Zhang M, Shi Q, Kim K S. Robust System Design with Built-in Soft-Error Resilience [C]. IEEE Transactions on Computer, 2005, 38(2): 43~52.
[14] Mukherjee S S, Emer J S, Reinhardt S K. The Soft Error Problem: An Architectural Perspective [C]. Proceedings of 11th International Symposium on High-Performance Computer Architecture, 2005: 243~247.
[15] Mcnulty P J, Farrell G E, Wyatt R C. Upset Phenomena Induced by Energetic Protons and Electrons [J]. IEEE Transactions on Nuclear Science, 1980, 27(6):1516~152.
[16] Binder D, Smith E C, Holman A B. Satellite Anomalies from Galactic Cosmic Rays [J]. IEEE Transactions on Nuclear Science, 1975, 22(6): 2675~2680.
[17] May T C, Woods M H. Alpha-Particle-Induced Soft Errors in Dynamic Memories [J]. IEEE Transactions on Electronic Devices, 1979, 26(1): 2~9.
[18] Ziegler J F, Lanford W A. The Effect of Cosmic Rays on Computer Memories [J]. Science, 1979, 206(4420): 776~788.
[19] Zielger J F, Puchner H. SER—History, Trends and Challenges [R]. Cypress Semiconductor Corporation, 2004.
[20] Normand E. Single Event Upset at Ground Level [J]. IEEE Transactions on Nuclear Science, 1996, 43(6): 2742~2750.
[21] Baumann R, Hossain T, Smith E, Murata S, Kitagawa H. Boron as a Primary Source of Radiation in High Density DRAMs [C]. IEEE Symposium on VLSI, 1995: 81~82.
[22] Baumann R C. Soft Errors in Commereial Semiconductor Technology: Overview and Scaling Trends [C]. IEEE Reliability Physics Tutorial Notes, Reliablity Fundamentals, April 7, 2002.
[23] Michalak S E, Harris K W, Hengartner N W, Takala B E, Wender S A. Predicting the Number of Fatal Soft Errors in Los Alamos National Laboratory’s ASC Q Supercomputer [J]. IEEE Transactions on Device and Materials Reliability, 2005, 5(3): 329~335.
[24] Phelan R. Addressing Soft Errors in ARM Core-Based SOC [R]. ARM White Paper, 2003.
[25] Ando H, Yoshida Y, Inoue A, et al. A 1.3 GHz Fifth Generation SPARC64 Microprocessor [C]. Proceedings of Design Automation Conference, 2003: 702~705.
[26] Ziegler J F, Curtis H W, Muhlfeld H P, et al. IBM Experiments in Soft Fails in Computer Electronics (1978-1994) [J]. IBM Journal of Research and Development, 1996, 40(1): 3~18.
[27] Ziegler J F. Terrestrial Cosmic Rays [J]. IBM Journal of Research and Development, 1996, 40(1): 19~39.
[28] O’Gorman T J, Ross J M, Taber A H, et al. Field Testing for Cosmic Ray Soft Errors in Semiconductor Memories [J]. IBM Journal of Research and Development, 1996, 40(1): 41~50.
[29] Ziegler J F, Muhlfeld H P, Montrose C J, et al. Accelerated Testing for Cosmic Soft-Error Rate [J]. IBM Journal of Research and Development, 1996, 40(1): 51~72.
[30] Ziegler J F, Saunders P A, Zabel T H. Portable Faraday Cup for Nonvacuum Proton Beams [J]. IBM Journal of Research and Development, 1996, 40(1):73~76.
[31] Srinivasan G R. Modeling the Cosmic-Ray-Induced Soft-Error Rate in Integrated Circuits: an Overview [J]. IBM Journal of Research and Development, 1996, 40(1): 77~89.
[32] Tang H H K. Nuclear Physics of Cosmic Ray Interaction with Semiconductor Materials: Particle-Induced Soft Errors From A Physic [J]. IBM Journal of Research and Development, 1996, 40(1): 91~108.
[33] Murley P C, Srinivasan G R. Soft-Error Monte Carlo Modeling Program, SEMM [J]. IBM Journal of Research and Development, 1996, 40(1): 109~118.
[34] Freeman L B. Critical Charge Calculations for a Bipolar SRAM Array [J]. IBM Journal of Research and Development, 1996, 40(1): 119~129.
[35] Heidel D F, Rodbell K P, Cannon E H, et al. Alpha-Particle-Induced Upsets in Advanced CMOS Circuits and Technology [J]. IBM Journal of Research and Development, 2008, 52(3): 225~232.
[36] Tang H H K. SEMM-2: a New Generation of Single-Event-Effect Modeling Tools [J]. IBM Journal of Research and Development, 2008, 52(3): 233~244.
[37] Tang H H K, Murray C E, Fiorenza G, et al. New Simulation Methodology for Effects Of Radiation in Semiconductor Chip Structures [J]. IBM Journal of Research and Development, 2008, 52(3): 245~253.
[38] KleinOsowski A, Cannon E H, Oldiges P, Wissel L. Circuit Design and Modeling for Soft Errors [J]. IBM Journal of Research and Development, 2008, 52(3): 255~263.
[39] Gordon M S, Rodbell K P, Heidel D F, et al. Single-Event-Upset and Alpha-Particle Emission Rate Measurement Techniques [J]. IBM Journal of Research and Development, 2008, 52(3): 265~273.
[40] Sanda P N, Kellington J W, Kudva P, et al. Soft-Error Resilience of The IBM POWER6 Processor [J]. IBM Journal of Research and Development, 2008, 52(3): 275~284.
[41] Bender C, Sanda P N, Kudva P, et al. Soft-Error Resilience of The IBM POWER6 Processor Input/Output Subsystem [J]. IBM Journal of Research and Development, 2008, 52(3): 285~292.
[42] Rivers J A, Bose P, Kudva P, et al. Phaser: Phased Methodology for Modeling the System-Level Effects of Soft Errors [J]. IBM Journal of Research and Development, 2008, 52(3): 293~306.
[43] Dell T J. System RAS Implications of DRAM Soft Errors [J]. IBM Journal of Research and Development, 2008, 52(3): 307~314.
[44] http://www.iroctech.com/
[45] Baumann R C. Radiation-Induced Soft Errors in Advanced Semiconductor Technologies [J]. IEEE Transactions on Device and Materials Reliability, 2005,5(3): 305~316.
[46]梁斌.数字集成电路中单粒子瞬态脉冲的产生与传播[D].博士学位论文.长沙:国防科学技术大学,2008.
[47]傅忠传,陈红松,崔刚,杨孝宗.处理器容错技术研究与展望[J].计算机研究与发展,2007, 44(1): 154~160.
[48] Hazucha P, Karnik T, Maiz J, et al. Neutron Soft Error Rate Measurements in a 90-nm CMOS Process and Scaling Trends in SRAM from 0.25-μm to 90-nm Generation [C]. IEEE International Electron Devices Meeting (IEDM 2003), 2003: 21.5.1~21.5.4.
[49] Borkar S. Designing Reliable Systems From Unreliable Components: The Challenges of Transistor Variability and Degradation [J]. IEEE Micro, 2005, 25(6): 10~16.
[50]赵振宇.锁相环中单粒子瞬变效应的分析与加固[D].博士学位论文.长沙:国防科学技术大学,2009.
[51] Baumann R. Tutorial on Soft Errors [R]. International Reliability Physics Symposium (IRPS) Tutorial Notes, 2002.
[52] iRoC Technologies– The Soft Error Solution Answers to Frequently Asked Questions Regarding iRoC’s Testing Methodology For SRAM-based FPGAs, http://www.iroctech.com/pdf/Q&A_FPGA.pdf
[53] Pagiamtzis K, Azizi N, Najm F N. A Soft-Error Tolerant Content-Addressable Memory (CAM) using an Error-Correcting-Match Scheme [C]. IEEE Custom Integrated Circuits Conference, 2006: 301~304.
[54]闵应骅.容错计算二十五年[J].计算机学报,1995,18(12):930~943.
[55]黄正峰.数字电路软错误防护方法研究[D].博士学位论文.合肥:合肥工业大学,2009.
[56] Favalli M, Metra C. Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors [C]. Proceedings of Conference and Exhibition on Design, Automation and Test in Europe, 2001: 290~296.
[57] Unsal O S, Tschanz J W, Bowman K, et al. Impact of Parameter Variations on Circuits and Microarchitecture [J]. IEEE Transanctions on Micro, 2006, 26(6): 30~39.
[58]丁瑾.可靠性与可测性分析设计[M].北京:北京邮电大学出版社.1996.
[59] Weaver C, Emer J, Mukherjee S S, et al. Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor [C]. In Proceedings of International Symposium on Computer Architecture (ISCA’04), 2004: 264~275.
[60] Reis G A, Chang J, Vachharajani N, et al. Design and Evaluation of Hybrid Fault-Detection Systems [C]. In Proceedings of International Symposium onComputer Architecture (ISCA’05), 2005: 148~159.
[61] Hareland S, Maiz J, Alavi M, et al. Impact of CMOS Scaling and SOI on Soft Error Rates of Logic Processes [C]. In Digest of Technical Papers of Symposium on VLSI Technology, 2001: 73~74.
[62] Karnik T, Bloechel B, Soumyanath K, et al. Scaling Trends of Cosmic Rays Induced Soft Errors in Static Latches beyond 0.18μm [C]. In Digest of Technical Papers of Symposium on VLSI Technology, 2001: 61~62.
[63]刘必慰.集成电路单粒子效应建模与加固方法研究[D].博士学位论文.长沙:国防科学技术大学,2008.
[64] Grubin H L, Kreskovsky J P, Weinberg B C. Numerical Studies of Charge Collection and Funneling in Silicon Device [J]. IEEE Transactions on Nuclear Science, 1984, 31(6): 1161~1166.
[65] Hu C. Alpha-Particle-Induced Field and Enhanced Collection of Carriers [J]. IEEE Electron Device Letters, 1982, 3(2): 31~34.
[66] Srour J R, Long D M. Radiation Effects on and Dose Enhancement of Electronic Materials [M]. New Jersey: Noyes Publications, 1984.
[67] Compbell A B, Knudson A R, Shapiro P, et al. Charge Collection in Test Structures [J]. IEEE Transactions on Nuclear Science, 1983, 30(6): 4486~4492.
[68] Yamaguchi K, Takemura Y, Osada K, Saito Y. Bipolar-Mode Multibit Soft-Error-Mechanism Analysis of SRAMs by Three-Dimensional Device Simulation [J]. IEEE Transactions on Electron Devices, 2007, 54(11): 3007~3017.
[69] KleinOsowski A, Oldiges P, Williams R Q, Solomon P M. Modeling Single-Event Upsets in 65-nm Silicon-on-Insulator Semiconductor Devices [J]. IEEE Transactions on Nuclear Science, 2006, 53(6): 3321~3328.
[70] Srinivasan G R, Murley P C, Tang H K, et al. Accurate, Predictive Modeling of Soft Error Rate Due to Cosmic Rays and Chip Alpha Radiation [C]. IEEE International Reliability Physics Symposium, 1994: 12~16.
[71] Baze M, Buchner S. Attenuation of Single Event Induced Pulses in CMOS Combinational Logic [J]. IEEE Transactions on Nuclear Science, 1997, 44(6): 2217~2223.
[72] Chandra V, Aitken R. Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS [C]. IEEE Defect and Fault Tolerance of VLSI Systems, 2008: 114~122.
[73] Rossi D, Cazeaux J M, Omana M. Accurate Linear Model for SET Critical Charge Estimation [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 17(8): 1161~1166.
[74] Sun Y, Song C, Zhao Y L, Zhang M X. FAST: A Framework of AccurateSER-Estimation at Transistor-Level for Logic Circuits [C]. International Conference on Solid-State and Integrated Circuit Technology, 2010.
[75] Hazucha P, Svensson C. Impact of CMOS Technological Scaling on the Atmospheric Neutron Soft Error Rate [J]. IEEE Transactions on Nuclear Science, 2000, 47(6): 2586~2594.
[76] Wang F, Xie Y, Rajaraman R, Vaidyanathan B. Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model [C]. Proceedings of IEEE International Conference on VLSI Design (VLSID), 2007: 165~170.
[77] Wang N J, Quek J, Rafacz T M, et al. Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline [C]. 2004 International Conference on Dependable Systems and Networks, 2004: 61~67.
[78]黄海林,唐志敏,许彤.龙芯1号处理器的故障注入方法与软错误敏感性分析[J].计算机研究与发展, 2006, 43(10): 1820~1827.
[79] Nguyen H T, Yagil Y, Seifert N, Reitsma M. Chip-Level Soft Error Estimation Method [J]. IEEE Transactions on Device and Materials Reliability, 2005, 5(3): 365~381.
[80] Mukherjee S S, Weaver C, Emer J, et al. A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor [C]. Proceedings of 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003: 29~40.
[81] Biswas A, Racunas P, Cheveresan R, et al. Computing Architectural Vulnerability Factors for Address-Based Structures [C]. Proceedings of 32nd International Symposium on Computer Architecture, 2005: 532~543.
[82] Fu X, Li T, Fortes J. Sim-SODA: A Unified Framework for Architectural Level Software Reliability Analysis [C]. Workshop on Modeling, Benchmarking and Simulation (Held in conjunction with International Symposium on Computer Architecture), 2006.
[83] Biswas A, Racunas P, Emer J, Mukherjee S S. Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal [J]. IEEE Computer Architecture Letters, 2007, 7(1): 21~24.
[84] Li X, Adve S V, Bose P, et al. SoftArch: An Architecture-Level Tool for Modeling and Analyzing Soft Errors [C]. Proceedings of International Conference on Dependable Systems and Networks, 2005: 496~505.
[85] Reick K, Sanda P N, Swaney S, et al. Fault-Tolerant Design of the IBM POWER6 Microprocessor [J]. IEEE Micro, 2008, 28(2): 30~38.
[86] Santarini M. Cosmic Radiation Comes to ASIC and SOC Design. EDN Europe, 2005, http://www.edn.com/contents/images/529381.pdf
[87] Cannon E H, Reinhardt D D, Gordon M S, et al. SRAM SER in 90, 130 and 180 nm Bulk and SOI Technologies [C]. International Reliability Physics Symposium, 2004: 300~304.
[88] Karnik T, Vangal S, Veeramachaneni V, et al. Selective Node Engineering for Chip-Level Soft Error Rate Improvement [C]. 2002 Symposium on VLSI Circuits Digest of Technical Papers, 2002: 204~205.
[89] Mohanram K, Touba N A. Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits [C]. Proceedings of International Test Conference (ITC’03), 2003: 893~901.
[90] Gill B S, Papachristou C, Wolff F G, Seifert N. Node Sensitivity Analysis for Soft Errors in CMOS Logic [C]. International Test Conference, 2005: 1~9.
[91] Rockett L R. An SEU-Hardened CMOS Data Latch Design [C]. IEEE Transactions on Nuclear Science, 1988, 35(6): 1682~1687.
[92] Whitaker S, Canaris J, Liu K. SEU Hardened Memory Cells for a CCSDS Reed Solomn Encoder [J]. IEEE Transactions on Nuclear Science, 1991, 38(6): 1471~1477.
[93] Liu M N, Whitaker S. Low Power SEU Immune CMOS Memory Circuits [J]. IEEE Transactions on Nuclear Science, 1992, 39(6): 1679~1684.
[94] Bessot D, Velazco R. Design of SEU-Hardened CMOS Memory Cells: The HIT Cell [C]. the 2nd European Conference Radiation and Its Effects on Components and Systems. 1993: 563~570.
[95] Velazco R, Bessot D. Two CMOS Memory Cells Suitable for the Design of SEU-Tolerant VLSI Circuits [C]. IEEE Transactions on Nuclear Science, 1994, 41(6): 2229~2234.
[96] Haddad N, Rockett L, Doyle S. Design Considerations for Next Generation Radiation Hardened SRAMs for Space Applications [C]. 2005 IEEE Aerospace Conference, 2005: 1~6.
[97] Calin T, Nicolaidis M, Velazco R. Upset Hardened Memory Design for Submicron CMOS Technology [J]. IEEE Transactions on Nuclear Science, 1996, 43(6): 2874~2878.
[98]刘必慰,陈书明,梁斌.一种低功耗的SEU加固存储单元[J].半导体学报,2007, 28(5): 755~758.
[99] Gong R, Chen W, Liu F, et al, A New Approach to Single Event Effect Tolerance based on Asynchronous Circuit Technique [J]. Journal of Electronic Testing: Theory and Applications (JETTA), 2008, 24(1): 57~65.
[100] Gong R, Chen W, Liu F, et al. Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique [C]. In Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT’06), 2006: 184~194.
[101] Mitra S, Zhang M, Waqas S, et al. Combinational Logic Soft Error Correction [C]. International Test Conference, 2006: 1~9.
[102] Sasaki Y, Namba K, Ito H, Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit [C]. the 21st International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’06), 2006: 327~335.
[103] Garg R, Jayakumar N, Khatri S P, et al. A Design Approach for Radiation-Hard Digital Electronics [C]. 43rd ACM/IEEE Design Automation Conference, 2006: 773~778.
[104] Michels A, Petroli L, Lisboa C A L, et al. SET Fault Tolerant Combinational Circuits Based on Majority Logic [C]. 21st International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’06), 2006: 345~352.
[105] Mohanram K, Touba N A. Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits [C], Proc of 18th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’03), 2003: 433~440.
[106] Miskov-Zivanov N, Marculescu D. MARS-C: Modeling and Reduction of Soft Errors in Combinational Circuits [C]. Proc of 43rd ACM/IEEE Design Automation Conference (DAC’06), 2006: 767~772.
[107] Rao R R, Blaauw D, Sylvester D. Soft Error Reduction in Combinational Logic Using Gate Resizing and Flipflop Selection [C]. Proc of International Conference on Computer-Aided Design (ICCAD’06), 2006: 502~509.
[108] Hill E L, Lipasti M H, Saluja K K. An Accurate Flip-flop Selection Technique for Reducing Logic SER [C]. Proc of 38th International Conference on Dependable Systems and Networks (DSN’08), 2008: 128~136.
[109] Sridharan V, Asadi H, Tahoori M B, Kaeli D. Reducing Data Cache Susceptibility to Soft Errors [J]. IEEE Transactions on Dependable and Secure Computing, 2006, 3(4): 353~364.
[110] Zhang W. Computing Cache Vulnerability to Transient Errors and Its Implication [C]. 20th IEEE Defect and Fault Tolerance in VLSI Systems, 2005: 427~435.
[111] Wang S, Hu J, Ziavras S G. On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors [C]. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2006: 14~20.
[112] Kadayif I, Kandemir M. Modeling and Improving Data Cache Reliability [J]. ACM SIGMETRICS Performance Evaluation Review, 2007, 35(1): 1~12.
[113] Zhang W, Gurumurthi S, Kandemir M, et al. ICR: In-Cache Replication for Enhancing Data Cache Reliability [C]. International Conference on ependable Systems and Networks, 2003: 291~300.
[114] Zhang W. Replica Victim Caching to Improve Reliability of In-CacheReplication [J]. Lecture Notes in Computer Science, Advances in Computer Systems Architecture, 2004: 2~15.
[115] Zhang W. Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability [J]. IEEE Transactions on Computers, 2005, 54(12): 1547~1555.
[116] Zhang W, Kandemir M, Sivasubramaniam A, et al. Performance, Energy, and Reliability Tradeoffs in Replicating Hot Cache Lines [C]. International Conference on Compilers, Architecture and Synthesis for Embedded Systems, 2003: 309~317.
[117] Hu J, Wang S, Ziavras S G. In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability [C]. International Dependable Systems and Networks, 2006: 281~290.
[118] Akcicek D, Koyuncu S, Sen H, et al. Exploiting Potentially Dead Blocks for Improving Data Cache Reliability Against Soft Errors [C]. International Symposium on Computer and Information Sciences, 2007: 1~6.
[119]江建慧,员春欣.芯片级系统的在线测试技术[J].计算机研究与发展,2004, 41(9): 1593~1603.
[120] Oh N, Shirvani P P, McCluskey E J. Error Detection by Duplicated Instructions in Super-Scalar Processors [J]. IEEE Transactions on Reliability, 2002, 51(1): 63~75.
[121] Oh N, Mitra S, McCluskey E J. ED4I: Error Detection by Diverse Data and Duplicated Instructions [J]. IEEE Transactions on Computer, 2002, 51(2): 180~199.
[122] Ray J, Hoe J C, Falsafi B. Dual Use of Superscalar Datapath for ransient-Fault Detection and Recovery [C]. Proceedings of 34th Symposium on Microarchitecture (Micro-34), 2001: 214~224.
[123] Todd M. Austin, DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design [C]. 32nd Annual International Symposium on Microarchitecture (MICRO), 1999: 196~207.
[124] Rotenberg E. AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors [C]. In Proceedings of the 29th Fault-Tolerant Computing Symposium, 1999: 84~91.
[125] Smolens J C, Jangwoo Kim, Hoe J C, Babak Falsafi. Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures [C]. International Symposium on Microarchitecture (MICRO), 2004: 257~268.
[126] Vijaykumar T N, Pomeranz I, Cheng K. Transient-Fault Recovery Using Simultaneous Multithreading [C]. Proceedings of 29th International Symposium on Computer Architecture, 2002: 87~98.
[127] Mukherjee S, Kontz M Reinhardt S. Detailed Design and Evaluation of Redundant Multithreading Alternatives [C]. In International Symposium on Computer Architecture (ISCA), 2002: 99~110.
[128] Parashar A, Gurumurthi A, Sivasubramaniam A. A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy [C]. In Proceedings of the International Symposium on Computer Architecture (ISCA), 2004: 376~386.
[129] Gomaa M A, Vijaykumar T N. Opportunistic Transient-Fault Detection [C]. In Proceedings of the International Symposium on Computer Architecture (ISCA), 2005: 172~183.
[130] Fu X, Poe J, Li T, Fortes J. Characterizing Microarchitecture Soft Error Vulnerability Phase Behavior [C]. In Proceedings of the International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), 2006: 147~155.
[131] Walcott K R, Humphreys G, Gurumurthi S. Vulnerabilities Dynamic Prediction of Architectural Vulnerability from Microarchitectural State [C]. 32nd Annual International Symposium on Computer Architecture (ISCA), 2007: 516~527.
[132] Lin S, Yang H, Luo R. A New Family of Sequential Elements with Built-in Soft Error Tolerance for Dual-VDD Systems [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008, 16(10): 1372.
[133] Mupid A, Mutyam M, Vijaykrishnan N, et al. Variation Analysis of CAM Cells [C]. 8th International Symposium on Quality Electronic Design (ISQED’07), 2007: 333~338.
[134] Chaudhary V, Clark L T. Low-Power High-Performance NAND Match Line Content Addressable Memories [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006, 14(8): 895.
[135] Luong Dinh Hung. Soft-Error Tolerant Cache Architectures [D]. Tokyo: The University of Tokyo, 2006.
[136] Rabaey J M等著,周润德等译.数字集成电路——电路、系统与设计(第二版)[M].北京:电子工业出版社,2004.
[137] Heijmen T. Soft-Error Vulnerability of Sub-100-nm Flip-flops [C]. Proc 14th IEEE International On-Line Testing Symposium, 2008: 247~252.
[138] Rao R R, Chopra K, Blaauw D, Sylvester D. An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits [C]. Proc Design Automation and Test in Europe (DATE), 2006: 164~169.
[139] Naseer R, Boulghassoul Y, Draper J, DasGupta S, Witulski A. Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM [C]. International Symposium on Computer Architecture (ISCAS’07), 2007: 1879~1882.
[140] Gill B S, Papachristou C, Wolff F G. A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA [C]. Design, Automation and Test in Europe Conference and Exposition (DATE’07), 2007: 1~6.
[141] Mavis D, Eaton P. Soft Error Rate Mitigation Techniques for Modern Microcircuits [C]. Proc. of IEEE International Reliability Physics Symposium (IRPS), 2002: 216~225.
[142] Knudsen J E, Clark L T. An Area and Power Efficient Radiation Hardened by Design Flip-Flop [J]. IEEE Transactions on Nuclear Science, 2006, 53(6): 3392~3399.
[143] Chen M, Orailoglu A. Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements [C]. Proc. of 16th IEEE Asian Test Symposium, 2007: 307~312.
[144] Zhang M et al. A Soft Error Rate Analysis (SERA) Methodology [C]. Proc of International Conference on Computer-Aided Design (ICCAD’04), 2004: 111~118.
[145] Asadi G, Tahoori M B. An Accurate SER Estimation Method Based on Propagation Probability [C]. Proc of Design, Automation and Test in Europe (DATE’05), 2005: 306~307.
[146] Zhang B, Wang W S, Orshansky M. FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs [C]. Proc of 7th International Symposium on Quality Electronic Design (ISQED’06), 2006: 755~760.
[147] Miskov-Zivanov N, Marculescu D. Modeling and Optimization for Soft-Error Reliability of Sequential Circuits [J]. IEEE Trans. on CAD of Integrated Circuits and Systems, 2008, 27(5): 803~816.
[148] Holcomb D, Li W, Seshia S A. Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits [C]. Proc of Design Automation and Test in Europe (DATE’09), 2009: 785~790.
[149]周学海,余洁,李曦等.基于指令行为的Cache可靠性评估研究[J].计算机研究与发展, 2007, 44(4): 553-559
[150] Cornelius C, Grassert F, Koppe S, et al. Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques [C]. 20th International Conference on VLSI Design (Held jointly with 6th International Conference on Embedded Systems), 2007: 330~338.
[151] Kumar J, Tahoori M B. A Low Power Soft Error Suppression Technique for Dynamic Logic [C]. 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2005: 454~462.
[152] Cha H, Patel J H. A Logic-Level Model forα-Particle Hits in CMOS Circuits [C]. IEEE International Conference Computer Design 1993: 538~542.
[153] Naseer R, Draper J, Boulghassoul Y, et al. Critical Charge and SET Pulse Widths for Combinational Logic in Commercial 90nm CMOS Technology [C]. Proceedings of the 17th Great Lakes Symposium on VLSI, 2007: 227~230.
[154] Wilkinson J, Hareland S. A Cautionary Tale of Soft Errors Induced by SRAM Packaging Materials [J]. IEEE Transactions on Device and Materials Reliability, 2005, 5(3): 428~433.
[155] Baumann R. The Impact of Technology Scaling on Soft Error Rate Performance and Limts to the Efficacy of Error Correction [C]. International Electron Devices Meeting, 2002: 329~332.
[156] Mitra S, Zhang M, Mak T M, et al. Logic Soft Errors: A Major Barrier to Robust Platform Design [C]. IEEE International Test Conference, 2005: 687~696.
[157] Lyons R E, Vanderkulk W. The Use of Triple Modular Redundancy to Improve Computer Reliability [J]. IBM Journal of Research and Development, 1962, 6(2): 200~209.
[158] Shah J S. Design of Soft Error Robust High Speed 64-bit Logarithmic Adder [D]. Master thesis, University of Waterloo, 2008.
[159] Kogge P, Stone H. A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Relations [J]. IEEE Trans. Computers, 1973, C-22(8): 786~793.
[160] Dimitrakopoulos G, Nikolos D. High-Speed Parallel-Prefix VLSI Ling Adders [J]. IEEE Transactions on Computers, 2005, 54(2): 225~231.
[161]李兆麟,盛世敏,吉利久,王阳元.基于单元故障模型的树型加法器的测试[C].计算机学报,2003, 26(11): 1494~1501.
[162]孙岩.高性能算术逻辑部件研究与全定制设计[D].硕士学位论文.长沙:国防科学技术大学.2005.
[163] Ndai P, Lu S L, Somesekhar D, et al. Fine-Grained Redundancy in Adders [C]. 8th International Symposium on Quality Electronic Design, 2007: 317~321.
[164] Sun Y, Zheng D Y, Zhang M X, et al. High Performance Low-Power Sparse-Tree Binary Adders [C]. 8th International Conference on Solid-State and Integrated Circuit Technology, 2006: 1649~1651.
[165] Mesquita E, Franck H, Agostini L, et al. Soft Error Tolerant Carry-Select Adders Implemented Into Altera FPGAs [C]. 3rd Southern Conference on Programmable Logic, 2007: 199~202.
[166] Zhou Q, Mohanram K. Gate Sizing to Radiation Harden Combinational Logic [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006: 155~166.
[167] Bushnell M L. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits [M]. Boston/Dordrecht/London : Kluwer Academic Publishers, 2000.
[2] Mueller S M, Paul W J. Computer Architecture - Complexity and Correctness [M]. Springer, 2000.
[3] Colinge J P. Silicon-on-Insulator Technology: Materials to VLSI [M]. Kluwer Academic Publishers, 1997.
[4] Mahmoodi H, Tirumalashetty V, Cooke M, Roy K. Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 17(1): 33~44.
[5]王永文.高性能微处理器体系结构级功耗估算与优化技术研究[D].博士学位论文.长沙:国防科学技术大学,2004.
[6]张承义.超深亚微米微处理器漏流功耗的体系结构级优化技术研究[D].博士学位论文.长沙:国防科学技术大学,2006.
[7]周宏伟.微处理器中Cache漏流功耗的体系结构级优化技术研究[D].博士学位论文.长沙:国防科学技术大学,2007.
[8] Hennessy J L, Patterson D A. Computer Architecture: a Quantitative Approach [M]. Elsevier, 2007.
[9] Mukherjee M. Architecture Design for Soft Errors [M]. Elsevier, 2008.
[10] V?yrynen M. Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-On-Chips [D]. Link?ping: Link?ping University, 2009.
[11] Shivakumar P, Kistler M, Keckler S W, Burger D, Alvisi L. Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic [C]. Proceedings of the International Conference on Dependable Systems Networks, 2002: 389~398.
[12]龚锐.多核微处理器容软错误设计关键技术研究[D].博士学位论文.长沙:国防科学技术大学,2008.
[13] Mitra S, Seifert N, Zhang M, Shi Q, Kim K S. Robust System Design with Built-in Soft-Error Resilience [C]. IEEE Transactions on Computer, 2005, 38(2): 43~52.
[14] Mukherjee S S, Emer J S, Reinhardt S K. The Soft Error Problem: An Architectural Perspective [C]. Proceedings of 11th International Symposium on High-Performance Computer Architecture, 2005: 243~247.
[15] Mcnulty P J, Farrell G E, Wyatt R C. Upset Phenomena Induced by Energetic Protons and Electrons [J]. IEEE Transactions on Nuclear Science, 1980, 27(6):1516~152.
[16] Binder D, Smith E C, Holman A B. Satellite Anomalies from Galactic Cosmic Rays [J]. IEEE Transactions on Nuclear Science, 1975, 22(6): 2675~2680.
[17] May T C, Woods M H. Alpha-Particle-Induced Soft Errors in Dynamic Memories [J]. IEEE Transactions on Electronic Devices, 1979, 26(1): 2~9.
[18] Ziegler J F, Lanford W A. The Effect of Cosmic Rays on Computer Memories [J]. Science, 1979, 206(4420): 776~788.
[19] Zielger J F, Puchner H. SER—History, Trends and Challenges [R]. Cypress Semiconductor Corporation, 2004.
[20] Normand E. Single Event Upset at Ground Level [J]. IEEE Transactions on Nuclear Science, 1996, 43(6): 2742~2750.
[21] Baumann R, Hossain T, Smith E, Murata S, Kitagawa H. Boron as a Primary Source of Radiation in High Density DRAMs [C]. IEEE Symposium on VLSI, 1995: 81~82.
[22] Baumann R C. Soft Errors in Commereial Semiconductor Technology: Overview and Scaling Trends [C]. IEEE Reliability Physics Tutorial Notes, Reliablity Fundamentals, April 7, 2002.
[23] Michalak S E, Harris K W, Hengartner N W, Takala B E, Wender S A. Predicting the Number of Fatal Soft Errors in Los Alamos National Laboratory’s ASC Q Supercomputer [J]. IEEE Transactions on Device and Materials Reliability, 2005, 5(3): 329~335.
[24] Phelan R. Addressing Soft Errors in ARM Core-Based SOC [R]. ARM White Paper, 2003.
[25] Ando H, Yoshida Y, Inoue A, et al. A 1.3 GHz Fifth Generation SPARC64 Microprocessor [C]. Proceedings of Design Automation Conference, 2003: 702~705.
[26] Ziegler J F, Curtis H W, Muhlfeld H P, et al. IBM Experiments in Soft Fails in Computer Electronics (1978-1994) [J]. IBM Journal of Research and Development, 1996, 40(1): 3~18.
[27] Ziegler J F. Terrestrial Cosmic Rays [J]. IBM Journal of Research and Development, 1996, 40(1): 19~39.
[28] O’Gorman T J, Ross J M, Taber A H, et al. Field Testing for Cosmic Ray Soft Errors in Semiconductor Memories [J]. IBM Journal of Research and Development, 1996, 40(1): 41~50.
[29] Ziegler J F, Muhlfeld H P, Montrose C J, et al. Accelerated Testing for Cosmic Soft-Error Rate [J]. IBM Journal of Research and Development, 1996, 40(1): 51~72.
[30] Ziegler J F, Saunders P A, Zabel T H. Portable Faraday Cup for Nonvacuum Proton Beams [J]. IBM Journal of Research and Development, 1996, 40(1):73~76.
[31] Srinivasan G R. Modeling the Cosmic-Ray-Induced Soft-Error Rate in Integrated Circuits: an Overview [J]. IBM Journal of Research and Development, 1996, 40(1): 77~89.
[32] Tang H H K. Nuclear Physics of Cosmic Ray Interaction with Semiconductor Materials: Particle-Induced Soft Errors From A Physic [J]. IBM Journal of Research and Development, 1996, 40(1): 91~108.
[33] Murley P C, Srinivasan G R. Soft-Error Monte Carlo Modeling Program, SEMM [J]. IBM Journal of Research and Development, 1996, 40(1): 109~118.
[34] Freeman L B. Critical Charge Calculations for a Bipolar SRAM Array [J]. IBM Journal of Research and Development, 1996, 40(1): 119~129.
[35] Heidel D F, Rodbell K P, Cannon E H, et al. Alpha-Particle-Induced Upsets in Advanced CMOS Circuits and Technology [J]. IBM Journal of Research and Development, 2008, 52(3): 225~232.
[36] Tang H H K. SEMM-2: a New Generation of Single-Event-Effect Modeling Tools [J]. IBM Journal of Research and Development, 2008, 52(3): 233~244.
[37] Tang H H K, Murray C E, Fiorenza G, et al. New Simulation Methodology for Effects Of Radiation in Semiconductor Chip Structures [J]. IBM Journal of Research and Development, 2008, 52(3): 245~253.
[38] KleinOsowski A, Cannon E H, Oldiges P, Wissel L. Circuit Design and Modeling for Soft Errors [J]. IBM Journal of Research and Development, 2008, 52(3): 255~263.
[39] Gordon M S, Rodbell K P, Heidel D F, et al. Single-Event-Upset and Alpha-Particle Emission Rate Measurement Techniques [J]. IBM Journal of Research and Development, 2008, 52(3): 265~273.
[40] Sanda P N, Kellington J W, Kudva P, et al. Soft-Error Resilience of The IBM POWER6 Processor [J]. IBM Journal of Research and Development, 2008, 52(3): 275~284.
[41] Bender C, Sanda P N, Kudva P, et al. Soft-Error Resilience of The IBM POWER6 Processor Input/Output Subsystem [J]. IBM Journal of Research and Development, 2008, 52(3): 285~292.
[42] Rivers J A, Bose P, Kudva P, et al. Phaser: Phased Methodology for Modeling the System-Level Effects of Soft Errors [J]. IBM Journal of Research and Development, 2008, 52(3): 293~306.
[43] Dell T J. System RAS Implications of DRAM Soft Errors [J]. IBM Journal of Research and Development, 2008, 52(3): 307~314.
[44] http://www.iroctech.com/
[45] Baumann R C. Radiation-Induced Soft Errors in Advanced Semiconductor Technologies [J]. IEEE Transactions on Device and Materials Reliability, 2005,5(3): 305~316.
[46]梁斌.数字集成电路中单粒子瞬态脉冲的产生与传播[D].博士学位论文.长沙:国防科学技术大学,2008.
[47]傅忠传,陈红松,崔刚,杨孝宗.处理器容错技术研究与展望[J].计算机研究与发展,2007, 44(1): 154~160.
[48] Hazucha P, Karnik T, Maiz J, et al. Neutron Soft Error Rate Measurements in a 90-nm CMOS Process and Scaling Trends in SRAM from 0.25-μm to 90-nm Generation [C]. IEEE International Electron Devices Meeting (IEDM 2003), 2003: 21.5.1~21.5.4.
[49] Borkar S. Designing Reliable Systems From Unreliable Components: The Challenges of Transistor Variability and Degradation [J]. IEEE Micro, 2005, 25(6): 10~16.
[50]赵振宇.锁相环中单粒子瞬变效应的分析与加固[D].博士学位论文.长沙:国防科学技术大学,2009.
[51] Baumann R. Tutorial on Soft Errors [R]. International Reliability Physics Symposium (IRPS) Tutorial Notes, 2002.
[52] iRoC Technologies– The Soft Error Solution Answers to Frequently Asked Questions Regarding iRoC’s Testing Methodology For SRAM-based FPGAs, http://www.iroctech.com/pdf/Q&A_FPGA.pdf
[53] Pagiamtzis K, Azizi N, Najm F N. A Soft-Error Tolerant Content-Addressable Memory (CAM) using an Error-Correcting-Match Scheme [C]. IEEE Custom Integrated Circuits Conference, 2006: 301~304.
[54]闵应骅.容错计算二十五年[J].计算机学报,1995,18(12):930~943.
[55]黄正峰.数字电路软错误防护方法研究[D].博士学位论文.合肥:合肥工业大学,2009.
[56] Favalli M, Metra C. Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors [C]. Proceedings of Conference and Exhibition on Design, Automation and Test in Europe, 2001: 290~296.
[57] Unsal O S, Tschanz J W, Bowman K, et al. Impact of Parameter Variations on Circuits and Microarchitecture [J]. IEEE Transanctions on Micro, 2006, 26(6): 30~39.
[58]丁瑾.可靠性与可测性分析设计[M].北京:北京邮电大学出版社.1996.
[59] Weaver C, Emer J, Mukherjee S S, et al. Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor [C]. In Proceedings of International Symposium on Computer Architecture (ISCA’04), 2004: 264~275.
[60] Reis G A, Chang J, Vachharajani N, et al. Design and Evaluation of Hybrid Fault-Detection Systems [C]. In Proceedings of International Symposium onComputer Architecture (ISCA’05), 2005: 148~159.
[61] Hareland S, Maiz J, Alavi M, et al. Impact of CMOS Scaling and SOI on Soft Error Rates of Logic Processes [C]. In Digest of Technical Papers of Symposium on VLSI Technology, 2001: 73~74.
[62] Karnik T, Bloechel B, Soumyanath K, et al. Scaling Trends of Cosmic Rays Induced Soft Errors in Static Latches beyond 0.18μm [C]. In Digest of Technical Papers of Symposium on VLSI Technology, 2001: 61~62.
[63]刘必慰.集成电路单粒子效应建模与加固方法研究[D].博士学位论文.长沙:国防科学技术大学,2008.
[64] Grubin H L, Kreskovsky J P, Weinberg B C. Numerical Studies of Charge Collection and Funneling in Silicon Device [J]. IEEE Transactions on Nuclear Science, 1984, 31(6): 1161~1166.
[65] Hu C. Alpha-Particle-Induced Field and Enhanced Collection of Carriers [J]. IEEE Electron Device Letters, 1982, 3(2): 31~34.
[66] Srour J R, Long D M. Radiation Effects on and Dose Enhancement of Electronic Materials [M]. New Jersey: Noyes Publications, 1984.
[67] Compbell A B, Knudson A R, Shapiro P, et al. Charge Collection in Test Structures [J]. IEEE Transactions on Nuclear Science, 1983, 30(6): 4486~4492.
[68] Yamaguchi K, Takemura Y, Osada K, Saito Y. Bipolar-Mode Multibit Soft-Error-Mechanism Analysis of SRAMs by Three-Dimensional Device Simulation [J]. IEEE Transactions on Electron Devices, 2007, 54(11): 3007~3017.
[69] KleinOsowski A, Oldiges P, Williams R Q, Solomon P M. Modeling Single-Event Upsets in 65-nm Silicon-on-Insulator Semiconductor Devices [J]. IEEE Transactions on Nuclear Science, 2006, 53(6): 3321~3328.
[70] Srinivasan G R, Murley P C, Tang H K, et al. Accurate, Predictive Modeling of Soft Error Rate Due to Cosmic Rays and Chip Alpha Radiation [C]. IEEE International Reliability Physics Symposium, 1994: 12~16.
[71] Baze M, Buchner S. Attenuation of Single Event Induced Pulses in CMOS Combinational Logic [J]. IEEE Transactions on Nuclear Science, 1997, 44(6): 2217~2223.
[72] Chandra V, Aitken R. Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS [C]. IEEE Defect and Fault Tolerance of VLSI Systems, 2008: 114~122.
[73] Rossi D, Cazeaux J M, Omana M. Accurate Linear Model for SET Critical Charge Estimation [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 17(8): 1161~1166.
[74] Sun Y, Song C, Zhao Y L, Zhang M X. FAST: A Framework of AccurateSER-Estimation at Transistor-Level for Logic Circuits [C]. International Conference on Solid-State and Integrated Circuit Technology, 2010.
[75] Hazucha P, Svensson C. Impact of CMOS Technological Scaling on the Atmospheric Neutron Soft Error Rate [J]. IEEE Transactions on Nuclear Science, 2000, 47(6): 2586~2594.
[76] Wang F, Xie Y, Rajaraman R, Vaidyanathan B. Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model [C]. Proceedings of IEEE International Conference on VLSI Design (VLSID), 2007: 165~170.
[77] Wang N J, Quek J, Rafacz T M, et al. Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline [C]. 2004 International Conference on Dependable Systems and Networks, 2004: 61~67.
[78]黄海林,唐志敏,许彤.龙芯1号处理器的故障注入方法与软错误敏感性分析[J].计算机研究与发展, 2006, 43(10): 1820~1827.
[79] Nguyen H T, Yagil Y, Seifert N, Reitsma M. Chip-Level Soft Error Estimation Method [J]. IEEE Transactions on Device and Materials Reliability, 2005, 5(3): 365~381.
[80] Mukherjee S S, Weaver C, Emer J, et al. A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor [C]. Proceedings of 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003: 29~40.
[81] Biswas A, Racunas P, Cheveresan R, et al. Computing Architectural Vulnerability Factors for Address-Based Structures [C]. Proceedings of 32nd International Symposium on Computer Architecture, 2005: 532~543.
[82] Fu X, Li T, Fortes J. Sim-SODA: A Unified Framework for Architectural Level Software Reliability Analysis [C]. Workshop on Modeling, Benchmarking and Simulation (Held in conjunction with International Symposium on Computer Architecture), 2006.
[83] Biswas A, Racunas P, Emer J, Mukherjee S S. Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal [J]. IEEE Computer Architecture Letters, 2007, 7(1): 21~24.
[84] Li X, Adve S V, Bose P, et al. SoftArch: An Architecture-Level Tool for Modeling and Analyzing Soft Errors [C]. Proceedings of International Conference on Dependable Systems and Networks, 2005: 496~505.
[85] Reick K, Sanda P N, Swaney S, et al. Fault-Tolerant Design of the IBM POWER6 Microprocessor [J]. IEEE Micro, 2008, 28(2): 30~38.
[86] Santarini M. Cosmic Radiation Comes to ASIC and SOC Design. EDN Europe, 2005, http://www.edn.com/contents/images/529381.pdf
[87] Cannon E H, Reinhardt D D, Gordon M S, et al. SRAM SER in 90, 130 and 180 nm Bulk and SOI Technologies [C]. International Reliability Physics Symposium, 2004: 300~304.
[88] Karnik T, Vangal S, Veeramachaneni V, et al. Selective Node Engineering for Chip-Level Soft Error Rate Improvement [C]. 2002 Symposium on VLSI Circuits Digest of Technical Papers, 2002: 204~205.
[89] Mohanram K, Touba N A. Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits [C]. Proceedings of International Test Conference (ITC’03), 2003: 893~901.
[90] Gill B S, Papachristou C, Wolff F G, Seifert N. Node Sensitivity Analysis for Soft Errors in CMOS Logic [C]. International Test Conference, 2005: 1~9.
[91] Rockett L R. An SEU-Hardened CMOS Data Latch Design [C]. IEEE Transactions on Nuclear Science, 1988, 35(6): 1682~1687.
[92] Whitaker S, Canaris J, Liu K. SEU Hardened Memory Cells for a CCSDS Reed Solomn Encoder [J]. IEEE Transactions on Nuclear Science, 1991, 38(6): 1471~1477.
[93] Liu M N, Whitaker S. Low Power SEU Immune CMOS Memory Circuits [J]. IEEE Transactions on Nuclear Science, 1992, 39(6): 1679~1684.
[94] Bessot D, Velazco R. Design of SEU-Hardened CMOS Memory Cells: The HIT Cell [C]. the 2nd European Conference Radiation and Its Effects on Components and Systems. 1993: 563~570.
[95] Velazco R, Bessot D. Two CMOS Memory Cells Suitable for the Design of SEU-Tolerant VLSI Circuits [C]. IEEE Transactions on Nuclear Science, 1994, 41(6): 2229~2234.
[96] Haddad N, Rockett L, Doyle S. Design Considerations for Next Generation Radiation Hardened SRAMs for Space Applications [C]. 2005 IEEE Aerospace Conference, 2005: 1~6.
[97] Calin T, Nicolaidis M, Velazco R. Upset Hardened Memory Design for Submicron CMOS Technology [J]. IEEE Transactions on Nuclear Science, 1996, 43(6): 2874~2878.
[98]刘必慰,陈书明,梁斌.一种低功耗的SEU加固存储单元[J].半导体学报,2007, 28(5): 755~758.
[99] Gong R, Chen W, Liu F, et al, A New Approach to Single Event Effect Tolerance based on Asynchronous Circuit Technique [J]. Journal of Electronic Testing: Theory and Applications (JETTA), 2008, 24(1): 57~65.
[100] Gong R, Chen W, Liu F, et al. Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique [C]. In Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT’06), 2006: 184~194.
[101] Mitra S, Zhang M, Waqas S, et al. Combinational Logic Soft Error Correction [C]. International Test Conference, 2006: 1~9.
[102] Sasaki Y, Namba K, Ito H, Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit [C]. the 21st International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’06), 2006: 327~335.
[103] Garg R, Jayakumar N, Khatri S P, et al. A Design Approach for Radiation-Hard Digital Electronics [C]. 43rd ACM/IEEE Design Automation Conference, 2006: 773~778.
[104] Michels A, Petroli L, Lisboa C A L, et al. SET Fault Tolerant Combinational Circuits Based on Majority Logic [C]. 21st International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’06), 2006: 345~352.
[105] Mohanram K, Touba N A. Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits [C], Proc of 18th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’03), 2003: 433~440.
[106] Miskov-Zivanov N, Marculescu D. MARS-C: Modeling and Reduction of Soft Errors in Combinational Circuits [C]. Proc of 43rd ACM/IEEE Design Automation Conference (DAC’06), 2006: 767~772.
[107] Rao R R, Blaauw D, Sylvester D. Soft Error Reduction in Combinational Logic Using Gate Resizing and Flipflop Selection [C]. Proc of International Conference on Computer-Aided Design (ICCAD’06), 2006: 502~509.
[108] Hill E L, Lipasti M H, Saluja K K. An Accurate Flip-flop Selection Technique for Reducing Logic SER [C]. Proc of 38th International Conference on Dependable Systems and Networks (DSN’08), 2008: 128~136.
[109] Sridharan V, Asadi H, Tahoori M B, Kaeli D. Reducing Data Cache Susceptibility to Soft Errors [J]. IEEE Transactions on Dependable and Secure Computing, 2006, 3(4): 353~364.
[110] Zhang W. Computing Cache Vulnerability to Transient Errors and Its Implication [C]. 20th IEEE Defect and Fault Tolerance in VLSI Systems, 2005: 427~435.
[111] Wang S, Hu J, Ziavras S G. On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors [C]. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2006: 14~20.
[112] Kadayif I, Kandemir M. Modeling and Improving Data Cache Reliability [J]. ACM SIGMETRICS Performance Evaluation Review, 2007, 35(1): 1~12.
[113] Zhang W, Gurumurthi S, Kandemir M, et al. ICR: In-Cache Replication for Enhancing Data Cache Reliability [C]. International Conference on ependable Systems and Networks, 2003: 291~300.
[114] Zhang W. Replica Victim Caching to Improve Reliability of In-CacheReplication [J]. Lecture Notes in Computer Science, Advances in Computer Systems Architecture, 2004: 2~15.
[115] Zhang W. Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability [J]. IEEE Transactions on Computers, 2005, 54(12): 1547~1555.
[116] Zhang W, Kandemir M, Sivasubramaniam A, et al. Performance, Energy, and Reliability Tradeoffs in Replicating Hot Cache Lines [C]. International Conference on Compilers, Architecture and Synthesis for Embedded Systems, 2003: 309~317.
[117] Hu J, Wang S, Ziavras S G. In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability [C]. International Dependable Systems and Networks, 2006: 281~290.
[118] Akcicek D, Koyuncu S, Sen H, et al. Exploiting Potentially Dead Blocks for Improving Data Cache Reliability Against Soft Errors [C]. International Symposium on Computer and Information Sciences, 2007: 1~6.
[119]江建慧,员春欣.芯片级系统的在线测试技术[J].计算机研究与发展,2004, 41(9): 1593~1603.
[120] Oh N, Shirvani P P, McCluskey E J. Error Detection by Duplicated Instructions in Super-Scalar Processors [J]. IEEE Transactions on Reliability, 2002, 51(1): 63~75.
[121] Oh N, Mitra S, McCluskey E J. ED4I: Error Detection by Diverse Data and Duplicated Instructions [J]. IEEE Transactions on Computer, 2002, 51(2): 180~199.
[122] Ray J, Hoe J C, Falsafi B. Dual Use of Superscalar Datapath for ransient-Fault Detection and Recovery [C]. Proceedings of 34th Symposium on Microarchitecture (Micro-34), 2001: 214~224.
[123] Todd M. Austin, DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design [C]. 32nd Annual International Symposium on Microarchitecture (MICRO), 1999: 196~207.
[124] Rotenberg E. AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors [C]. In Proceedings of the 29th Fault-Tolerant Computing Symposium, 1999: 84~91.
[125] Smolens J C, Jangwoo Kim, Hoe J C, Babak Falsafi. Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures [C]. International Symposium on Microarchitecture (MICRO), 2004: 257~268.
[126] Vijaykumar T N, Pomeranz I, Cheng K. Transient-Fault Recovery Using Simultaneous Multithreading [C]. Proceedings of 29th International Symposium on Computer Architecture, 2002: 87~98.
[127] Mukherjee S, Kontz M Reinhardt S. Detailed Design and Evaluation of Redundant Multithreading Alternatives [C]. In International Symposium on Computer Architecture (ISCA), 2002: 99~110.
[128] Parashar A, Gurumurthi A, Sivasubramaniam A. A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy [C]. In Proceedings of the International Symposium on Computer Architecture (ISCA), 2004: 376~386.
[129] Gomaa M A, Vijaykumar T N. Opportunistic Transient-Fault Detection [C]. In Proceedings of the International Symposium on Computer Architecture (ISCA), 2005: 172~183.
[130] Fu X, Poe J, Li T, Fortes J. Characterizing Microarchitecture Soft Error Vulnerability Phase Behavior [C]. In Proceedings of the International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), 2006: 147~155.
[131] Walcott K R, Humphreys G, Gurumurthi S. Vulnerabilities Dynamic Prediction of Architectural Vulnerability from Microarchitectural State [C]. 32nd Annual International Symposium on Computer Architecture (ISCA), 2007: 516~527.
[132] Lin S, Yang H, Luo R. A New Family of Sequential Elements with Built-in Soft Error Tolerance for Dual-VDD Systems [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008, 16(10): 1372.
[133] Mupid A, Mutyam M, Vijaykrishnan N, et al. Variation Analysis of CAM Cells [C]. 8th International Symposium on Quality Electronic Design (ISQED’07), 2007: 333~338.
[134] Chaudhary V, Clark L T. Low-Power High-Performance NAND Match Line Content Addressable Memories [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006, 14(8): 895.
[135] Luong Dinh Hung. Soft-Error Tolerant Cache Architectures [D]. Tokyo: The University of Tokyo, 2006.
[136] Rabaey J M等著,周润德等译.数字集成电路——电路、系统与设计(第二版)[M].北京:电子工业出版社,2004.
[137] Heijmen T. Soft-Error Vulnerability of Sub-100-nm Flip-flops [C]. Proc 14th IEEE International On-Line Testing Symposium, 2008: 247~252.
[138] Rao R R, Chopra K, Blaauw D, Sylvester D. An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits [C]. Proc Design Automation and Test in Europe (DATE), 2006: 164~169.
[139] Naseer R, Boulghassoul Y, Draper J, DasGupta S, Witulski A. Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM [C]. International Symposium on Computer Architecture (ISCAS’07), 2007: 1879~1882.
[140] Gill B S, Papachristou C, Wolff F G. A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA [C]. Design, Automation and Test in Europe Conference and Exposition (DATE’07), 2007: 1~6.
[141] Mavis D, Eaton P. Soft Error Rate Mitigation Techniques for Modern Microcircuits [C]. Proc. of IEEE International Reliability Physics Symposium (IRPS), 2002: 216~225.
[142] Knudsen J E, Clark L T. An Area and Power Efficient Radiation Hardened by Design Flip-Flop [J]. IEEE Transactions on Nuclear Science, 2006, 53(6): 3392~3399.
[143] Chen M, Orailoglu A. Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements [C]. Proc. of 16th IEEE Asian Test Symposium, 2007: 307~312.
[144] Zhang M et al. A Soft Error Rate Analysis (SERA) Methodology [C]. Proc of International Conference on Computer-Aided Design (ICCAD’04), 2004: 111~118.
[145] Asadi G, Tahoori M B. An Accurate SER Estimation Method Based on Propagation Probability [C]. Proc of Design, Automation and Test in Europe (DATE’05), 2005: 306~307.
[146] Zhang B, Wang W S, Orshansky M. FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs [C]. Proc of 7th International Symposium on Quality Electronic Design (ISQED’06), 2006: 755~760.
[147] Miskov-Zivanov N, Marculescu D. Modeling and Optimization for Soft-Error Reliability of Sequential Circuits [J]. IEEE Trans. on CAD of Integrated Circuits and Systems, 2008, 27(5): 803~816.
[148] Holcomb D, Li W, Seshia S A. Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits [C]. Proc of Design Automation and Test in Europe (DATE’09), 2009: 785~790.
[149]周学海,余洁,李曦等.基于指令行为的Cache可靠性评估研究[J].计算机研究与发展, 2007, 44(4): 553-559
[150] Cornelius C, Grassert F, Koppe S, et al. Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques [C]. 20th International Conference on VLSI Design (Held jointly with 6th International Conference on Embedded Systems), 2007: 330~338.
[151] Kumar J, Tahoori M B. A Low Power Soft Error Suppression Technique for Dynamic Logic [C]. 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2005: 454~462.
[152] Cha H, Patel J H. A Logic-Level Model forα-Particle Hits in CMOS Circuits [C]. IEEE International Conference Computer Design 1993: 538~542.
[153] Naseer R, Draper J, Boulghassoul Y, et al. Critical Charge and SET Pulse Widths for Combinational Logic in Commercial 90nm CMOS Technology [C]. Proceedings of the 17th Great Lakes Symposium on VLSI, 2007: 227~230.
[154] Wilkinson J, Hareland S. A Cautionary Tale of Soft Errors Induced by SRAM Packaging Materials [J]. IEEE Transactions on Device and Materials Reliability, 2005, 5(3): 428~433.
[155] Baumann R. The Impact of Technology Scaling on Soft Error Rate Performance and Limts to the Efficacy of Error Correction [C]. International Electron Devices Meeting, 2002: 329~332.
[156] Mitra S, Zhang M, Mak T M, et al. Logic Soft Errors: A Major Barrier to Robust Platform Design [C]. IEEE International Test Conference, 2005: 687~696.
[157] Lyons R E, Vanderkulk W. The Use of Triple Modular Redundancy to Improve Computer Reliability [J]. IBM Journal of Research and Development, 1962, 6(2): 200~209.
[158] Shah J S. Design of Soft Error Robust High Speed 64-bit Logarithmic Adder [D]. Master thesis, University of Waterloo, 2008.
[159] Kogge P, Stone H. A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Relations [J]. IEEE Trans. Computers, 1973, C-22(8): 786~793.
[160] Dimitrakopoulos G, Nikolos D. High-Speed Parallel-Prefix VLSI Ling Adders [J]. IEEE Transactions on Computers, 2005, 54(2): 225~231.
[161]李兆麟,盛世敏,吉利久,王阳元.基于单元故障模型的树型加法器的测试[C].计算机学报,2003, 26(11): 1494~1501.
[162]孙岩.高性能算术逻辑部件研究与全定制设计[D].硕士学位论文.长沙:国防科学技术大学.2005.
[163] Ndai P, Lu S L, Somesekhar D, et al. Fine-Grained Redundancy in Adders [C]. 8th International Symposium on Quality Electronic Design, 2007: 317~321.
[164] Sun Y, Zheng D Y, Zhang M X, et al. High Performance Low-Power Sparse-Tree Binary Adders [C]. 8th International Conference on Solid-State and Integrated Circuit Technology, 2006: 1649~1651.
[165] Mesquita E, Franck H, Agostini L, et al. Soft Error Tolerant Carry-Select Adders Implemented Into Altera FPGAs [C]. 3rd Southern Conference on Programmable Logic, 2007: 199~202.
[166] Zhou Q, Mohanram K. Gate Sizing to Radiation Harden Combinational Logic [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006: 155~166.
[167] Bushnell M L. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits [M]. Boston/Dordrecht/London : Kluwer Academic Publishers, 2000.