专用指令集处理器（ASIP）体系结构设计研究
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摘要
专用指令集处理器(ASIP，Application Specific Instruction Set Processor)是一种新型的具有处理器结构的芯片，它为某个或某一类型应用而专门设计。通过权衡速度、功耗、成本、灵活性等多个方面的设计约束，设计者可以定制ASIP达到最好的平衡点，从而适应嵌入式系统的需要。因而ASIP在嵌入式领域具有良好的应用前景。
ASIP设计需要面对多种类型的应用定制最优的体系结构，应用多样性和设计时效性是迫切需要解决的问题。然而，目前ASIP体系结构设计的研究大多在某个局部展开，难以提供一种具有易用性、快速性和可评估性的设计方法和环境。所以，本文在对具体的ASIP设计步骤和现有设计方法学进行分析的基础上，提出一种“描述-搜索-细化”的ASIP体系结构设计流程，研究了设计中体系结构描述、搜索与低功耗优化的问题，并依此实现完整的设计环境原型。主要研究归结为
① 基于ASIP体系结构描述语言xpADL的软件工具生成技术。使用体系结构描述语言xpADL驱动设计流程，设计和实现了描述语言可执行语义的转化和扩展机制，支持快速的功能性验证和性能估计。
② 基于基本指令集方法的指令集定制和结构属性设计空间搜索技术。定制指令集时利用性能、能耗、面积等多指标归一化模型评估指令集扩展的效果，并采用低功耗状态编码的思想进行指令字编码。同时，采用自动生成的软件工具对由流水线、功能部件、存储部件等构成的结构属性设计空间进行搜索，得到最优的ASIP体系结构。
③ 结合ASIP体系结构特征，以应用特征为指导，针对指令集(程序代码)、流水线和存储部件进行了低功耗优化研究。
④ 在上述研究的基础上，实现了一个支持“描述-搜索-细化”设计流程的ASIP体系结构设计环境原型A~2IDE，并基于此平台定义了采用ARM、PISA和Vcore等体系结构的实验型ASIP，验证了A~2IDE的有效性。
本论文做出的贡献主要体现在：
(1)在深入分析已有的电子系统设计方法学的基础上，实现了“描述-搜
ASIP (Application Specific Instruction Processor) is a kind of special processor designed for specific applications. Making tradeoffs between speed, cost, power consumption and flexibility, the designers customize ASIP to meet the demand of many design goals. So ASIP is becoming more and more popular in embedded applications.
When ASIP is used in embedded systems, the variance of applications and TTM (Time-to-Market) of the design poses challenges for ASIP designers. However, recent researches focus on some local factors of ASIP design. Most of them lack an easy-to-use, fast design method and evaluation environment. In this thesis, propose a "describe-explore-refine" design flow after analyzing existing design methodology. And then implement a prototype version of the design environment using our ASIP design method. The research mainly include
(1) Software automatic generation based on architecture description language (ADL, Architecture Description Language). Use xpADL to drive multiple design tasks. The transformation and extension of execution semantics of xpADL can speedup the functional verification and performance evaluation.
(2) Instruction customization and structure design space exploration base on basic instruction set method. Instruction set extension is evaluated by multi-objective unification evaluation model which uses performance, power, area, and code size as parameters. Encode instruction word based on low power state encoding. Meanwhile, adopt automatically generated tools to explore ASIP architecture design space, and obtain an optimal architecture.
(3) Combining with features of ASIP architecture, study on application specific low power optimization technology focusing on instruction set (program code), pipeline and storage.
(4) Build a "describe-explore-refine" design environment prototype system, A~2IDE. A~2IDE define multiple architecture instances (ARM, PISA, Vcore) as experimental ASIP. Verify the validity of the A~2IDE.
Main contributions of this paper include:
(1)After in-depth analysis of the design methodologies of electronic systems, propose a "describe-explore-refine" design flow. This design method uses
ASIP设计需要面对多种类型的应用定制最优的体系结构，应用多样性和设计时效性是迫切需要解决的问题。然而，目前ASIP体系结构设计的研究大多在某个局部展开，难以提供一种具有易用性、快速性和可评估性的设计方法和环境。所以，本文在对具体的ASIP设计步骤和现有设计方法学进行分析的基础上，提出一种“描述-搜索-细化”的ASIP体系结构设计流程，研究了设计中体系结构描述、搜索与低功耗优化的问题，并依此实现完整的设计环境原型。主要研究归结为
① 基于ASIP体系结构描述语言xpADL的软件工具生成技术。使用体系结构描述语言xpADL驱动设计流程，设计和实现了描述语言可执行语义的转化和扩展机制，支持快速的功能性验证和性能估计。
② 基于基本指令集方法的指令集定制和结构属性设计空间搜索技术。定制指令集时利用性能、能耗、面积等多指标归一化模型评估指令集扩展的效果，并采用低功耗状态编码的思想进行指令字编码。同时，采用自动生成的软件工具对由流水线、功能部件、存储部件等构成的结构属性设计空间进行搜索，得到最优的ASIP体系结构。
③ 结合ASIP体系结构特征，以应用特征为指导，针对指令集(程序代码)、流水线和存储部件进行了低功耗优化研究。
④ 在上述研究的基础上，实现了一个支持“描述-搜索-细化”设计流程的ASIP体系结构设计环境原型A~2IDE，并基于此平台定义了采用ARM、PISA和Vcore等体系结构的实验型ASIP，验证了A~2IDE的有效性。
本论文做出的贡献主要体现在：
(1)在深入分析已有的电子系统设计方法学的基础上，实现了“描述-搜
ASIP (Application Specific Instruction Processor) is a kind of special processor designed for specific applications. Making tradeoffs between speed, cost, power consumption and flexibility, the designers customize ASIP to meet the demand of many design goals. So ASIP is becoming more and more popular in embedded applications.
When ASIP is used in embedded systems, the variance of applications and TTM (Time-to-Market) of the design poses challenges for ASIP designers. However, recent researches focus on some local factors of ASIP design. Most of them lack an easy-to-use, fast design method and evaluation environment. In this thesis, propose a "describe-explore-refine" design flow after analyzing existing design methodology. And then implement a prototype version of the design environment using our ASIP design method. The research mainly include
(1) Software automatic generation based on architecture description language (ADL, Architecture Description Language). Use xpADL to drive multiple design tasks. The transformation and extension of execution semantics of xpADL can speedup the functional verification and performance evaluation.
(2) Instruction customization and structure design space exploration base on basic instruction set method. Instruction set extension is evaluated by multi-objective unification evaluation model which uses performance, power, area, and code size as parameters. Encode instruction word based on low power state encoding. Meanwhile, adopt automatically generated tools to explore ASIP architecture design space, and obtain an optimal architecture.
(3) Combining with features of ASIP architecture, study on application specific low power optimization technology focusing on instruction set (program code), pipeline and storage.
(4) Build a "describe-explore-refine" design environment prototype system, A~2IDE. A~2IDE define multiple architecture instances (ARM, PISA, Vcore) as experimental ASIP. Verify the validity of the A~2IDE.
Main contributions of this paper include:
(1)After in-depth analysis of the design methodologies of electronic systems, propose a "describe-explore-refine" design flow. This design method uses
引文
[1].Jain M.K., Balakrishnan M., Kumar A.: ASIP design methodologies: survey and issues, VLSI Design, 2001. :76-81
[2].Keutzer, K.; Malik, S.; Newton, A.R., From ASIC to ASIP: the next design discontinuity, Computer Design: VLSI in Computers and Processors, 2002. Pages:84-90.
[3]. Najm F N. Transition density: a new measure of activity in digital circuits. IEEE Trans Comp-Aided Des Integ Circ Syst, 1992; 12 (2): 310-323.
[4]. Gupta, T.V.K.; Sharma, P.; Balakrishnan, M.; Malik, S. : "Processor evaluation in an embedded systems design environment. ",Proceedings of Thirteenth International Conference on VLSI Design 2000, 3-7 Jan. 2000, Pages: 98-103.
[5]. Ghazal, N.; Newton, R.; Jan Rabaey. : "Retargetable estimation scheme for DSP architectnre selection.", Proceedings of the Asia and South Pacific Design Automation Conference 2000(ASP-DAC 2000), 25-28 Jan. 2000, Pages: 485- 489.
[6]. Liu D, Svensson C.Power consumption estimation in CMOS VLSI chips.IEEE Journal of Solid-State Circuits, 1994, 29(6):663～670
[7]. Gong J.; Gajski, D.D.; Nicolau, A. : "Performance evaluation for application- specific architectures.", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Dec. 1995 Vol. 3 Issue: 4, Pages: 483-490.
[8]. Binh, N.N.; Imai, M.; Shiomi, A.; Hikichi, N. : "A hardware/software partitioning algorithm for pipelined instruction set processor.", Proceedings of the Design Automation Conference, 1995, with EURO-VHDL, EURO- DAC '95, 18-22 Sept. 1995, Pages: 176-181.
[9]. Binh, N.N.; Imai, M.; Shiomi, A. : "A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs.", Proceedings of the Design Automation Conference, 1996, with EURO-VHDL'96 , EURO-DAC'96, 16-20 Sept. 1996, Pages: 126-131.
[10].Kienhuis, B.; Deprettere, E.; Vissers, K.; van der Wolf, P. : "The construction of a retargetable simulator for an architecture template." , Proceedings of the Sixth International Workshop on Hardware/Software Codesign 1998(CODES/CASHE'98), 15-18 March 1998, Pages: 125-129.
[11].Kin, J.; Chunho Lee; Mangione-Smith,W.H.; Potkonjak, M. : "Power efficient mediaprocessors: design space exploration.", Proceedings of the 36th Design Automation Conference 1999, 21-25 June 1999, Pages: 321-326.
[12].Gupta, T.V.K.; Sharma, P.; Balakrishnan, M; Malik, S. : "Processor evaluation in an embedded systems design environment.", Proceedings of Thirteenth International Conference on VLSI Design 2000, 3-7 Jan. 2000, Pages: 98-103.
[13].Kienhuis, B.; Deprettere, E.; Vissers, K.; van der Wolf, P. : "The construction of a retargetable simulator for an architecture template.", Proceedings of the Sixth International Workshop on Hardware/Software Codesign 1998 (CODES/CASHE'98), 15-18 March 1998, Pages: 125-129.
[14].Gloria A. D.; Faraboschi, P. : "An evaluation system for application specific architectures.", Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture. (Micro 23), 27-29 Nov. 1990, Pages: 80-89.
[15].Gschwind, M. : "Instruction set selection for ASIP design.", Proceedings of the Seventh International Workshop on Hardware/Software Codesign 1999 (CODES'99), 3-5 May 1999, Pages: 7-11.
[16].Hoon Choi; In-Cheol Park; Seung Ho Hwang; Chong-Min Kyung : "Synthesis of application specific instructions for embedded DSP software.", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1998.ICCAD 98. Digest of Technical Papers 1998, 8-12 Nov. 1998, Pages: 665 -671.
[17]. Huang , I.J.; Despain , A.M. : "Generating Instruction Sets And Microarchitectures From Applications." , Proceedings of the IEEE/ACM International Conference on Computer-Aided Design 1994, 6-10 Nov. 1994, Pages: 391-396.
[18].Huang I.J.; Despain, A.M. : "Synthesis of application specific instruction sets.", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, June 1995 Vol. 14 Issue: 6 Pages: 663-675.
[19].Imai, M.; Alomary, A.; Sato, J.; Hikichi, N. : "An integer programming approach to instruction implementation method selection problem." , Proceedings of the European Design Automation Conference, 1992., EURO- VHDL'92, EURO-DAC'92, 7-10 Sept. 1992, Pages: 106-111.
[20].Liem, C; May, T.; Paulin, P. : "Instruction-set matching and selection for DSP and ASIP code generation.", Proceedings of the European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, 28 Feb.-3 March 1994, Pages: 31-37.
[21].Leupers, R.; Marwedel, P. : "Instruction selection for embedded DSPs with complex instructions.", Proceedings of the European Design Automation Conference, 1996, with EURO-VHDL '96, EURO-DAC '96, 16-20 Sept. 1996, Pages: 200-205.
[22].Shu, J.; Wilson, T.C.; Banerji, D.K. : "Instruction-set matching and GA- based selection for embedded-processor code generation.", Proceedings of the Ninth International Conference on VLSI Design 1996, 3-6 Jan. 1996, Pages: 73-76.
[23].Hsieh C T, Ding C S, Wu Q, et al.Sta tistical sampling and regression estimat i on in power macro-modeling [A] .Proc IEEE Int Conf Comp Aided Des [C], 1996, 583—58 8.
[24]《现代处理器设计技术》, John paul shen, Mikko H.lipasti 著。电子工业出版社 出版, 2004
[25].Kreuzer,W.; Gotschlich, M.; Wess, B. : "A retargetable optimizing code generator for digital signal processors.", Proceedings of the IEEE International Symposium on Circuits and Systems 1996. ISCAS '96. , Connecting theWorld., 1996, Vol.2, Pages:257-260.
[26].Praet, J.V.; Lanneer, D.; Goossens, G; Geurts, W.; De Man, H. : "A graph based processor model for retargetable code generation.", Proceedings of the European Design and Test Conference 1996 (ED&TC 96), 11-14 March 1996, Pages: 102-107.
[27]. Yamaguchi, M.; Ishiura, N.; Kambe, T. : "Binding and scheduling algorithms for highly retargetable compilation.", Proceedings of the Asia and South Pacific Design Automation Conference 1998 (ASP-DAC '98), 10-13 Feb. 1998, Pages:93-98.
[28].Hanono, S.; Devadas, S. : "Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator.",Proceedings of the Design Automation Conference 1998, 15-19 June 1998, Pages: 510-515.
[29].Serge Leef, "A Methodology for Virtual Hardware/Software Integration", Mentor, 1998
[30].Hatcher , P.J.; Tuller , J.W. : "Efficient retargetable compiler code generation." , Proceedings of the International Conference on Computer Languages 1988, 9-13 Oct. 1988, Pages: 25-30.
[31].Kuroda, I.; Nishitani, T. : "A knowledge-based retargetable compiler for application specific signal processors.", Proceedings of the IEEE International Symposium on Circuits and Systems 1989, 8-11 May 1989, Vol. 1, Pages: 631-634.
[32].Leupers, R.; Marwedel, P. : "Retargetable generation of code selectors from HDL processor models.", Proceedings of the European Design and Test Conference, 1997. ED&TC 97, 9-13 June 1997, Pages: 534-539.
[33].Steven Bashford, Ulrich Bieker, Berthold Harking et. al.. The MIMOLA Language Version 4.1. http://lsl2-www.cs.uni-dortmund.de/research/mimola- 4.1.ps.gz
[34].Fauth, A.; Van Praet, J.; Freericks, M.; Describing instruction set processors using nML, European Design and Test Conference, 1995. ED&TC 1995, Proceedings, 6-9 March 1995 Page(s):503 - 507.
[35].Mark R. Hartoog, James A. Rowson, Prakash D. Reddy et al., Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign. Design Automation Conference Proceedings of the 34th, 1997, 9 (13): 303 - 306.
[36].G. Hadjiyiannis, S. Hanono, and S. Devadas. ISDL: An Instruction Set Description Language for Retargetability. In Proceedingsof the 34 th DesignAutomation Conference,pages 299-302 , June 1997. http://citeseer.ist.psu.edu/hadjiyiannis97isdl.html
[37].G. Hadjiyiannis, P. Russo, and S. Devadas. A methodology for accurate performance evaluation in architecture exploration. In Proceedings of the 36th Design Automation Conference, June 1999.
[38]. George Hadjiyiannis, Srinivas Devadas. Techniques for Accurate Performance Evaluation in Architecture Exploration. IEEE Transactions on VLSI Systems, 2003, 11(4): 601-615.
[39].J. C. Gyllenhaal, "A machine description language for compilation", Master thesis, Dept. of ECE, UIUC, 1994
[40]. J. C. Gyllenhaal et.al., "Optimization of nachine descriptions for efficient use", Int'l Journal of Parallel Programming, 1998
[41].Stefan Pees, Andreas Ho mann, Vojin Zivojnovic, and Heinrich Meyr. LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures. Proceedings of the DAC , 1999. To be published. http://citeseer.ist.psu.edu/pees991isa.html
[42]. V. Zivojnovic, S. Pees, and H. Meyr. Lisa - machine description language and generic machine model for hw/sw co-design. In W. Burleson, K. Konstantinides, and T. Meng, editors, VLSI Signal Processing IX, 1996. http://citeseer.ist.psu.edu/pees961isa.html
[43].Andreas Hoffmann, Tim Kogel, Achim Nohl et al., A Novel Methodology for the Design of Application-Specific Instruction-Set Processors (ASIPs) Using a Machine Description Language. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001, 20(11): 1338 - 1354.
[44].Ashok Halambi, Peter Grun, Vijay Ganesh, et al., EXPRESSION: A Language for Architecture Exploration through Compile/Simulator Retargetability. Proceedings of DATE, 1999, 9(12): 485 - 490.
[45].P.Grun, A.Halambi,A.Khare,et al; EXPRESSION:An ADL for system level design exploration. Tech Report TR 98-29 , University of California , Irvine, 1998
[46].Russell Priebe, Cary Ussery. A configurable platform for advanced system-on-a-chip applications. In: ICSPA T2000.Dallas, TX, USA, 2000
[47].Marc Tremblay, Jeffrey Chan, et al. The MAJC architecture: A synthesis of parallelism and scalability.IEEE M icro, 2000, 20 (6): 12— 25
[48].Li Li, Minglun Gao, Zuoren Cheng, Duoli Zhang, et al A new platform-based orthogonal SoC design methodology[A], ASIC[C], 2003:428-432.
[49].Ahdina M, Monteiro J, Devadas S.Precomputation-based sequential logic optimization for low power.IEEE Trans on VLSI Systems, 1994, 2(4):426～ 436
[50].Benini L, De Micheli G.Transformation and synthesis of FSMs for low power gated clock implementation.IEEE Trans on CAD, 1996, 15(6):630～643
[51].Tiwari V, Malik S, Ashar P.Guarded evaluation:pushing power management to logic synthesis/design.ACM/IEEE ISLPD, 1995, 221 —226
[52].Tensilica. Xtensa http://www.tensilica.com, 2001.
[53].R. Gonzales. Xtensa: A Configurable and Extensible Processor. IEEE Micro, 20(2):60-70, Mar. 2000.
[54].ARC Cores Ltd. ARC Programmers Reference Manual, Dec. 1999.
[55].ARC Cores Ltd. ARCtangent Processor, http://www.arccores.com, 2001.
[56].Cary Ussery. Configurable Processing Platforms: Redefining SoC. http://www.improvsys.com, 2001.
[57]. S.H. Leibson. Jazz Joins VLIW Juggernaut - CMP and Java as an HDL Take System-on-Chip. Design to Parallel Universe. Microprocessor Report, 2000.
[58].P. Kievits, E. Lambers, C. Moerman, and R. Woudsma. R.E.A.L. DSP Technology for Telecom Baseband Processing. Proc. of the Int. Conf. on Signal Processing Applications and Technology (ICSPAT), Toronto, CA, 1998.
[59].Kucukcakar, K. , et al, "Matisse: An Architectural Design Tool for Commodity ICs," IEEE Design & Test of Computers, April-June 1998
[60].D. Knapp and M. Winslett, "A Prescriptive Formal Model for Data-Path Hardware," IEEE Trans. Computer-Aided Design, Vol. 11, No. 2, Feb. 1992, pp.158-184.
[61].D. Gajski et al., A Design Methodology and Environment for Interactive Bahavioral Synthesis, Tech. Report 96-29, Dept. of Information and Computer Science, Univ. of California, Irvine, 1996.
[62].A.A. Jerraya, I. Park, and K. O'Brien, "Amical: An Interactive High Level Synthesis Environment," Proc. European Design Automation Conf., IEEE Computer Society Press, Los Alamitos, Calif., 1993, pp. 58-63.
[63].B. Shackleford, M. Yasuda, E. Okushi, H. Koizumi, H. Tomiyama, and H. Yasuura. Satsuki: An Integrated Processor Synthesis and Compiler Generation System. In IEICE Transactions on Information and Systems, pages 1373 - 1381, 1996.
[64].I.J. Huang and A.M. Despain. Synthesis of Instruction Sets for Pipelined Microprocessors. In Proc. of the Design Automation Conference (DAC), Jun. 1994.
[65].I.J. Huang, B. Holmer, and A.M. Despain. ASIA: Automatic Synthesis of Instruction-Set Architectures. In Proc. of the SASIMI Workshop, Oct. 1993.
[66]. P. Paulin, C. Liem, T.C. May, and S. Sutarwala. Flex Ware: A Flexible Firmware Development Environment for Embedded Systems. In Code Generation for Embedded Processors, Editors: P. Marwedel and G. Goossens. Kluwer Academic Publishers, 1995.
[67].P. Paulin, C. Liem, C. May, and S. Sutarwala. CodeSyn: A Retargetable Code Synthesis System. In Proc. of the Int. Symposium on System Synthesis (ISSS), May 1994.
[68].Pieter J. Schoenmakers and J. Frans M. Theeuwen. Clock Gating on RT-Level VHDL. Proc. of the Int. Workshop on Logic Synthesis, Tahoe City, CA, pages 387-391, June 7 - 10, 1998.
[69].Santosh Abraham, Bob Rau, Robert Schreiber, Greg Snider, and Michael Schlansker. Efficient Design Space Exploration in PICO. Proc. of the Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), pages 71-79, Nov. 2000.
[70].Yanagisawa, H.; Uehara, M.; Mori, H.; Development methodology of ASIP based on Java byte code using HW/SW co-design system for processor design. Distributed Computing Systems Workshops , 2004. Proceedings. 24th International Conference on 2004 Page(s):831 - 837
[71].M. Itoh, S. Higaki, J. Sato, A. Shiomi, Y. Takeuchi A. Kitajima, and M. Imai. PEAS-III: An ASIP Design Environment. In Proc. of the Int. Conf. on Computer Design (ICCD), Sep. 2000.
[72].A. Kitajima, M. Itoh, J. Sato, A. Shiomi, Y. Takeuchi, and M. Imai. Effectiveness of the ASIP Design System PEAS-III in Design of Pipelined Processors. In Proc. of the Asia South Pacific Design Automation Conference (ASPDAC), Jan. 2001.
[73]J.-H. Yang, B.-W. Kim, S.-J. Nam, Y.-S. Kwon, D.-H. Lee, J.-Y. Lee, C- S. Hwang, Y.-H. Lee, S.-H. Hwang, I.-C. Park, and C.-M. Kyung. MetaCore: An Application-Specific Programmable DSP Development System. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(2): 173-183, Apr. 2000.
[74]．李曦：片上系统(SOC)的体系结构设计方法与功耗模型研究，中国科学技术大学博士学位论文，2003
[75]. D. E. Thomas nad R moorby. The Verilog Hardware Description Language. Kluwer Academic Publishers, 1991
[76]. D. D. Gajski, F. Vahid, S Narayan. A system-desing methodology: Executablespecification refinement. EDAC 1994
[77]. W3C,http://www.w3c.org/xml/
[78]. tolemy,http://ptolemy.eecs.berkeley.edu/
[79]. W3C,http://www.w3c.org/schema/
[80]. Doug Burger, Todd M. Austin: The SimpleScalar Tool Set, Version 2.0[R], University of Wisconsin-Madison Computer Sciences Department Technical Report #1342, June, 1997.
[81]. E. S. Davidson, L. E. Shar, A. T. Thomas, and J. H. Patel, "Effective Control for Pipelined Computers", in the Spring COMPCON'75 Digest of Papers, 181-184, February 1975
[82]. H. Zhong, and S. Mahlke. Processor acceleration through automated instruction set customisation. In Diego, Calif. Dec. 2003.
[83]．李曦，王志刚，周学海，王煦法，面向低功耗优化设计的系统级功耗模型研究，电子学报，Vol 32，No 2，2004
[84]. Yun Zhu, Xi Li, Laurence T. Yang, Jun Yang. A Fast Instruction Set Evaluation Method for ASIP Designs.EUC-06, acccpted
[85]. M. Martonosi, D. Brooks and P. Bose, Modeling and Analyzing CPU Power and Performance: Metrics, Methods and Abstractions; Tutorial presentation at ACM Sigmetrics-2001, June 17, 2001.
[86]. Weiyu Tang; Gupta, R.; Nicolau, A., Power savings in embedded processors through decode filter cache, Design, Automation and Test in Europe Conference and Exhibition, 2002. Pages: 443-448.
[87]. Bajwa, R. S.; Hiraki, M.; et al, Instruction buffering to reduce power in processors for signal processing, Very Large Scale Integration (VLSI) Systems, Dec. 1997. Pages: 417-424.
[88]. Lea Hwang Lee; Moyer, B.; Mends, J., Low-cost embedded program loop caching-revisited, Tech. rep., EECS, University of Michigan, December 1999.
[89]. Lea Hwang Lee; Moyer, B.; Arends, J., Instruction fetch energy reduction using loop caches for embedded applications with small tight loops, Low Power Electronics and Design, 1999. Proceedings. Pages:267 - 269.
[90].Vander An, T.; Jayapala, M.; Barat, F; Deconinck, G., Instruction buffering exploration for low energy VLIWs with instruction clusters, Design Automation Conference, 2004. Pages:825 - 830.
[91].Panis, C.; Grunbacher, H.; Nurmi, J., A scalable instruction buffer and align unit for xDSPcore, Solid-State Circuits, IEEE Journal of, Volume: 39 , Issue: 7 , July 2004. Pages: 1094-1100.
[92].Hiraki, M.; Bajwa, R.S.; Kojima, H.; Gorny, D.J.; Nitta, K.; Shri, A., Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer, Low Power Electronics and Design, 1996. Pages:353-358.
[93].Guthaus M.R., Ringenberg J.S., et al. MiBench: A free, commercially representative embedded benchmark suite [C]. IEEE International Workshop on Workload Characterization. Austin, 2001: 3 -14.
[94].Se-Hyun Yang, Powell M.D., et al. Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay [C]. Proceedings. Eighth International Symposium on High-Performance Computer Architecture. 2002: 151-161.
[95].Serge Leef, "A Methodology for Virtual Hardware/Software Integration", Mentor, 1998
[96].R K Gupta, Y Zorian. Introducing core base system design. IEEE Design & Test of Computers, 1997,14 (4) : 15-25
[97].R Ernst, .Codesign of embedded systems: status and trends. IEEE Design & Test of Computers, 1998,15(2):45-54
[98]. A Ferrari ,et al . System design :Traditional concepts and new paradigms. ICCD' 1999. Austin ,Texas ,1999. 2 -12.
[99]. L P Carloni , et al . The art and science of integrated systems design. In Proceedings of the 28th European Solid2State Circuits Conference. Firenze ,Italy ,2002. 25 - 36.
[100]. Bob Altizer. Platform2based design :the next reuse frontier. Embedded Systems Conference. San Francisco ,2002.
[101]. Huiyang Zhou, Toburen M.C., Rotenberg E., et al. Adaptive mode control: a static-power-efficient cache design [C]. Proceedings. 2001 International Conference on Parallel Architectures and Compilation Techniques. Barcelona, 2001:61-70.
[102]. Ranganathan P., Adve S., Jouppi, N.P. Reconfigurable caches and their application to media processing [C]. Proceedings of the 27th International Symposium on Computer Architecture. Vancouver, Canada, 2000: 214-224.
[103]. Wilton S., Jouppi N. P.: CACTI: An Enhanced Cache Access and Cycle Time Model [J]. IEEE Journal of Solid State Circuits, 1996, vol. 31, no. 5: 677-688
[104]. Shivakumar R, Jouppi N. P.: CACTI 3.0: An integrated cache timing, power and area model. Western Research Laboratory. Technical Report, 2001
[105]. David Tarjan: CACTI 4.0 Beta. http://analog.cs.virginia.edu:81/cacti/
[106]. Susan L. Graham, Peter B. Kessler, Marshall K. McKusick: gprof: a Call Graph Execution Profiler, SIGPLAN '82 Symposium on Compiler Construction, 1982, Pages: 120-126
[107]. Robert Cmelik, David Keppel: Shade: A Fast Instruction Set Simulator for Execution Profiling, Performance Evaluation Review, 1994, Pages: 128-137.
[108]. ExoLab Group: The Castor Project, http://castor.exolab.org/
[109]．陆岚：嵌入式系统可重定向功耗优化编译器研究，中国科学技术大学博士学位论文，2004
[110]．苏鹤年，李曦，王志刚，杨君：基于语言的ASIP系统级综合方法研究，微型机与应用，已录用
[111]．余洁，李曦等．可重定向的周期精确模拟器生成环境的研究．小型微型计算机系统，已录用
[112]. SPEC web99 Design Document. http://www.specbench.org/osg/web99/docs/whitepaper.html
[113]. Transaction Processing Performance Council, TPC Benchmark. http://www.tpc.org/information/benchmarks.asp
[114]. A. Malik, B. Moyer and D. Cermak, "A Low Power Unified Cache Architecture Providing Power and Performance Flexibility," Int. Symp. on Low Power Electronics and Design, June 2000.
[115]. C. Lee, M. Potkonjak and W. Mangione-Smith,"MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems," Int. Symp. On Microarchitecture, 1997.
[116]. D. C. Suresh, W. A. Najjar, F. Vahid, et al, Profiling tools for hardware/software partitioning of embedded applications. Compilers and Tools for Embedded Systems (LCTES), 2003, pp. 189-198
[117]. Weiyu Tang; Rajesh Gupta; Alexandru Nicolau."Power Savings in Embedded Processors through Decode Filter Cache" Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE.02) 1530-1591/02 2002 IEEE
[118]. Devadas S, Newton A R.Decomposition and factorization of sequential finite state machines.IEEE Trans on CAD, 1989, 8(11):1206—1217
[119]. Lin B, Newton A R, Implicit manipulation of equivalence classes using binary decision diagrams.IEEE ICCD , 1991, 81 — 85
[120]. Tsui C Y, Pedram M, Despain A M.Low power state assignment targeting two-and multilevel logic implementations.IEEE/ACM ICCAD, San Jose, CA, 1994, 82—87
[121]. Iman S, Pedram M. POSE: Power optimization and synthesis enviorment. In: IEEE eds. Proc 33rd ACM/IEEE Design Automation Conf. San Jose: IEEE Press. 1996.21—26
[122]. Gebotys C H.Low energy memory and register allocation using network flow.In:34th ACM/IEEE DAC, Anaheim, CA 1997, 435—440
[2].Keutzer, K.; Malik, S.; Newton, A.R., From ASIC to ASIP: the next design discontinuity, Computer Design: VLSI in Computers and Processors, 2002. Pages:84-90.
[3]. Najm F N. Transition density: a new measure of activity in digital circuits. IEEE Trans Comp-Aided Des Integ Circ Syst, 1992; 12 (2): 310-323.
[4]. Gupta, T.V.K.; Sharma, P.; Balakrishnan, M.; Malik, S. : "Processor evaluation in an embedded systems design environment. ",Proceedings of Thirteenth International Conference on VLSI Design 2000, 3-7 Jan. 2000, Pages: 98-103.
[5]. Ghazal, N.; Newton, R.; Jan Rabaey. : "Retargetable estimation scheme for DSP architectnre selection.", Proceedings of the Asia and South Pacific Design Automation Conference 2000(ASP-DAC 2000), 25-28 Jan. 2000, Pages: 485- 489.
[6]. Liu D, Svensson C.Power consumption estimation in CMOS VLSI chips.IEEE Journal of Solid-State Circuits, 1994, 29(6):663～670
[7]. Gong J.; Gajski, D.D.; Nicolau, A. : "Performance evaluation for application- specific architectures.", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Dec. 1995 Vol. 3 Issue: 4, Pages: 483-490.
[8]. Binh, N.N.; Imai, M.; Shiomi, A.; Hikichi, N. : "A hardware/software partitioning algorithm for pipelined instruction set processor.", Proceedings of the Design Automation Conference, 1995, with EURO-VHDL, EURO- DAC '95, 18-22 Sept. 1995, Pages: 176-181.
[9]. Binh, N.N.; Imai, M.; Shiomi, A. : "A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs.", Proceedings of the Design Automation Conference, 1996, with EURO-VHDL'96 , EURO-DAC'96, 16-20 Sept. 1996, Pages: 126-131.
[10].Kienhuis, B.; Deprettere, E.; Vissers, K.; van der Wolf, P. : "The construction of a retargetable simulator for an architecture template." , Proceedings of the Sixth International Workshop on Hardware/Software Codesign 1998(CODES/CASHE'98), 15-18 March 1998, Pages: 125-129.
[11].Kin, J.; Chunho Lee; Mangione-Smith,W.H.; Potkonjak, M. : "Power efficient mediaprocessors: design space exploration.", Proceedings of the 36th Design Automation Conference 1999, 21-25 June 1999, Pages: 321-326.
[12].Gupta, T.V.K.; Sharma, P.; Balakrishnan, M; Malik, S. : "Processor evaluation in an embedded systems design environment.", Proceedings of Thirteenth International Conference on VLSI Design 2000, 3-7 Jan. 2000, Pages: 98-103.
[13].Kienhuis, B.; Deprettere, E.; Vissers, K.; van der Wolf, P. : "The construction of a retargetable simulator for an architecture template.", Proceedings of the Sixth International Workshop on Hardware/Software Codesign 1998 (CODES/CASHE'98), 15-18 March 1998, Pages: 125-129.
[14].Gloria A. D.; Faraboschi, P. : "An evaluation system for application specific architectures.", Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture. (Micro 23), 27-29 Nov. 1990, Pages: 80-89.
[15].Gschwind, M. : "Instruction set selection for ASIP design.", Proceedings of the Seventh International Workshop on Hardware/Software Codesign 1999 (CODES'99), 3-5 May 1999, Pages: 7-11.
[16].Hoon Choi; In-Cheol Park; Seung Ho Hwang; Chong-Min Kyung : "Synthesis of application specific instructions for embedded DSP software.", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1998.ICCAD 98. Digest of Technical Papers 1998, 8-12 Nov. 1998, Pages: 665 -671.
[17]. Huang , I.J.; Despain , A.M. : "Generating Instruction Sets And Microarchitectures From Applications." , Proceedings of the IEEE/ACM International Conference on Computer-Aided Design 1994, 6-10 Nov. 1994, Pages: 391-396.
[18].Huang I.J.; Despain, A.M. : "Synthesis of application specific instruction sets.", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, June 1995 Vol. 14 Issue: 6 Pages: 663-675.
[19].Imai, M.; Alomary, A.; Sato, J.; Hikichi, N. : "An integer programming approach to instruction implementation method selection problem." , Proceedings of the European Design Automation Conference, 1992., EURO- VHDL'92, EURO-DAC'92, 7-10 Sept. 1992, Pages: 106-111.
[20].Liem, C; May, T.; Paulin, P. : "Instruction-set matching and selection for DSP and ASIP code generation.", Proceedings of the European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, 28 Feb.-3 March 1994, Pages: 31-37.
[21].Leupers, R.; Marwedel, P. : "Instruction selection for embedded DSPs with complex instructions.", Proceedings of the European Design Automation Conference, 1996, with EURO-VHDL '96, EURO-DAC '96, 16-20 Sept. 1996, Pages: 200-205.
[22].Shu, J.; Wilson, T.C.; Banerji, D.K. : "Instruction-set matching and GA- based selection for embedded-processor code generation.", Proceedings of the Ninth International Conference on VLSI Design 1996, 3-6 Jan. 1996, Pages: 73-76.
[23].Hsieh C T, Ding C S, Wu Q, et al.Sta tistical sampling and regression estimat i on in power macro-modeling [A] .Proc IEEE Int Conf Comp Aided Des [C], 1996, 583—58 8.
[24]《现代处理器设计技术》, John paul shen, Mikko H.lipasti 著。电子工业出版社 出版, 2004
[25].Kreuzer,W.; Gotschlich, M.; Wess, B. : "A retargetable optimizing code generator for digital signal processors.", Proceedings of the IEEE International Symposium on Circuits and Systems 1996. ISCAS '96. , Connecting theWorld., 1996, Vol.2, Pages:257-260.
[26].Praet, J.V.; Lanneer, D.; Goossens, G; Geurts, W.; De Man, H. : "A graph based processor model for retargetable code generation.", Proceedings of the European Design and Test Conference 1996 (ED&TC 96), 11-14 March 1996, Pages: 102-107.
[27]. Yamaguchi, M.; Ishiura, N.; Kambe, T. : "Binding and scheduling algorithms for highly retargetable compilation.", Proceedings of the Asia and South Pacific Design Automation Conference 1998 (ASP-DAC '98), 10-13 Feb. 1998, Pages:93-98.
[28].Hanono, S.; Devadas, S. : "Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator.",Proceedings of the Design Automation Conference 1998, 15-19 June 1998, Pages: 510-515.
[29].Serge Leef, "A Methodology for Virtual Hardware/Software Integration", Mentor, 1998
[30].Hatcher , P.J.; Tuller , J.W. : "Efficient retargetable compiler code generation." , Proceedings of the International Conference on Computer Languages 1988, 9-13 Oct. 1988, Pages: 25-30.
[31].Kuroda, I.; Nishitani, T. : "A knowledge-based retargetable compiler for application specific signal processors.", Proceedings of the IEEE International Symposium on Circuits and Systems 1989, 8-11 May 1989, Vol. 1, Pages: 631-634.
[32].Leupers, R.; Marwedel, P. : "Retargetable generation of code selectors from HDL processor models.", Proceedings of the European Design and Test Conference, 1997. ED&TC 97, 9-13 June 1997, Pages: 534-539.
[33].Steven Bashford, Ulrich Bieker, Berthold Harking et. al.. The MIMOLA Language Version 4.1. http://lsl2-www.cs.uni-dortmund.de/research/mimola- 4.1.ps.gz
[34].Fauth, A.; Van Praet, J.; Freericks, M.; Describing instruction set processors using nML, European Design and Test Conference, 1995. ED&TC 1995, Proceedings, 6-9 March 1995 Page(s):503 - 507.
[35].Mark R. Hartoog, James A. Rowson, Prakash D. Reddy et al., Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign. Design Automation Conference Proceedings of the 34th, 1997, 9 (13): 303 - 306.
[36].G. Hadjiyiannis, S. Hanono, and S. Devadas. ISDL: An Instruction Set Description Language for Retargetability. In Proceedingsof the 34 th DesignAutomation Conference,pages 299-302 , June 1997. http://citeseer.ist.psu.edu/hadjiyiannis97isdl.html
[37].G. Hadjiyiannis, P. Russo, and S. Devadas. A methodology for accurate performance evaluation in architecture exploration. In Proceedings of the 36th Design Automation Conference, June 1999.
[38]. George Hadjiyiannis, Srinivas Devadas. Techniques for Accurate Performance Evaluation in Architecture Exploration. IEEE Transactions on VLSI Systems, 2003, 11(4): 601-615.
[39].J. C. Gyllenhaal, "A machine description language for compilation", Master thesis, Dept. of ECE, UIUC, 1994
[40]. J. C. Gyllenhaal et.al., "Optimization of nachine descriptions for efficient use", Int'l Journal of Parallel Programming, 1998
[41].Stefan Pees, Andreas Ho mann, Vojin Zivojnovic, and Heinrich Meyr. LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures. Proceedings of the DAC , 1999. To be published. http://citeseer.ist.psu.edu/pees991isa.html
[42]. V. Zivojnovic, S. Pees, and H. Meyr. Lisa - machine description language and generic machine model for hw/sw co-design. In W. Burleson, K. Konstantinides, and T. Meng, editors, VLSI Signal Processing IX, 1996. http://citeseer.ist.psu.edu/pees961isa.html
[43].Andreas Hoffmann, Tim Kogel, Achim Nohl et al., A Novel Methodology for the Design of Application-Specific Instruction-Set Processors (ASIPs) Using a Machine Description Language. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001, 20(11): 1338 - 1354.
[44].Ashok Halambi, Peter Grun, Vijay Ganesh, et al., EXPRESSION: A Language for Architecture Exploration through Compile/Simulator Retargetability. Proceedings of DATE, 1999, 9(12): 485 - 490.
[45].P.Grun, A.Halambi,A.Khare,et al; EXPRESSION:An ADL for system level design exploration. Tech Report TR 98-29 , University of California , Irvine, 1998
[46].Russell Priebe, Cary Ussery. A configurable platform for advanced system-on-a-chip applications. In: ICSPA T2000.Dallas, TX, USA, 2000
[47].Marc Tremblay, Jeffrey Chan, et al. The MAJC architecture: A synthesis of parallelism and scalability.IEEE M icro, 2000, 20 (6): 12— 25
[48].Li Li, Minglun Gao, Zuoren Cheng, Duoli Zhang, et al A new platform-based orthogonal SoC design methodology[A], ASIC[C], 2003:428-432.
[49].Ahdina M, Monteiro J, Devadas S.Precomputation-based sequential logic optimization for low power.IEEE Trans on VLSI Systems, 1994, 2(4):426～ 436
[50].Benini L, De Micheli G.Transformation and synthesis of FSMs for low power gated clock implementation.IEEE Trans on CAD, 1996, 15(6):630～643
[51].Tiwari V, Malik S, Ashar P.Guarded evaluation:pushing power management to logic synthesis/design.ACM/IEEE ISLPD, 1995, 221 —226
[52].Tensilica. Xtensa http://www.tensilica.com, 2001.
[53].R. Gonzales. Xtensa: A Configurable and Extensible Processor. IEEE Micro, 20(2):60-70, Mar. 2000.
[54].ARC Cores Ltd. ARC Programmers Reference Manual, Dec. 1999.
[55].ARC Cores Ltd. ARCtangent Processor, http://www.arccores.com, 2001.
[56].Cary Ussery. Configurable Processing Platforms: Redefining SoC. http://www.improvsys.com, 2001.
[57]. S.H. Leibson. Jazz Joins VLIW Juggernaut - CMP and Java as an HDL Take System-on-Chip. Design to Parallel Universe. Microprocessor Report, 2000.
[58].P. Kievits, E. Lambers, C. Moerman, and R. Woudsma. R.E.A.L. DSP Technology for Telecom Baseband Processing. Proc. of the Int. Conf. on Signal Processing Applications and Technology (ICSPAT), Toronto, CA, 1998.
[59].Kucukcakar, K. , et al, "Matisse: An Architectural Design Tool for Commodity ICs," IEEE Design & Test of Computers, April-June 1998
[60].D. Knapp and M. Winslett, "A Prescriptive Formal Model for Data-Path Hardware," IEEE Trans. Computer-Aided Design, Vol. 11, No. 2, Feb. 1992, pp.158-184.
[61].D. Gajski et al., A Design Methodology and Environment for Interactive Bahavioral Synthesis, Tech. Report 96-29, Dept. of Information and Computer Science, Univ. of California, Irvine, 1996.
[62].A.A. Jerraya, I. Park, and K. O'Brien, "Amical: An Interactive High Level Synthesis Environment," Proc. European Design Automation Conf., IEEE Computer Society Press, Los Alamitos, Calif., 1993, pp. 58-63.
[63].B. Shackleford, M. Yasuda, E. Okushi, H. Koizumi, H. Tomiyama, and H. Yasuura. Satsuki: An Integrated Processor Synthesis and Compiler Generation System. In IEICE Transactions on Information and Systems, pages 1373 - 1381, 1996.
[64].I.J. Huang and A.M. Despain. Synthesis of Instruction Sets for Pipelined Microprocessors. In Proc. of the Design Automation Conference (DAC), Jun. 1994.
[65].I.J. Huang, B. Holmer, and A.M. Despain. ASIA: Automatic Synthesis of Instruction-Set Architectures. In Proc. of the SASIMI Workshop, Oct. 1993.
[66]. P. Paulin, C. Liem, T.C. May, and S. Sutarwala. Flex Ware: A Flexible Firmware Development Environment for Embedded Systems. In Code Generation for Embedded Processors, Editors: P. Marwedel and G. Goossens. Kluwer Academic Publishers, 1995.
[67].P. Paulin, C. Liem, C. May, and S. Sutarwala. CodeSyn: A Retargetable Code Synthesis System. In Proc. of the Int. Symposium on System Synthesis (ISSS), May 1994.
[68].Pieter J. Schoenmakers and J. Frans M. Theeuwen. Clock Gating on RT-Level VHDL. Proc. of the Int. Workshop on Logic Synthesis, Tahoe City, CA, pages 387-391, June 7 - 10, 1998.
[69].Santosh Abraham, Bob Rau, Robert Schreiber, Greg Snider, and Michael Schlansker. Efficient Design Space Exploration in PICO. Proc. of the Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), pages 71-79, Nov. 2000.
[70].Yanagisawa, H.; Uehara, M.; Mori, H.; Development methodology of ASIP based on Java byte code using HW/SW co-design system for processor design. Distributed Computing Systems Workshops , 2004. Proceedings. 24th International Conference on 2004 Page(s):831 - 837
[71].M. Itoh, S. Higaki, J. Sato, A. Shiomi, Y. Takeuchi A. Kitajima, and M. Imai. PEAS-III: An ASIP Design Environment. In Proc. of the Int. Conf. on Computer Design (ICCD), Sep. 2000.
[72].A. Kitajima, M. Itoh, J. Sato, A. Shiomi, Y. Takeuchi, and M. Imai. Effectiveness of the ASIP Design System PEAS-III in Design of Pipelined Processors. In Proc. of the Asia South Pacific Design Automation Conference (ASPDAC), Jan. 2001.
[73]J.-H. Yang, B.-W. Kim, S.-J. Nam, Y.-S. Kwon, D.-H. Lee, J.-Y. Lee, C- S. Hwang, Y.-H. Lee, S.-H. Hwang, I.-C. Park, and C.-M. Kyung. MetaCore: An Application-Specific Programmable DSP Development System. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(2): 173-183, Apr. 2000.
[74]．李曦：片上系统(SOC)的体系结构设计方法与功耗模型研究，中国科学技术大学博士学位论文，2003
[75]. D. E. Thomas nad R moorby. The Verilog Hardware Description Language. Kluwer Academic Publishers, 1991
[76]. D. D. Gajski, F. Vahid, S Narayan. A system-desing methodology: Executablespecification refinement. EDAC 1994
[77]. W3C,http://www.w3c.org/xml/
[78]. tolemy,http://ptolemy.eecs.berkeley.edu/
[79]. W3C,http://www.w3c.org/schema/
[80]. Doug Burger, Todd M. Austin: The SimpleScalar Tool Set, Version 2.0[R], University of Wisconsin-Madison Computer Sciences Department Technical Report #1342, June, 1997.
[81]. E. S. Davidson, L. E. Shar, A. T. Thomas, and J. H. Patel, "Effective Control for Pipelined Computers", in the Spring COMPCON'75 Digest of Papers, 181-184, February 1975
[82]. H. Zhong, and S. Mahlke. Processor acceleration through automated instruction set customisation. In Diego, Calif. Dec. 2003.
[83]．李曦，王志刚，周学海，王煦法，面向低功耗优化设计的系统级功耗模型研究，电子学报，Vol 32，No 2，2004
[84]. Yun Zhu, Xi Li, Laurence T. Yang, Jun Yang. A Fast Instruction Set Evaluation Method for ASIP Designs.EUC-06, acccpted
[85]. M. Martonosi, D. Brooks and P. Bose, Modeling and Analyzing CPU Power and Performance: Metrics, Methods and Abstractions; Tutorial presentation at ACM Sigmetrics-2001, June 17, 2001.
[86]. Weiyu Tang; Gupta, R.; Nicolau, A., Power savings in embedded processors through decode filter cache, Design, Automation and Test in Europe Conference and Exhibition, 2002. Pages: 443-448.
[87]. Bajwa, R. S.; Hiraki, M.; et al, Instruction buffering to reduce power in processors for signal processing, Very Large Scale Integration (VLSI) Systems, Dec. 1997. Pages: 417-424.
[88]. Lea Hwang Lee; Moyer, B.; Mends, J., Low-cost embedded program loop caching-revisited, Tech. rep., EECS, University of Michigan, December 1999.
[89]. Lea Hwang Lee; Moyer, B.; Arends, J., Instruction fetch energy reduction using loop caches for embedded applications with small tight loops, Low Power Electronics and Design, 1999. Proceedings. Pages:267 - 269.
[90].Vander An, T.; Jayapala, M.; Barat, F; Deconinck, G., Instruction buffering exploration for low energy VLIWs with instruction clusters, Design Automation Conference, 2004. Pages:825 - 830.
[91].Panis, C.; Grunbacher, H.; Nurmi, J., A scalable instruction buffer and align unit for xDSPcore, Solid-State Circuits, IEEE Journal of, Volume: 39 , Issue: 7 , July 2004. Pages: 1094-1100.
[92].Hiraki, M.; Bajwa, R.S.; Kojima, H.; Gorny, D.J.; Nitta, K.; Shri, A., Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer, Low Power Electronics and Design, 1996. Pages:353-358.
[93].Guthaus M.R., Ringenberg J.S., et al. MiBench: A free, commercially representative embedded benchmark suite [C]. IEEE International Workshop on Workload Characterization. Austin, 2001: 3 -14.
[94].Se-Hyun Yang, Powell M.D., et al. Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay [C]. Proceedings. Eighth International Symposium on High-Performance Computer Architecture. 2002: 151-161.
[95].Serge Leef, "A Methodology for Virtual Hardware/Software Integration", Mentor, 1998
[96].R K Gupta, Y Zorian. Introducing core base system design. IEEE Design & Test of Computers, 1997,14 (4) : 15-25
[97].R Ernst, .Codesign of embedded systems: status and trends. IEEE Design & Test of Computers, 1998,15(2):45-54
[98]. A Ferrari ,et al . System design :Traditional concepts and new paradigms. ICCD' 1999. Austin ,Texas ,1999. 2 -12.
[99]. L P Carloni , et al . The art and science of integrated systems design. In Proceedings of the 28th European Solid2State Circuits Conference. Firenze ,Italy ,2002. 25 - 36.
[100]. Bob Altizer. Platform2based design :the next reuse frontier. Embedded Systems Conference. San Francisco ,2002.
[101]. Huiyang Zhou, Toburen M.C., Rotenberg E., et al. Adaptive mode control: a static-power-efficient cache design [C]. Proceedings. 2001 International Conference on Parallel Architectures and Compilation Techniques. Barcelona, 2001:61-70.
[102]. Ranganathan P., Adve S., Jouppi, N.P. Reconfigurable caches and their application to media processing [C]. Proceedings of the 27th International Symposium on Computer Architecture. Vancouver, Canada, 2000: 214-224.
[103]. Wilton S., Jouppi N. P.: CACTI: An Enhanced Cache Access and Cycle Time Model [J]. IEEE Journal of Solid State Circuits, 1996, vol. 31, no. 5: 677-688
[104]. Shivakumar R, Jouppi N. P.: CACTI 3.0: An integrated cache timing, power and area model. Western Research Laboratory. Technical Report, 2001
[105]. David Tarjan: CACTI 4.0 Beta. http://analog.cs.virginia.edu:81/cacti/
[106]. Susan L. Graham, Peter B. Kessler, Marshall K. McKusick: gprof: a Call Graph Execution Profiler, SIGPLAN '82 Symposium on Compiler Construction, 1982, Pages: 120-126
[107]. Robert Cmelik, David Keppel: Shade: A Fast Instruction Set Simulator for Execution Profiling, Performance Evaluation Review, 1994, Pages: 128-137.
[108]. ExoLab Group: The Castor Project, http://castor.exolab.org/
[109]．陆岚：嵌入式系统可重定向功耗优化编译器研究，中国科学技术大学博士学位论文，2004
[110]．苏鹤年，李曦，王志刚，杨君：基于语言的ASIP系统级综合方法研究，微型机与应用，已录用
[111]．余洁，李曦等．可重定向的周期精确模拟器生成环境的研究．小型微型计算机系统，已录用
[112]. SPEC web99 Design Document. http://www.specbench.org/osg/web99/docs/whitepaper.html
[113]. Transaction Processing Performance Council, TPC Benchmark. http://www.tpc.org/information/benchmarks.asp
[114]. A. Malik, B. Moyer and D. Cermak, "A Low Power Unified Cache Architecture Providing Power and Performance Flexibility," Int. Symp. on Low Power Electronics and Design, June 2000.
[115]. C. Lee, M. Potkonjak and W. Mangione-Smith,"MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems," Int. Symp. On Microarchitecture, 1997.
[116]. D. C. Suresh, W. A. Najjar, F. Vahid, et al, Profiling tools for hardware/software partitioning of embedded applications. Compilers and Tools for Embedded Systems (LCTES), 2003, pp. 189-198
[117]. Weiyu Tang; Rajesh Gupta; Alexandru Nicolau."Power Savings in Embedded Processors through Decode Filter Cache" Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE.02) 1530-1591/02 2002 IEEE
[118]. Devadas S, Newton A R.Decomposition and factorization of sequential finite state machines.IEEE Trans on CAD, 1989, 8(11):1206—1217
[119]. Lin B, Newton A R, Implicit manipulation of equivalence classes using binary decision diagrams.IEEE ICCD , 1991, 81 — 85
[120]. Tsui C Y, Pedram M, Despain A M.Low power state assignment targeting two-and multilevel logic implementations.IEEE/ACM ICCAD, San Jose, CA, 1994, 82—87
[121]. Iman S, Pedram M. POSE: Power optimization and synthesis enviorment. In: IEEE eds. Proc 33rd ACM/IEEE Design Automation Conf. San Jose: IEEE Press. 1996.21—26
[122]. Gebotys C H.Low energy memory and register allocation using network flow.In:34th ACM/IEEE DAC, Anaheim, CA 1997, 435—440