功耗分析攻击研究及抗功耗分析攻击密码芯片设计
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摘要
密码模块部分是信息安全系统的关键部件,其安全性的高低直接关乎整个信息系统的安全。21世纪以前的大部分时间,对密码模块的攻击主要集中在数学分析上,主要是是以线性攻击和差分攻击为代表的传统密码分析方法,通过利用密码算法的统计特性,通过分析所选择的明密文对来获取密钥。这类攻击一般需要获取和处理巨量的数据,实际中并不总是可行的。于是有人开始分析用另外的思路,对实际工作的密码芯片进行攻击,考虑到密码芯片实际工作中总会释放一些物理信息,比如芯片工作时的电流、电压、电磁信息,以及与这些信息有关的时间信息,通过分析这些外漏的物理信息来对芯片进行攻击,这就是旁道攻击(Side Channel Attack, SCA).
从21世纪开始,功耗分析攻击成了一个针对实现的密码芯片进行旁道攻击的主要方法。它主要分为三种：简单功耗分析攻击、差分功耗分析攻击、相关性功耗分析攻击。简单功耗攻击(Simple Power Analysis Attack, SPA)利用加密操作过程中的密钥位与芯片实际功耗之间的关系直接从实际测量的功耗曲线获取密钥信息。差分功耗分析攻击(Differential Power Analysis Attack, DPA)是通过对大量明文或密文和功耗曲线的的统计分析来获取密钥信息。相关性功耗分析攻击(Correlation Power Analysis Attack, CPA)是通过事先预设一个预测模型,用其进行密码运算,得出预测的功耗信息,然后用实际的芯片进行运算,实际的功耗与预测的功耗进行相关性对比分析,从而推测出芯片的实际工作密钥。
功耗分析理论的出现给密码芯片带来了很大的安全性问题,许多文献给出了对实际密码芯片成功进行功耗攻击的实例。本文主要对几种主要的密码算法进行功耗分析研究。研究的目的,一是对密码算法进行研究,找出其实现过程中易受功耗攻击的原因；二是为了芯片设计时增加相应地防御措施以增强其抵御功耗分析攻击的能力。本文主要有如下贡献和创新点：
功耗分析平台设计与实现：为了对抗功耗攻击,密码算法在实现过程中就必须考虑抗功耗攻击的问题,因此需要一个芯片流片前评估其抗功耗分析攻击能力的平台。为此,本文通过将PC应用程序和FPGA硬件相结合设计了一种功耗分析评估平台。
基于高性能FPGA设计实现的功耗分析平台,不仅可以实现对单独的密码算法模块进行功耗分析实验,而且还可以对设计的整个芯片进行抗功耗分析能力评估。功耗分析平台的实现不仅为密码算法功耗分析的研究提供了一个实践平台,而且为密码芯片的抗功耗分析能力提供了评价平台。
RSA算法功耗分析研究和抗功耗分析攻击的USB KEY芯片设计USB Key里面常用的的公钥算法RSA易受功耗分析攻击的困扰。本文首先针对RSA算法进行了研究,通过分析知道RSA模块易受功耗分析攻击的原因是其算法中模幂运算实现的方式造成的。其模幂运算实现的基本方式是利用平方-乘积算法原理来实现,这种实现方式使得RSA运算时产生的功耗与运算密钥的每一个比特位密切相关,攻击者通过采集其工作时泄露的功耗信息进行分析,从而导致密钥被解析,因此安全性受到很大的威胁。为抵御SPA和DPA的攻击,本文提出了在模幂算法实现方式上增加随机伪操作数和应用随机混合模幂的防御算法。然后利用该算法在FPGA上实现了RSA模块并通过了仿真验证。最后在FPGA上实现了USB Key的全部设计,并围绕该FPGA搭建了功耗分析测试硬件平台,利用该平台进行功耗攻击实验。通过对基于LR模幂算法的DPA攻击和基于固定的混合模幂算法的DPA攻击,本文验证了上述模幂实现方式确实容易被DPA攻击。最后对本文提出的基于增加随机伪操作数和应用随机混合模幂的防御算法进行DPA攻击,攻击结果表明,该防御算法可以有效地防御MESD攻击。
AES算法功耗分析研究和抗功耗分析攻击的高速密码协处理器设计：为了设计具有抗功耗分析能力的AES算法模块,首先研究了AES的基本原理以及算法流程,研究了其易受功耗攻击的原因,以及相应的攻击算法。然后提出了增加掩码覆盖的防御方案。完成了抗功耗分析的AES密码模块设计,考虑到安全性和可实现性的平衡,采用了固定几个掩码,随机选择的方案以求达到近似随机掩码的目的。为了加快AES模块的运行速度,采用4级流水线设计,每3个时钟就可以完成一次加解密操作。在高速密码协处理器的设计中,内部运行机制采用并行调度机制,最大化的发挥了AES密码模块的性能。高速密码协处理器的功耗分析实验结果表明,没有掩码保护的设计,难以避免DPA攻击,加了掩码措施后,可以有效地抵御DPA攻击。
The cipher modules are key components of the information security system, its security level is directly related to the safety of the whole information system.21centuries ago, most of the time, the attack on the cipher module focused on the math-ematical analysis. Linear attack and differential attack were representative of the traditional cryptanalysis method. By utilizing the statistical properties of the cipher algorithm, by analyzing the selected plaintext or ciphertext to obtain the key. Such attacks generally need to acquire and process a huge amount of data, the practice is not always feasible. Thus someone started to analyze other ideas. Taking into account the actual fact that cipher chips always release some of the physical information when in working state, such as current, voltage, electromagnetic, as well as the time related information.By analyzing the physical information leakage to attack the chip, this is called side-channel attack
From the beginning of the21st century, power analysis attack became main side-channel attack which is usually divided into three kinds:simple power analysis attack, differential power analysis attack, correlation power analysis attack. Simple power at-tack (SPA) using the relationship between the key bits in the encryption process and the actual power consumption of the chip to acquire the key information directly from the power consumption curve of the actual measurement. Differential power analysis attack (DPA) is a method by statistically analyzing large number of plaintext or cipher-text and power curves to obtain key. Correlation power analysis attack (CPA) firstly utilizes a forecast model used for cryptographic operations to draw predicted power consumption information, by correlatively comparing actual chip power consumption with predicted power consumption to infer actual key.
The emergence of Power analysis theory against cipher chip has brought a lot of security issues, many literature showed examples of the successful power attacks. In this paper, we focused on several cipher algorithms to carry on power analysis research. The purpose of the study, is to find out the vulnerability of cipher algorithms,and then add countermeasures to resist the threat. Main contributions of the thesis are as follows::
Power analysis platform construction:To resist the threat of power attack, countermeasures must be taken into account when realizing the cipher algorithms.In this paper, by combinating PC applications with FPGA hardware,we designed a power analysis evaluation platform. Implementation of power analysis platform based on high-performance FPGA design, not only can carry out power analysis experiments for separate cipher modules, but also has the capability to assess anti-power analysis capabilities for the design of cipher chip.
RSA algorithm power analysis research and USB KEY chip design:
Public key algorithm RSA is vulnerable to power analysis attacks. Firstly.by analyzing the RSA algorithm we know that the the RSA module vulnerable to power analysis attacks is due to the Modular exponentiation algorithm implementations. The basic approach to realize modular exponentiation is square-product algorithm which makes RSA each bit of key is closely related to power consumption. Attacker analyzed the consumption information then got the key.Therefore it is a great threat to the se-curity. To counter SPA and DPA attacks, we proposed a scheme by adopting random mixed modular exponentiation algorithm plus adding random pseudo-operands to re-alize modular exponentiation algorithm.The modified RSA module was implemented in FPGA and verified. Implemented on FPGA, USB Key power analysis test hard-ware platform was established. DPA attack to RSA which was based on the LR mode algorithm and fixed mixed modular exponentiation algorithm was carried out.Results showed they are easy to be attack. Finally, our proposed scheme was also tested, results showed our scheme is strong enough to sustain MESD attack.
AES algorithm power analysis and high-speed cipher coprocessor de-sign:In order to design the AES algorithm module which has the ability of anti-power analysis,firstly the basic principle of AES algorithm flow, reasons for their vulnerabil-ity to power attack, as well as the corresponding attack algorithm were studied.And then we proposed our Mask covering scheme which enhanced the ability to counter power analysis attack.We completed the design of AES cipher module.Taking into ac- count the balance between security and resource,our scheme was achieved by using several fixed masks with random Selecting to achieve the purpose of approximation of random mask.In order to speed up the the AES module running speed, four pipeline design was implemented, every three clock time encryption and decryption can be done.In the design of high-speed cryptographic coprocessor, internal operation mecha-nism was parallel scheduling mechanism, thus maximized AES cryptographic module performance.The high-speed cryptographic coprocessor power analysis results showed that design with no mask protected is difficult to prevent the DPA attack, design with mask protected can effectively prevent the DPA attack.
从21世纪开始,功耗分析攻击成了一个针对实现的密码芯片进行旁道攻击的主要方法。它主要分为三种：简单功耗分析攻击、差分功耗分析攻击、相关性功耗分析攻击。简单功耗攻击(Simple Power Analysis Attack, SPA)利用加密操作过程中的密钥位与芯片实际功耗之间的关系直接从实际测量的功耗曲线获取密钥信息。差分功耗分析攻击(Differential Power Analysis Attack, DPA)是通过对大量明文或密文和功耗曲线的的统计分析来获取密钥信息。相关性功耗分析攻击(Correlation Power Analysis Attack, CPA)是通过事先预设一个预测模型,用其进行密码运算,得出预测的功耗信息,然后用实际的芯片进行运算,实际的功耗与预测的功耗进行相关性对比分析,从而推测出芯片的实际工作密钥。
功耗分析理论的出现给密码芯片带来了很大的安全性问题,许多文献给出了对实际密码芯片成功进行功耗攻击的实例。本文主要对几种主要的密码算法进行功耗分析研究。研究的目的,一是对密码算法进行研究,找出其实现过程中易受功耗攻击的原因；二是为了芯片设计时增加相应地防御措施以增强其抵御功耗分析攻击的能力。本文主要有如下贡献和创新点：
功耗分析平台设计与实现：为了对抗功耗攻击,密码算法在实现过程中就必须考虑抗功耗攻击的问题,因此需要一个芯片流片前评估其抗功耗分析攻击能力的平台。为此,本文通过将PC应用程序和FPGA硬件相结合设计了一种功耗分析评估平台。
基于高性能FPGA设计实现的功耗分析平台,不仅可以实现对单独的密码算法模块进行功耗分析实验,而且还可以对设计的整个芯片进行抗功耗分析能力评估。功耗分析平台的实现不仅为密码算法功耗分析的研究提供了一个实践平台,而且为密码芯片的抗功耗分析能力提供了评价平台。
RSA算法功耗分析研究和抗功耗分析攻击的USB KEY芯片设计USB Key里面常用的的公钥算法RSA易受功耗分析攻击的困扰。本文首先针对RSA算法进行了研究,通过分析知道RSA模块易受功耗分析攻击的原因是其算法中模幂运算实现的方式造成的。其模幂运算实现的基本方式是利用平方-乘积算法原理来实现,这种实现方式使得RSA运算时产生的功耗与运算密钥的每一个比特位密切相关,攻击者通过采集其工作时泄露的功耗信息进行分析,从而导致密钥被解析,因此安全性受到很大的威胁。为抵御SPA和DPA的攻击,本文提出了在模幂算法实现方式上增加随机伪操作数和应用随机混合模幂的防御算法。然后利用该算法在FPGA上实现了RSA模块并通过了仿真验证。最后在FPGA上实现了USB Key的全部设计,并围绕该FPGA搭建了功耗分析测试硬件平台,利用该平台进行功耗攻击实验。通过对基于LR模幂算法的DPA攻击和基于固定的混合模幂算法的DPA攻击,本文验证了上述模幂实现方式确实容易被DPA攻击。最后对本文提出的基于增加随机伪操作数和应用随机混合模幂的防御算法进行DPA攻击,攻击结果表明,该防御算法可以有效地防御MESD攻击。
AES算法功耗分析研究和抗功耗分析攻击的高速密码协处理器设计：为了设计具有抗功耗分析能力的AES算法模块,首先研究了AES的基本原理以及算法流程,研究了其易受功耗攻击的原因,以及相应的攻击算法。然后提出了增加掩码覆盖的防御方案。完成了抗功耗分析的AES密码模块设计,考虑到安全性和可实现性的平衡,采用了固定几个掩码,随机选择的方案以求达到近似随机掩码的目的。为了加快AES模块的运行速度,采用4级流水线设计,每3个时钟就可以完成一次加解密操作。在高速密码协处理器的设计中,内部运行机制采用并行调度机制,最大化的发挥了AES密码模块的性能。高速密码协处理器的功耗分析实验结果表明,没有掩码保护的设计,难以避免DPA攻击,加了掩码措施后,可以有效地抵御DPA攻击。
The cipher modules are key components of the information security system, its security level is directly related to the safety of the whole information system.21centuries ago, most of the time, the attack on the cipher module focused on the math-ematical analysis. Linear attack and differential attack were representative of the traditional cryptanalysis method. By utilizing the statistical properties of the cipher algorithm, by analyzing the selected plaintext or ciphertext to obtain the key. Such attacks generally need to acquire and process a huge amount of data, the practice is not always feasible. Thus someone started to analyze other ideas. Taking into account the actual fact that cipher chips always release some of the physical information when in working state, such as current, voltage, electromagnetic, as well as the time related information.By analyzing the physical information leakage to attack the chip, this is called side-channel attack
From the beginning of the21st century, power analysis attack became main side-channel attack which is usually divided into three kinds:simple power analysis attack, differential power analysis attack, correlation power analysis attack. Simple power at-tack (SPA) using the relationship between the key bits in the encryption process and the actual power consumption of the chip to acquire the key information directly from the power consumption curve of the actual measurement. Differential power analysis attack (DPA) is a method by statistically analyzing large number of plaintext or cipher-text and power curves to obtain key. Correlation power analysis attack (CPA) firstly utilizes a forecast model used for cryptographic operations to draw predicted power consumption information, by correlatively comparing actual chip power consumption with predicted power consumption to infer actual key.
The emergence of Power analysis theory against cipher chip has brought a lot of security issues, many literature showed examples of the successful power attacks. In this paper, we focused on several cipher algorithms to carry on power analysis research. The purpose of the study, is to find out the vulnerability of cipher algorithms,and then add countermeasures to resist the threat. Main contributions of the thesis are as follows::
Power analysis platform construction:To resist the threat of power attack, countermeasures must be taken into account when realizing the cipher algorithms.In this paper, by combinating PC applications with FPGA hardware,we designed a power analysis evaluation platform. Implementation of power analysis platform based on high-performance FPGA design, not only can carry out power analysis experiments for separate cipher modules, but also has the capability to assess anti-power analysis capabilities for the design of cipher chip.
RSA algorithm power analysis research and USB KEY chip design:
Public key algorithm RSA is vulnerable to power analysis attacks. Firstly.by analyzing the RSA algorithm we know that the the RSA module vulnerable to power analysis attacks is due to the Modular exponentiation algorithm implementations. The basic approach to realize modular exponentiation is square-product algorithm which makes RSA each bit of key is closely related to power consumption. Attacker analyzed the consumption information then got the key.Therefore it is a great threat to the se-curity. To counter SPA and DPA attacks, we proposed a scheme by adopting random mixed modular exponentiation algorithm plus adding random pseudo-operands to re-alize modular exponentiation algorithm.The modified RSA module was implemented in FPGA and verified. Implemented on FPGA, USB Key power analysis test hard-ware platform was established. DPA attack to RSA which was based on the LR mode algorithm and fixed mixed modular exponentiation algorithm was carried out.Results showed they are easy to be attack. Finally, our proposed scheme was also tested, results showed our scheme is strong enough to sustain MESD attack.
AES algorithm power analysis and high-speed cipher coprocessor de-sign:In order to design the AES algorithm module which has the ability of anti-power analysis,firstly the basic principle of AES algorithm flow, reasons for their vulnerabil-ity to power attack, as well as the corresponding attack algorithm were studied.And then we proposed our Mask covering scheme which enhanced the ability to counter power analysis attack.We completed the design of AES cipher module.Taking into ac- count the balance between security and resource,our scheme was achieved by using several fixed masks with random Selecting to achieve the purpose of approximation of random mask.In order to speed up the the AES module running speed, four pipeline design was implemented, every three clock time encryption and decryption can be done.In the design of high-speed cryptographic coprocessor, internal operation mecha-nism was parallel scheduling mechanism, thus maximized AES cryptographic module performance.The high-speed cryptographic coprocessor power analysis results showed that design with no mask protected is difficult to prevent the DPA attack, design with mask protected can effectively prevent the DPA attack.
引文
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