10bit 100MSPS Pipeline ADC关键电路模块的研究与设计
摘要
人类生活的真实世界都是一些模拟的物理量，而现代科技的发展，数字处理技术越来越成熟。由于数字处理有许多优点，所以一般人们都希望用数字技术来处理真实的物理量,而这就需要先把真实世界中的模拟量转换为数字量。模数转换器（Analog-to-digital converter,ADC）就是连接真实世界和离散的数字运算领域的关键元件之一。相比较其它种类的模数转换器，流水线式模数转换器（Pipeline ADC）不仅可以保证高速的工作，也可以实现8位以上的分辨率，因而成为高速、高精度模数转换器的主流。本文针对10bit 100MSPSPipeline ADC的设计技术进行研究，分析了Pipeline ADC中的误差来源和非理想的因素，提出了1.5位/级的系统结构。在此基础上以CSMC公司的0.18μm 1P6M CMOS混合信号工艺对10bit 100MSPS PipelineADC中的采样保持电路、流水线转换电路及时钟产生电路等关键电路模块进行设计。具体如下：
（1）设计完成电容翻转式的采样保持电路（sample-and-hold）从而获取高速的前端采样，应用下极板采样技术减小电荷注入和时钟馈通效应；设计了栅压自举开关提高了采样的线性度，利用增益自举技术设计完成用于采样保持电路和第一级余量增益电路（Multiplying Digital-Analog Converter，MDAC）的全差分高速高增益跨导运算放大器（OTA）。
（2）设计完成10bit 100MSPS Pipeline ADC中第一级流水线转换电路，包括1.5位/级的子ADC电路和余量增益电路（Multiplying Digital-Analog Converter，MDAC）。采用了动态比较器来降低每个流水级的功耗；利用栅压自举采样开关和底极板采样技术减少时钟馈通和电荷注入效应。
（3）设计完成10bit 100MSPS Pipeline ADC中时钟产生电路、基准电压、偏置电流源等辅助模块。利用延迟锁相环路产生两相不交叠的主时钟和其辅助时钟。利用高阶温度补偿技术降低带隙基准的温漂系数，完成为ADC系统提供比较电压和偏置电流的高精度低温漂的带隙基准源（Bandgap）。
本文对所设计的电路模块进行了版图的设计和后仿真，后仿真结果表明，采样保持电路的信噪失真比（SNDR）为78.8dB，有效位数（ENOB）为12.8位，无杂散动态范围(SFDR)为79.6dB；子ADC电路完成了本级的数模转换功能；余量增益电路完成采样保持、减法和2倍增益放大的功能。所设计的电路模块均满足10bit 100MSPS Pipeline ADC系统的要求。
The real world of human’s life are physical quantities which is called analog signal,whilewith the development of modern technology, the digital processing technology become more andmore matured. As digital processing has many advantages, generally people want to use digitaltechnology to deal with the real physical quantities. And it is required that the analog signal of thereal word to be converted to digital signal for processing. The ADC (Analog-to-digital converter)is the key component that connect the real world and digital computing areas. Compared to othertypes of ADC, pipeline ADC can not only guarantee high-speed work, but also achieve more than8-bit resolution.So it has became the mainstream of the high-speed, high precision analog todigital converter. This paper firstly describes the working principle and the classification of theADC and then research the 10bit 100MSPS pipeline ADC design technology, analys the sourcesof pipeline ADC’s error and non-ideal factors, and design the key cells of 10bit 100MSPSpipeline ADC in CSMC 0.18μm 1P6M CMOS mixed-signal technology, the work that hascompleted are summarized as follows:
(1) The capacitor flip-around architecture sample and hold (S/H) circuit is completed toachieve high speed front end sampling, the bottom plate sampling techniques are adopted toreduce clock feed-through reduction and charge injection effects. Bootstrapped Sampling Switchis designed to Improve the linearity of the sample and hold circuit. The high-speed high-gain fullydifferential operational transconductance amplifier with gain-booster which could be used insample and hold circuit and the first class multiplying digital-analog Converter (MDAC) circuit isdesigned.
(2) The first stage converter circuit of 10bits 100MSPS pipeline ADC is completed include1.5bit/stage subADC circuit and multiplying digital-analog converter (MDAC) circuit. Thedynamic comparator is adopted to reduce reduce the power consumption of each stage.Bootstrapped Sampling Switch and bottom plate sampling techniques are adopted to reduce clockfeed-through reduction and charge injection effects.
(3) The clock generator, voltage reference ,bias current source and other auxiliary modules of10bit 100MSPS pipeline ADC are completed. The delay locked loop is used to generate twophases non-overlapping clock and the auxiliary clock. High precision low temperature driftbandgap voltage reference adopted high-temperature compensation technology which is used toprovide reference voltage and bias current for the ADC system is completed.
In this paper, all the circuit modules' layout and post simulation are done. The post simulation results show that the S/H circuit achieves SNDR of 78.8dB, ENOB of 12.8, SFDR of79.6dB; the subADC circuit achieve the function of analog to digital;The MDAC circuit achievethe function of sample and hold, subtraction, and 2 times gain. All the designed circuit modulesmeet the 10bits 100MSPS Pipelined ADC system’s requirements.
（1）设计完成电容翻转式的采样保持电路（sample-and-hold）从而获取高速的前端采样，应用下极板采样技术减小电荷注入和时钟馈通效应；设计了栅压自举开关提高了采样的线性度，利用增益自举技术设计完成用于采样保持电路和第一级余量增益电路（Multiplying Digital-Analog Converter，MDAC）的全差分高速高增益跨导运算放大器（OTA）。
（2）设计完成10bit 100MSPS Pipeline ADC中第一级流水线转换电路，包括1.5位/级的子ADC电路和余量增益电路（Multiplying Digital-Analog Converter，MDAC）。采用了动态比较器来降低每个流水级的功耗；利用栅压自举采样开关和底极板采样技术减少时钟馈通和电荷注入效应。
（3）设计完成10bit 100MSPS Pipeline ADC中时钟产生电路、基准电压、偏置电流源等辅助模块。利用延迟锁相环路产生两相不交叠的主时钟和其辅助时钟。利用高阶温度补偿技术降低带隙基准的温漂系数，完成为ADC系统提供比较电压和偏置电流的高精度低温漂的带隙基准源（Bandgap）。
本文对所设计的电路模块进行了版图的设计和后仿真，后仿真结果表明，采样保持电路的信噪失真比（SNDR）为78.8dB，有效位数（ENOB）为12.8位，无杂散动态范围(SFDR)为79.6dB；子ADC电路完成了本级的数模转换功能；余量增益电路完成采样保持、减法和2倍增益放大的功能。所设计的电路模块均满足10bit 100MSPS Pipeline ADC系统的要求。
The real world of human’s life are physical quantities which is called analog signal,whilewith the development of modern technology, the digital processing technology become more andmore matured. As digital processing has many advantages, generally people want to use digitaltechnology to deal with the real physical quantities. And it is required that the analog signal of thereal word to be converted to digital signal for processing. The ADC (Analog-to-digital converter)is the key component that connect the real world and digital computing areas. Compared to othertypes of ADC, pipeline ADC can not only guarantee high-speed work, but also achieve more than8-bit resolution.So it has became the mainstream of the high-speed, high precision analog todigital converter. This paper firstly describes the working principle and the classification of theADC and then research the 10bit 100MSPS pipeline ADC design technology, analys the sourcesof pipeline ADC’s error and non-ideal factors, and design the key cells of 10bit 100MSPSpipeline ADC in CSMC 0.18μm 1P6M CMOS mixed-signal technology, the work that hascompleted are summarized as follows:
(1) The capacitor flip-around architecture sample and hold (S/H) circuit is completed toachieve high speed front end sampling, the bottom plate sampling techniques are adopted toreduce clock feed-through reduction and charge injection effects. Bootstrapped Sampling Switchis designed to Improve the linearity of the sample and hold circuit. The high-speed high-gain fullydifferential operational transconductance amplifier with gain-booster which could be used insample and hold circuit and the first class multiplying digital-analog Converter (MDAC) circuit isdesigned.
(2) The first stage converter circuit of 10bits 100MSPS pipeline ADC is completed include1.5bit/stage subADC circuit and multiplying digital-analog converter (MDAC) circuit. Thedynamic comparator is adopted to reduce reduce the power consumption of each stage.Bootstrapped Sampling Switch and bottom plate sampling techniques are adopted to reduce clockfeed-through reduction and charge injection effects.
(3) The clock generator, voltage reference ,bias current source and other auxiliary modules of10bit 100MSPS pipeline ADC are completed. The delay locked loop is used to generate twophases non-overlapping clock and the auxiliary clock. High precision low temperature driftbandgap voltage reference adopted high-temperature compensation technology which is used toprovide reference voltage and bias current for the ADC system is completed.
In this paper, all the circuit modules' layout and post simulation are done. The post simulation results show that the S/H circuit achieves SNDR of 78.8dB, ENOB of 12.8, SFDR of79.6dB; the subADC circuit achieve the function of analog to digital;The MDAC circuit achievethe function of sample and hold, subtraction, and 2 times gain. All the designed circuit modulesmeet the 10bits 100MSPS Pipelined ADC system’s requirements.
引文
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[2] K. Bult, G. Geelen. A Fast-Settling CMOS Opamp for SC Circuits with 90-dB DC Gain. IEEE J. Solid-State Circuits. 1990,25:1379~1394.
[3] R.Sun, L. Peng. A Gain Enhanced Two-Stage Fully Differential CMOS Opamp with High Unity-Gain Bandwidth. IEEE International Symposium on Circuits and System.2002,2:428~431.
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[5] A. E. Stevens, G. A. Miller. A High-Swing Integrator for Switched-Capacitor Circuits. IEEE J. Solid-State Circuits. 1994,29(9):1379~1394.
[6] U. Chilakapati, T. Fiez. Settling Time Design Consideration for SC Integrators. IEEE Int. Symposium on Circuits and Systems. 1998:492~295.
[7] S. Kannan. Error Compensation in Pipeline A/D Converters. B.S. University of Maine Doctoral Thesis. 2000:35~55.
[8] H. S. Chen, B. S. Song, K. Bacrania. A 14-b 20-MSamples/s CMOS Pipelined ADC. IEEE J. Solid-State Circuits. 2001,36(6):997~1001.
[9] S. H. Lewis. Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converters for Video-Rate Applications. IEEE Transactions on Circuits and System-II.1992,39(8):516~523.
[10]Y. Chiu, P. Gray, B. Nikolic. A 14-b 12-MS/s CMOS Pipeline ADC with over 100-dB SFDR. IEEE J. Solid-State Circuits. 2004,39(12):2139~2151.
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[13]赵晓晓,李福乐.无采样保持运放的12位流水线A/D转换器[J].电子产品世界, 2011，05:39-42.
[14]栗成智,瞿小峰,隋文泉.一种0.18μm数字工艺的12bit 100MS/s流水线型ADC设计[J].固体电子学研究与进展, 2010,04:592-595.
[15]洪志良.模拟集成电路分析与设计.科学出版社, 2008:12~31.
[16]林佳明.一种10位，200MSample/s模数转换器的设计[D].上海：上海交通大学，2008.
[17]C.W. Mangelsdorf,“A 400-MHz Input Flash Converter with Error Correction,”IEEE Journal of Solid-State Circuits, Vol. 25 pp. 184-191, Feb 1990.
[18]K. J. McCall, M. J. Demler, and M. W. Plante,“A 6-bit 125 MHz CMOS A/DConverter,”in Proc. CICC, pp. 16.8.1-16.8.4, May 1992.
[19]赵富菊. 16位具有前馈结构的三阶DeltaSigmaADC设计[D].哈尔滨：哈尔滨工业大学，2010.
[20]D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley &Sons, Inc., 1997.
[21]P. E. Allen, CMOS analog circuit design -2nd, Oxford University Press, Inc.,2002.
[22]B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995.
[23]A.M.Abo,andP.R.Gray,“A1.5-V 10-bit 14.3MS/s CMOS Pipeline Analog-to-Digital converter,”IEEE J. Solid-State Circuits, Vol. 34, No. 5, pp. 599-605, May 1999.
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[27]S. H. Lewis, P. R. Gray. A Pipelined 5-MSample/s 9-bit Analog-to-Digital Converter. IEEE J. Solid-State Circuits. 1987,22:954~961.
[28]Phillip E. Allen and Douglas R. Holberg,“CMOS Analog Circuit Design (Seconde Edition)”, Publishing House of Electronics Industry, 2002.
[29]张伟.12位40MSPS流水线ADC关键单元的设计[D].哈尔滨：哈尔滨工业大学，2010.
[30]B.Murmann and B.Boser,“A 12-b 75MS/s pipelined ADC using open-loop residueamplifier,”ISSCC Dig. Tech. Papers, pp. 330-331Feb. 2003.
[31]W. C. Song, H. W. Choi, S. U. Kwak, and B. S. Song,“A 10-b 20-Msample/s Low-Power CMOS ADC,”IEEE J. Solid-State Circuits, Vol.30, No.5, pp.514-521, May 1995.
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