高速VML收发器的研究与设计
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摘要
VML(电压模式逻辑)是一种高速差分接口技术,它具有高速、低噪声、低功耗、低成本等优点,在千兆位串行器解串器(Serdes)芯片中获得了广泛的应用。
本文首先详细介绍了几种常用的高速差分接口技术LVDS、CML、LVPECL,然后将VML技术与它们进行比较,最终确定了以VML技术设计一款用于Serdes的收发器电路。电路采用TSMC 0.13um CMOS 1P7M工艺实现,可传输速率最高达2.7Gbps的串行数据。
发送器VML主体驱动电路采用自偏置差分放大器及负反馈技术实现。由于信号在信道中传输时不可避免会有高频衰减,对输出差分信号进行了强度可调的预加重。针对Serdes芯片内核电平与I/O接口电平不同,设计了电平转换电路,仿真结果表明,工作频率为1.5GHz时输出信号占空比为50.7%。
接收器VML高速采样接收电路选用了共模和差模输入范围比较大的基于敏感放大器的触发器实现,仿真结果表明,其传输延时Tcq只有147pS。为了保持信道阻抗的一致性,加入了片内阻抗匹配电路。最后,针对收发器系统中可能会出现各种错误状态,在接收器加入了信号丢失检测电路。
论文最后给出了最终实现的收发器版图,并基于整个Serdes芯片使用安捷伦Infiniium 91304A示波器对收发器进行了测试,结果表明,本芯片在传输速率为1.5Gbps时收发器基本功能正确。
VML(Voltage Mode Logic)high speed differential interface technology has several advantages, such as high speed, low noise, low power and low cost etc. So it is widely used in Gigabit Serdes.
Based on the solid understanding of the difference of the common high-speed differential interface technology LVDS, CML, LVPECL, VML, a 2.7Gbps Transceiver has been designed and implemented in TSMC 0.13um 1P7M CMOS technology,which is used in Serdes.
The VML driver of the transmitter has adopted a self-biased differential amplifier and negative feedback technique. Because of the inevitable high-frequency components attenuation of signal transmitting in the channel, a pre-emphasis circuit has been designed. A level-shifting circuit has been designed to meet the different voltage level between the core of chip and I/O interface. Simulation results show that the duty cycle of the output signal is 50.7% when the operating frequency is 1.5GHz.
The VML high speed sampling circuit of the receiver has been implemented using a SAFF (Sense-Amplifier-based Flip-Flop), which has a large common mode and differential mode input range. Simulation results show that the delay between output data and clock is 147pS. In order to maintain a consistent channel resistance, a on-chip impedance matching circuitry has been designed. Finally, a loss of signal detection circuit has been designed to meet various errors state in the transceiver system
At last, the layout of the transceiver has been realized in Virtuoso of cadence and the transceiver has been tested with Agilent Infiniium 91304A oscilloscope based on Serdes. Test results show that the transceiver can function well when the serial interface speed is 1.5Gbps.
本文首先详细介绍了几种常用的高速差分接口技术LVDS、CML、LVPECL,然后将VML技术与它们进行比较,最终确定了以VML技术设计一款用于Serdes的收发器电路。电路采用TSMC 0.13um CMOS 1P7M工艺实现,可传输速率最高达2.7Gbps的串行数据。
发送器VML主体驱动电路采用自偏置差分放大器及负反馈技术实现。由于信号在信道中传输时不可避免会有高频衰减,对输出差分信号进行了强度可调的预加重。针对Serdes芯片内核电平与I/O接口电平不同,设计了电平转换电路,仿真结果表明,工作频率为1.5GHz时输出信号占空比为50.7%。
接收器VML高速采样接收电路选用了共模和差模输入范围比较大的基于敏感放大器的触发器实现,仿真结果表明,其传输延时Tcq只有147pS。为了保持信道阻抗的一致性,加入了片内阻抗匹配电路。最后,针对收发器系统中可能会出现各种错误状态,在接收器加入了信号丢失检测电路。
论文最后给出了最终实现的收发器版图,并基于整个Serdes芯片使用安捷伦Infiniium 91304A示波器对收发器进行了测试,结果表明,本芯片在传输速率为1.5Gbps时收发器基本功能正确。
VML(Voltage Mode Logic)high speed differential interface technology has several advantages, such as high speed, low noise, low power and low cost etc. So it is widely used in Gigabit Serdes.
Based on the solid understanding of the difference of the common high-speed differential interface technology LVDS, CML, LVPECL, VML, a 2.7Gbps Transceiver has been designed and implemented in TSMC 0.13um 1P7M CMOS technology,which is used in Serdes.
The VML driver of the transmitter has adopted a self-biased differential amplifier and negative feedback technique. Because of the inevitable high-frequency components attenuation of signal transmitting in the channel, a pre-emphasis circuit has been designed. A level-shifting circuit has been designed to meet the different voltage level between the core of chip and I/O interface. Simulation results show that the duty cycle of the output signal is 50.7% when the operating frequency is 1.5GHz.
The VML high speed sampling circuit of the receiver has been implemented using a SAFF (Sense-Amplifier-based Flip-Flop), which has a large common mode and differential mode input range. Simulation results show that the delay between output data and clock is 147pS. In order to maintain a consistent channel resistance, a on-chip impedance matching circuitry has been designed. Finally, a loss of signal detection circuit has been designed to meet various errors state in the transceiver system
At last, the layout of the transceiver has been realized in Virtuoso of cadence and the transceiver has been tested with Agilent Infiniium 91304A oscilloscope based on Serdes. Test results show that the transceiver can function well when the serial interface speed is 1.5Gbps.
引文
[1] Future of High-Speed Transceievers.ISSCC/2008/FORUM/F5
[2]Gary Roosevelt, David Bueno, Jamal Haque, etal. Rad-Hard High Speed Serial Communication using Honeywell Serdes Macros. IEEE Aerospace conference, March 2009
[3]轻松实现高速串行I/O,连接功能解决方案,1.0版,2005
[4]李优杏,周先敏,吕军红.基于FPGA的SERDES接口设计与实现.中国通信学会第五届学术年会论文集.北京:电子工业出版社,2008,11-14
[5]黄林.CMOS高速串行数据接收器的研究和设计:[博士学位论文].上海:复旦大学,2005
[6] Introduction to LVDS, PECL, and CML, Application Report. HFAN-1.0, 2008-04
[7] Interacing Between LVPECL, VML, CML and LVDS Levels, Application Report. SLLA120, 2002-12
[8] Behzad Razavi.模拟CMOS集成电路设计,陈贵灿等译.西安:西安交通大学出版社, 2003: 292-301
[9] Phillip E.Allen. CMOS模拟集成电路设计,冯军等译.北京:电子工业出版社, 2007: 286-357
[10] V Stojanovic, et al. Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver.IEEE International Conference on Communications, vol.3, 2002
[11] Chih-Hsien Lin , Chung-Hong Wang and Shyh-Jye Jou, etal. 5Gbps Serial Link Transmitter with Pre-emphasis.
[12]LVDS owner’s Manual,4th edition,2008
[13] Manabu Ishibe, Shoji Otaka, Junichi Takeda, etal. A 6.4-Gbs CMOS Serdes core with feed-forward and decision-feedback equalization. IEEE journal of SOLID-STATE CIRCUITS,VOL.40,NO.12,DECEMBER 2005
[14] V Stojanovic, etal. A 1.5V 20/30 Gb/s CMOS backplane driver with digital pre-emphasis. IEEE Custom Integrated Circuits Conference , Oct. 2004
[15] William L. Abbott .Disk drive using PRML class IV sampling data detection with digital adaptive equalization. United States Patent, 5341249, Aug.23, 1994
[16] Gregory P.Hartinan,Keiiiieth W.Martin,Angus McLaren,et al.Continuous-time adaptive-analog coaxial cable equalizer in 0.5μm CMOS, IEEE International Symposium on Circuits and Systems,Vol.2, Jul 1999
[17] Jong-Sang Choi, Moon-Sang Hwang and Deog-Kyoon Jeong, etal. A CMOS 3.5 Gbpscontinuous-time adaptive cable equalizer with joint adaptation method of low-frequency gain and High-Frequency Boosting. VLSI Circuits, June 2003
[18]谢詹奇.高速LVDS收发器的研究与设计:[硕士学位论文].上海:上海交通大学,2008
[19] Miao Li, Tad Kwasniewski, Shoujun Wang, Yuming Tao,etal. FIR filter optimization as preemphasis of high-speed backplane data transmission. Electronics Letters ,Vo.40,NO.14, July 2004
[20] RaminFarjad-Rad,et al. A 0.4-μm CMOS 10-Gbs 4-PAM pre-emphasis serial link transmitter. IEEE journal of SOLID-STATECIRCUITS,VOL.34,NO.5,MAY1999
[21]刘中唯,张涛,刘政林等.具有预加重功能的LVDS驱动电路.微电子学与计算机,2007,24(1):133-139
[22] John S Dame.Voltage level shifting circuit,United States Patent, 3801831, Apr. 2,1974
[23] Raymond L Gioradno.Level shift circuit including source follower output,United States Patent, 4695744, Sep.22, 1987
[24] Manabu Ishibe, Shoji Otaka, Junichi Takeda, et al. High-speed CMOS U0 Buffer Circuits. IEEk JOURNAL OF SOLID-STATE CIRCUITS, VOL.27, NO.4, APRIL 1992
[25] John P.Uyemyra超大规模集成电路设计与导论,周润德译.北京:电子工业出版社, 2003: 226-229
[26] William C.Madden.High input impedance strobed CMOS differential sense amplifier. United States Patent, 4910713, May. 20, 1990
[27] BorivojeNikolic,etal. Improved Sense-Amplifier-Based Flip-Flop Designand Measurements. IEEE journal of SOLID-STATECIRCUITS,VOL.35,NO.6,JUNE2000
[28] Active Fail-Safe in TI’s LVDS Receivers, Application Report. SLLA082B, October 2001
[29] Failsafe Biasing of LVDS Interfaces. Application Note. 1194, December2001
[30] Alan Hastings.模拟电路版图的艺术,张为等译.北京:电子工业出版社出版社, 2007: 460-520
[2]Gary Roosevelt, David Bueno, Jamal Haque, etal. Rad-Hard High Speed Serial Communication using Honeywell Serdes Macros. IEEE Aerospace conference, March 2009
[3]轻松实现高速串行I/O,连接功能解决方案,1.0版,2005
[4]李优杏,周先敏,吕军红.基于FPGA的SERDES接口设计与实现.中国通信学会第五届学术年会论文集.北京:电子工业出版社,2008,11-14
[5]黄林.CMOS高速串行数据接收器的研究和设计:[博士学位论文].上海:复旦大学,2005
[6] Introduction to LVDS, PECL, and CML, Application Report. HFAN-1.0, 2008-04
[7] Interacing Between LVPECL, VML, CML and LVDS Levels, Application Report. SLLA120, 2002-12
[8] Behzad Razavi.模拟CMOS集成电路设计,陈贵灿等译.西安:西安交通大学出版社, 2003: 292-301
[9] Phillip E.Allen. CMOS模拟集成电路设计,冯军等译.北京:电子工业出版社, 2007: 286-357
[10] V Stojanovic, et al. Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver.IEEE International Conference on Communications, vol.3, 2002
[11] Chih-Hsien Lin , Chung-Hong Wang and Shyh-Jye Jou, etal. 5Gbps Serial Link Transmitter with Pre-emphasis.
[12]LVDS owner’s Manual,4th edition,2008
[13] Manabu Ishibe, Shoji Otaka, Junichi Takeda, etal. A 6.4-Gbs CMOS Serdes core with feed-forward and decision-feedback equalization. IEEE journal of SOLID-STATE CIRCUITS,VOL.40,NO.12,DECEMBER 2005
[14] V Stojanovic, etal. A 1.5V 20/30 Gb/s CMOS backplane driver with digital pre-emphasis. IEEE Custom Integrated Circuits Conference , Oct. 2004
[15] William L. Abbott .Disk drive using PRML class IV sampling data detection with digital adaptive equalization. United States Patent, 5341249, Aug.23, 1994
[16] Gregory P.Hartinan,Keiiiieth W.Martin,Angus McLaren,et al.Continuous-time adaptive-analog coaxial cable equalizer in 0.5μm CMOS, IEEE International Symposium on Circuits and Systems,Vol.2, Jul 1999
[17] Jong-Sang Choi, Moon-Sang Hwang and Deog-Kyoon Jeong, etal. A CMOS 3.5 Gbpscontinuous-time adaptive cable equalizer with joint adaptation method of low-frequency gain and High-Frequency Boosting. VLSI Circuits, June 2003
[18]谢詹奇.高速LVDS收发器的研究与设计:[硕士学位论文].上海:上海交通大学,2008
[19] Miao Li, Tad Kwasniewski, Shoujun Wang, Yuming Tao,etal. FIR filter optimization as preemphasis of high-speed backplane data transmission. Electronics Letters ,Vo.40,NO.14, July 2004
[20] RaminFarjad-Rad,et al. A 0.4-μm CMOS 10-Gbs 4-PAM pre-emphasis serial link transmitter. IEEE journal of SOLID-STATECIRCUITS,VOL.34,NO.5,MAY1999
[21]刘中唯,张涛,刘政林等.具有预加重功能的LVDS驱动电路.微电子学与计算机,2007,24(1):133-139
[22] John S Dame.Voltage level shifting circuit,United States Patent, 3801831, Apr. 2,1974
[23] Raymond L Gioradno.Level shift circuit including source follower output,United States Patent, 4695744, Sep.22, 1987
[24] Manabu Ishibe, Shoji Otaka, Junichi Takeda, et al. High-speed CMOS U0 Buffer Circuits. IEEk JOURNAL OF SOLID-STATE CIRCUITS, VOL.27, NO.4, APRIL 1992
[25] John P.Uyemyra超大规模集成电路设计与导论,周润德译.北京:电子工业出版社, 2003: 226-229
[26] William C.Madden.High input impedance strobed CMOS differential sense amplifier. United States Patent, 4910713, May. 20, 1990
[27] BorivojeNikolic,etal. Improved Sense-Amplifier-Based Flip-Flop Designand Measurements. IEEE journal of SOLID-STATECIRCUITS,VOL.35,NO.6,JUNE2000
[28] Active Fail-Safe in TI’s LVDS Receivers, Application Report. SLLA082B, October 2001
[29] Failsafe Biasing of LVDS Interfaces. Application Note. 1194, December2001
[30] Alan Hastings.模拟电路版图的艺术,张为等译.北京:电子工业出版社出版社, 2007: 460-520