介电氧化物薄膜在GaN半导体上的外延生长与性能研究
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摘要
近年来,电子信息系统为了缩小体积、增强功能,正快速向微型化以及单片集成化方向发展,对电子薄膜与器件提出了尺寸小型化和功能集成化的要求。将以极化为特征、具有丰富功能特性的介电氧化物材料通过外延薄膜的方式,与GaN半导体生长在一起形成介电氧化物/GaN集成薄膜,为高性能电子器件的研制提供了新的思路,将推动电子系统单片集成化的进一步发展。然而,在介电氧化物/GaN集成薄膜的研制中,两类材料物理、化学性质的巨大差异导致了严重的相容性生长问题。由于理论研究和实验条件的限制,与之相关的很多物理现象和机理尚未深入研究,尤其是介电氧化物/GaN异质外延机理以及薄膜微结构控制等方面研究不足,阻碍了介电氧化物/GaN集成薄膜与器件的发展。
本论文采用激光分子束外延技术(LMBE),以典型的SrTiO_3(STO)介电氧化物薄膜为对象,研究氧化物/GaN异质外延的生长机制和界面控制方法。通过特殊设计的纳米厚度缓冲层材料,对界面加以控制,优化STO薄膜的外延质量。在此基础上,研究了GaN基半导体上生长的STO、BaTiO_3等多种介电氧化物薄膜的性能,为GaN基介电氧化物集成薄膜的实用化提供了一定的基础。
1.采用反射式高能电子衍射(RHEED)等方法,系统研究了STO在GaN上的生长行为及界面微结构特性。发现在界面化学能的作用下,STO薄膜在GaN衬底上偏离晶格失配度小的方向30°,按STO(111)[110]//GaN(0002)[1120]的外延关系生长,晶格失配度为-13.3%。大的晶格失配度使得STO薄膜以岛状模式生长,产生大量缺陷,取向一致性较差。STO(111)面与GaN(0002)对称性的差异导致STO薄膜面内具有特殊的双畴结构。研究还发现STO中SrO与Ga面GaN之间的不稳定性导致STO/GaN界面发生扩散反应,产生界面层。因此,介电氧化物/GaN界面存在大晶格失配和界面扩散,影响STO薄膜的外延质量,难以实现高质量集成薄膜的可控生长。
2.研究了TiO_2模板层对STO薄膜外延质量和界面微结构的影响。在GaN上制备了以层状模式外延生长的TiO_2模板层。TiO_2薄膜表面平整(表面均方根粗糙度RMS<0.5nm),具有明显的台阶状结构;与GaN形成清晰、无明显扩散的界面。研究发现,利用TiO_2模板层降低了STO薄膜外延温度,提高了薄膜面内、面外取向的一致性。结果表明,TiO_2模板层可以有效诱导STO(111)薄膜的取向外延生长。通过近重位点阵理论和界面原子构型分析发现,TiO_2与STO的结构类似性以及晶格失配的降低(从直接生长时的-13.3%降低到1.3%)是TiO_2模板层对STO薄膜取向诱导作用的主要原因。通过控制TiO_2模板层厚度可以进一步提高STO薄膜外延质量。当TiO_2厚度为2nm时,STO薄膜以层状模式在TiO_2模板层上外延生长,其面外、面内半高宽分别为0.569°和1.65°。HRTEM和XPS分析表明,STO/TiO_2/GaN集成薄膜具有清晰的界面,界面扩散反应得到了显著抑制。这些结果说明,TiO_2纳米模板层能有效地优化氧化物/GaN的界面特性,提高了STO薄膜的外延质量。
3.开展了STO/TiO_2缓冲层对GaN基集成铁电薄膜取向诱导和性能影响的研究。直接在GaN上生长的铁电薄膜为多晶结构;而STO/TiO_2缓冲层能够诱导BaTiO_3、Hf掺杂Bi4Ti3O12(BTH)以及BiFeO_3等不同晶体结构的铁电薄膜外延生长。与多晶的铁电薄膜相比,外延的铁电薄膜具有更好的电学性能,如更大的剩余极化、更小的漏电流密度和更好的抗疲劳特性等。STO/TiO_2缓冲层显著提升了GaN基集成铁电薄膜的性能。
4.研究了MgO薄膜的低温外延生长特性及其对界面扩散的阻挡作用,初步探索了MgO势垒层在AlGaN/GaN高电子迁移率晶体管(HEMT)器件中的作用。发现MgO的强离子性是其能在室温条件下外延生长的主要原因。界面特性分析表明,室温生长的MgO能够阻挡STO与GaN界面的扩散反应。MgO势垒层提高了STO与GaN界面的势垒高度,使得STO/TiO_2/MgO叠层结构漏电流小于STO/TiO_2结构,为STO等介电氧化物薄膜在GaN基场效应器件中实际应用提供了一种可能的方法。
Recently, electronic information systems are quickly developed to further miniaturization and monolithic integration in order to realize smaller volume and enhanced multifunction. In order to satisfy the demand of system develop trend, the electronic films and devices must be miniaturized and integrated. The integration of multifunctional oxide dielectrics possessing spontaneous polarization with GaN semiconductors put forward a new direction of developing electronic devices with higher performances. However, the dielectric oxide and GaN semiconductors are quite different from each other. It will cause many problems when the two kind materials are integrated together. However, little is known about the physical phenomena and mechanism in this heterostructure. Especially, the lack of related research about epitaxial growth and interface control of dielectric oxide film on GaN has hampered the development of the integrated films and devices.
In this dissertation, SrTiO_3 (STO) dielectric oxide films were fabricated by laser molecular beam epitaxy (LMBE) to investigate the epitaxial mechanism and interface control method. Bufferlayers at nanometer scale were designed and fabricated to optimize the crystalline quality of STO epitaxial film. Based on these results, the electric properties of STO and other dielectric films were studied.
1. The growth behaviors and interface microstructures were systematically studied. It was found that STO can be epitaxially grown on GaN at 700℃and the epitaxial relationship was STO(111)[110]//GaN(0002)[1120]. The lattice mismatch under this alignment was calculated to be -13.3%, which leads to 3D island growth mode and poor crystalline quality. The analyses of interface energy show that the bonding energy can compensates the strain energy and make this alignment more stable. From the RHEED images, it was found that STO films show a twin variant related by a 180°in-plane rotation. This in-plane structure was caused by the different symmetry index of STO (111) and GaN (0002). On the other hand, an interface layer was observed at STO/GaN interface. The formation of interface layer was due to the instability of STO with Ga-terminated GaN. As indicated by these results, Lattice mismatch and interface diffusions are the two major obstacles hindered the integration growth of dielectric oxide films on GaN.
2. The effect of TiO_2 template layer on STO epitaxial growth and microstructure was studied. TiO_2 was epitaxially grown on GaN(0002) surface in layer by layer mode. The TiO_2 surface was smooth and uniform with a root-mean-square roughness (RMS) less than 0.5nm. A sharp interface was observed between TiO_2/GaN. It was found that the epitaxial growth temperature was decreased and the orientation uniformity of STO was improved on TiO_2 coated GaN. These results indicated that the epitaxial growth of STO film was enhanced by TiO_2 template layer because of the reduced lattice mismatch and similar Ti-O6 octahedron structure between TiO_2 and STO. By inserting a strained layer of TiO_2 below its critical thickness, the crystalline quality was further improved. The optimal thickness of TiO_2 was about 2nm. The interfaces of STO/TiO_2/GaN integrated films were sharp as confirmed by HRTEM and XPS. These results demonstrated that the interface of oxide/GaN was optimized and the crystalline quality was improved by the design of TiO_2 template layer.
3. The impacts of STO/TiO_2 bufferlayer on the epitaxial growth and properties of GaN-based ferroelectric films were carried out. It was found that these ferroelectric films deposited on GaN directly show polycrystalline structure. In contrast, three kind ferroelectric films with different crystal structure, BaTiO_3,Hf-doped Bi4Ti3O12 and BiFeO_3, were epitaxially grown on STO/TiO_2 buffered GaN. Simultaneously, these epitaxial films show much better electric properties than that of polycrystalline ones, such as enlarged polarization, reduced leakage and enhanced fatigue endurance.
4. The low temperature fabrication of MgO and its effect on STO/GaN integrated films were studied. It was found that the strong ionic characteristics of MgO makes its epitaxial temperature can be as low as room temperature. This special feature reduced the interface diffusion between oxide and GaN remarkably. On the other hand, STO/TiO_2/MgO gate stack show reduced leakage than that of STO/TiO_2. It is concluded that the presence of MgO barrier layer increases band offsets and reduces the leakage current density effectively.
本论文采用激光分子束外延技术(LMBE),以典型的SrTiO_3(STO)介电氧化物薄膜为对象,研究氧化物/GaN异质外延的生长机制和界面控制方法。通过特殊设计的纳米厚度缓冲层材料,对界面加以控制,优化STO薄膜的外延质量。在此基础上,研究了GaN基半导体上生长的STO、BaTiO_3等多种介电氧化物薄膜的性能,为GaN基介电氧化物集成薄膜的实用化提供了一定的基础。
1.采用反射式高能电子衍射(RHEED)等方法,系统研究了STO在GaN上的生长行为及界面微结构特性。发现在界面化学能的作用下,STO薄膜在GaN衬底上偏离晶格失配度小的方向30°,按STO(111)[110]//GaN(0002)[1120]的外延关系生长,晶格失配度为-13.3%。大的晶格失配度使得STO薄膜以岛状模式生长,产生大量缺陷,取向一致性较差。STO(111)面与GaN(0002)对称性的差异导致STO薄膜面内具有特殊的双畴结构。研究还发现STO中SrO与Ga面GaN之间的不稳定性导致STO/GaN界面发生扩散反应,产生界面层。因此,介电氧化物/GaN界面存在大晶格失配和界面扩散,影响STO薄膜的外延质量,难以实现高质量集成薄膜的可控生长。
2.研究了TiO_2模板层对STO薄膜外延质量和界面微结构的影响。在GaN上制备了以层状模式外延生长的TiO_2模板层。TiO_2薄膜表面平整(表面均方根粗糙度RMS<0.5nm),具有明显的台阶状结构;与GaN形成清晰、无明显扩散的界面。研究发现,利用TiO_2模板层降低了STO薄膜外延温度,提高了薄膜面内、面外取向的一致性。结果表明,TiO_2模板层可以有效诱导STO(111)薄膜的取向外延生长。通过近重位点阵理论和界面原子构型分析发现,TiO_2与STO的结构类似性以及晶格失配的降低(从直接生长时的-13.3%降低到1.3%)是TiO_2模板层对STO薄膜取向诱导作用的主要原因。通过控制TiO_2模板层厚度可以进一步提高STO薄膜外延质量。当TiO_2厚度为2nm时,STO薄膜以层状模式在TiO_2模板层上外延生长,其面外、面内半高宽分别为0.569°和1.65°。HRTEM和XPS分析表明,STO/TiO_2/GaN集成薄膜具有清晰的界面,界面扩散反应得到了显著抑制。这些结果说明,TiO_2纳米模板层能有效地优化氧化物/GaN的界面特性,提高了STO薄膜的外延质量。
3.开展了STO/TiO_2缓冲层对GaN基集成铁电薄膜取向诱导和性能影响的研究。直接在GaN上生长的铁电薄膜为多晶结构;而STO/TiO_2缓冲层能够诱导BaTiO_3、Hf掺杂Bi4Ti3O12(BTH)以及BiFeO_3等不同晶体结构的铁电薄膜外延生长。与多晶的铁电薄膜相比,外延的铁电薄膜具有更好的电学性能,如更大的剩余极化、更小的漏电流密度和更好的抗疲劳特性等。STO/TiO_2缓冲层显著提升了GaN基集成铁电薄膜的性能。
4.研究了MgO薄膜的低温外延生长特性及其对界面扩散的阻挡作用,初步探索了MgO势垒层在AlGaN/GaN高电子迁移率晶体管(HEMT)器件中的作用。发现MgO的强离子性是其能在室温条件下外延生长的主要原因。界面特性分析表明,室温生长的MgO能够阻挡STO与GaN界面的扩散反应。MgO势垒层提高了STO与GaN界面的势垒高度,使得STO/TiO_2/MgO叠层结构漏电流小于STO/TiO_2结构,为STO等介电氧化物薄膜在GaN基场效应器件中实际应用提供了一种可能的方法。
Recently, electronic information systems are quickly developed to further miniaturization and monolithic integration in order to realize smaller volume and enhanced multifunction. In order to satisfy the demand of system develop trend, the electronic films and devices must be miniaturized and integrated. The integration of multifunctional oxide dielectrics possessing spontaneous polarization with GaN semiconductors put forward a new direction of developing electronic devices with higher performances. However, the dielectric oxide and GaN semiconductors are quite different from each other. It will cause many problems when the two kind materials are integrated together. However, little is known about the physical phenomena and mechanism in this heterostructure. Especially, the lack of related research about epitaxial growth and interface control of dielectric oxide film on GaN has hampered the development of the integrated films and devices.
In this dissertation, SrTiO_3 (STO) dielectric oxide films were fabricated by laser molecular beam epitaxy (LMBE) to investigate the epitaxial mechanism and interface control method. Bufferlayers at nanometer scale were designed and fabricated to optimize the crystalline quality of STO epitaxial film. Based on these results, the electric properties of STO and other dielectric films were studied.
1. The growth behaviors and interface microstructures were systematically studied. It was found that STO can be epitaxially grown on GaN at 700℃and the epitaxial relationship was STO(111)[110]//GaN(0002)[1120]. The lattice mismatch under this alignment was calculated to be -13.3%, which leads to 3D island growth mode and poor crystalline quality. The analyses of interface energy show that the bonding energy can compensates the strain energy and make this alignment more stable. From the RHEED images, it was found that STO films show a twin variant related by a 180°in-plane rotation. This in-plane structure was caused by the different symmetry index of STO (111) and GaN (0002). On the other hand, an interface layer was observed at STO/GaN interface. The formation of interface layer was due to the instability of STO with Ga-terminated GaN. As indicated by these results, Lattice mismatch and interface diffusions are the two major obstacles hindered the integration growth of dielectric oxide films on GaN.
2. The effect of TiO_2 template layer on STO epitaxial growth and microstructure was studied. TiO_2 was epitaxially grown on GaN(0002) surface in layer by layer mode. The TiO_2 surface was smooth and uniform with a root-mean-square roughness (RMS) less than 0.5nm. A sharp interface was observed between TiO_2/GaN. It was found that the epitaxial growth temperature was decreased and the orientation uniformity of STO was improved on TiO_2 coated GaN. These results indicated that the epitaxial growth of STO film was enhanced by TiO_2 template layer because of the reduced lattice mismatch and similar Ti-O6 octahedron structure between TiO_2 and STO. By inserting a strained layer of TiO_2 below its critical thickness, the crystalline quality was further improved. The optimal thickness of TiO_2 was about 2nm. The interfaces of STO/TiO_2/GaN integrated films were sharp as confirmed by HRTEM and XPS. These results demonstrated that the interface of oxide/GaN was optimized and the crystalline quality was improved by the design of TiO_2 template layer.
3. The impacts of STO/TiO_2 bufferlayer on the epitaxial growth and properties of GaN-based ferroelectric films were carried out. It was found that these ferroelectric films deposited on GaN directly show polycrystalline structure. In contrast, three kind ferroelectric films with different crystal structure, BaTiO_3,Hf-doped Bi4Ti3O12 and BiFeO_3, were epitaxially grown on STO/TiO_2 buffered GaN. Simultaneously, these epitaxial films show much better electric properties than that of polycrystalline ones, such as enlarged polarization, reduced leakage and enhanced fatigue endurance.
4. The low temperature fabrication of MgO and its effect on STO/GaN integrated films were studied. It was found that the strong ionic characteristics of MgO makes its epitaxial temperature can be as low as room temperature. This special feature reduced the interface diffusion between oxide and GaN remarkably. On the other hand, STO/TiO_2/MgO gate stack show reduced leakage than that of STO/TiO_2. It is concluded that the presence of MgO barrier layer increases band offsets and reduces the leakage current density effectively.
引文
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