适合于硬件进化的FPGA平台设计实现
摘要
可进化硬件(EHW)是指硬件能够通过与环境的交互作用自适应地和动态地改变和调整自身的结构和行为，其研究思路是在可重配置的硬件平台上模拟自然进化的过程。可进化硬件硬件系统在电路设计、自动控制、容错系统、模式识别与人工智能、机器人、太空和深海探索等领域将有着极其广泛的应用前景。
本文总结了可进化硬件研究领域的研究现状，分析了目前研究中使用的可进化硬件平台的结构特点和优缺点，着重分析了基于FPGA硬件进化各种实现结构。
首先，本文根据硬件进化的原理，研究了硬件进化在电路设计领域的应用。本文通过2个硬件进化实例设计并实现，分别在基于FPGA的门级和函数级硬件进化方面做了一些探索。在门级进化方面，提出了一种基于LUT的VRC模型，通过对3到5输入LUT的LUT-VRC模型进行了系统的比较分析，得到了一种最佳的基于3输入LUT的VRC结构模型；函数级进化研究方面，本文提出了一种新型针对图像滤波器应用硬件进化单元结构，该结构进化出的滤波器能够很好的滤除图像中的高斯噪声和椒盐噪声。
其次，根据针对现有FPGA硬件进化平台的缺点，采用0．13um工艺设计并实现了一种适合进化的CPU+FPGA可重构平台芯片。FPGA方面，逻辑单元设计中采用了4 S LICE组合成一个CLB结构，加强了SLICE之间的资源复用和资源共享，SLICE内部实现了SOP功能扩展，提高了SLICE对多输入逻辑的支持。互联资源方面，采用了新一代的主动互联架构技术，实现各种IP单元通过统一接口融入互联网络。互联资源采用了全驱动(Full Buffer)方式构建开关矩阵，增加了时序性能和时序可预测性。CPU部分采用了IBM公司32位开源处理器核PowerPC405软核，FPGA和CPU之间设计异步FIFO和共享双口RAM接口，通过中断驱动方式进行数据通信。
该芯片从3个方面针对硬件进化设计，加快硬件进化速度。第一是针对硬件进化过程中每次只有少量位流改变的情况，减少重配置位流粒度，FPGA的位流配置结构采用了行列双译码方式，可以以1bit为单位对FPGA进行配置读写，大大提高了部分重配置速度。第二专门设计FPGA配置控制接口，可以实现通过CPU对FPGA进行快速部分配置，实现单芯片(on chip)硬件进化。第三，针对遗传算法需要大量随机数特点，专门设计随机数模板发生器和交叉加速器，以实现遗传算法硬件加速，比软件实现提高了4倍以上。
该芯片采用SMIC 0．13uM工艺进行流片，FPGA模块采用全定制设计，CPU和配置控制器部分采用标准SYNOPSYS流程实现，最后手工拼接，芯片面积4．5×6．2mm。
Evolvable Hardware (EHW) refers to hardware that can change its architectureand behavior dynamically and autonomously by interacting with its environment.Theprime motivation of EHW is to simulate the nature of evolution on a reconfigurablehardware platform.EHW have a wide range application prospects at circuit design,autornatic control,fault-tolerant systems,artificial intelligence,robotics,and deepspace exploration.
First,the purpose of this dissertation is to study circuit design methodology baseon EHW,on the two aspects:gate-level and function-level FPGA-based hardwareevolution.In the gate-level field,A LUT-based VRC implementation of EHW hasbeen proposed with the aim to find a general purpose VRC model for evolvingrandom logic function targets.Experiment results indicate that 3-LUT based VRCachieves the best results,and gets a significant improvement in resource utilization ofthe basic cell.In the function-level research,a new architecture of EHW cell has beenproposed for image filter,the filter evolved from this architecture can successfullyfilter out Gauss noise and Salt-and-pepper noise.
Second,aims the drawbacks of the existing FPGA-based EHW platform,anSOPC chip based on CPU+FPGA was designed and implemented on 0.13um logicprocess.The SOPC chip was designed to speed up the hardware evolution processfrom three aspects.First of all,because only a small mount of bitstream changes inthe every evolution iteration,a row-column dual-decode architecture is adapted tospeed up configuration.Compared to the traditional row based architecture,thismethod reduces the smallest bitsteam scale and significantly improves the speed ofpartial configuration.Next,a dedicated CPU configuration interface is designed,enable CPU to configure FPGA conveniently and realize on-chip evolution.At last,genetic algorithm needs much of random numbers,in this chip,a dedicated randomnumber generator and cross-accelerator is designed in order to achievehardware-accelerated genetic algorithm.
本文总结了可进化硬件研究领域的研究现状，分析了目前研究中使用的可进化硬件平台的结构特点和优缺点，着重分析了基于FPGA硬件进化各种实现结构。
首先，本文根据硬件进化的原理，研究了硬件进化在电路设计领域的应用。本文通过2个硬件进化实例设计并实现，分别在基于FPGA的门级和函数级硬件进化方面做了一些探索。在门级进化方面，提出了一种基于LUT的VRC模型，通过对3到5输入LUT的LUT-VRC模型进行了系统的比较分析，得到了一种最佳的基于3输入LUT的VRC结构模型；函数级进化研究方面，本文提出了一种新型针对图像滤波器应用硬件进化单元结构，该结构进化出的滤波器能够很好的滤除图像中的高斯噪声和椒盐噪声。
其次，根据针对现有FPGA硬件进化平台的缺点，采用0．13um工艺设计并实现了一种适合进化的CPU+FPGA可重构平台芯片。FPGA方面，逻辑单元设计中采用了4 S LICE组合成一个CLB结构，加强了SLICE之间的资源复用和资源共享，SLICE内部实现了SOP功能扩展，提高了SLICE对多输入逻辑的支持。互联资源方面，采用了新一代的主动互联架构技术，实现各种IP单元通过统一接口融入互联网络。互联资源采用了全驱动(Full Buffer)方式构建开关矩阵，增加了时序性能和时序可预测性。CPU部分采用了IBM公司32位开源处理器核PowerPC405软核，FPGA和CPU之间设计异步FIFO和共享双口RAM接口，通过中断驱动方式进行数据通信。
该芯片从3个方面针对硬件进化设计，加快硬件进化速度。第一是针对硬件进化过程中每次只有少量位流改变的情况，减少重配置位流粒度，FPGA的位流配置结构采用了行列双译码方式，可以以1bit为单位对FPGA进行配置读写，大大提高了部分重配置速度。第二专门设计FPGA配置控制接口，可以实现通过CPU对FPGA进行快速部分配置，实现单芯片(on chip)硬件进化。第三，针对遗传算法需要大量随机数特点，专门设计随机数模板发生器和交叉加速器，以实现遗传算法硬件加速，比软件实现提高了4倍以上。
该芯片采用SMIC 0．13uM工艺进行流片，FPGA模块采用全定制设计，CPU和配置控制器部分采用标准SYNOPSYS流程实现，最后手工拼接，芯片面积4．5×6．2mm。
Evolvable Hardware (EHW) refers to hardware that can change its architectureand behavior dynamically and autonomously by interacting with its environment.Theprime motivation of EHW is to simulate the nature of evolution on a reconfigurablehardware platform.EHW have a wide range application prospects at circuit design,autornatic control,fault-tolerant systems,artificial intelligence,robotics,and deepspace exploration.
First,the purpose of this dissertation is to study circuit design methodology baseon EHW,on the two aspects:gate-level and function-level FPGA-based hardwareevolution.In the gate-level field,A LUT-based VRC implementation of EHW hasbeen proposed with the aim to find a general purpose VRC model for evolvingrandom logic function targets.Experiment results indicate that 3-LUT based VRCachieves the best results,and gets a significant improvement in resource utilization ofthe basic cell.In the function-level research,a new architecture of EHW cell has beenproposed for image filter,the filter evolved from this architecture can successfullyfilter out Gauss noise and Salt-and-pepper noise.
Second,aims the drawbacks of the existing FPGA-based EHW platform,anSOPC chip based on CPU+FPGA was designed and implemented on 0.13um logicprocess.The SOPC chip was designed to speed up the hardware evolution processfrom three aspects.First of all,because only a small mount of bitstream changes inthe every evolution iteration,a row-column dual-decode architecture is adapted tospeed up configuration.Compared to the traditional row based architecture,thismethod reduces the smallest bitsteam scale and significantly improves the speed ofpartial configuration.Next,a dedicated CPU configuration interface is designed,enable CPU to configure FPGA conveniently and realize on-chip evolution.At last,genetic algorithm needs much of random numbers,in this chip,a dedicated randomnumber generator and cross-accelerator is designed in order to achievehardware-accelerated genetic algorithm.
引文
[1]Von Neumann J.“Theory of Self-reproduction Automata”.A.W.Burks(Ed.),Urbana,IL:Univ.of Illinois Press,1966
[2]王正志，薄涛，“进化计算”，长沙：国防科技大学出版社，2000
[3]Stoica A.“Evolvable hardware:from on-chip circuit synthesis to evolvable space systems”Proceedings."IEEE International Symposium on Multiple-Valued Logic,2000.(ISMVL 2000)
[4]Stoica A.,Zebulum R.,Keymeulen D..“Progress and challenges in building evolvable device”,Proceedings.“The Third NASA/DoD Workshop on,Evolvable Hardware”,2001
[5]A.Thompson,“Evolving Electronic Robot Controllers that Exploit Hardware Resources,”in Advances in Artificial Lrfe:Proc.3rd European Conference on Artificial life,1995,pp.640-656
[6]S.Thorsten and X.Yao,“Using Negative Correlation to Evolve Fault-Tolerant Circuits,”in the 5th International Conference on Evolvable Systems,Trondheim,Norway,2003,pp.35-46.
[7]Garis H D.“Evolvable Hardware Genetic Programming of a Darwin Machine in:Branko Soucek and the IRIS Group(Eds.)”,Dynamic,Genetic and Chaotic Programming.John Willey&Sons,Inc.,373-393,1992
[8]Hugo de Garis,“Exploring GenNet Behaviors:Using Genetic Programming to Explore Qualitatively New Behaviors in Recurrent Neural Networks”,Int.Joint Conference on Neural Networks”,Baltimore,USA,June 1992
[9]http://www.smi.stanford.edu/people/koza
[10]http://www.cogs.susx.ac.uldusers/adrianth
[11]http://www.etl.go.jp:8080/etl/kikou/ehw.html
[12]A.Thompson,“Explorations in Design Space:Unconventional Electronics Design Through Artificial Evolution”,IEEE Transation on Evolutionary Computation,1999,3(3),167-196
[13]T.Higuchi,M.Iwata,l.Kajitani,H.Yamada,B.Manderick,Y Hirao,M.Murakawa,S.Yoshizawa,T.Fumya,“Evolvable Hardware with Genetic Learning”,Proceedings of the IEEE International Symposium on Circuits and Systems,1996,Vol.4,29-32
[14]T.Higuchi,M.Iwata,I.Kajitani,H.Iba,T.Furuya,Mandeik,“Evolvable Hardware and its Applications to Pattern Recognition and Fault-tolerant System”,Towards Evolvable Hardware:The Evolutionary Engineering Approach(Lecture Notes in Computer Science),Springer-Verlag,1996,Vol.1062,118-135
[15]T.Higuchi,“Real-World Applications of Analog and Digital Evolvable Hardware”,IEEE Transaction on Evolutionary Computation,1999,3(3),220-235
[16]G Tufte et al.,“Evolving an Adaptive Digital Filter”,Proceedings of the Second NASA/DOD Workshop on Evolvable Hardware,CA:Palo Alto,U.S.A,2000,143-15
[17]J.R.Koza et al.,“Automated Synthesis of Analog Electrical Circuits by Means of Genetic Programming”,IEEE Transaction on Evolutionary Computation,1997,1(2),109-128
[18]A.Stoica et al.,“Evolution of Analog Circuits on Field Programmable Transistor Arrays”,Proceedings of the Second NASA/DOD Workshop on Evolvable Hardware,CA:Palo Alto,U.S.A,2000,99-108
[19]R Zebulum et al.,“A Reconfigurable Platform for the Automatic Synthesis of Analog Circuits”,Proceedings of the Second NASA/DOD Workshop on Evolvable Hardware,CA:Palo Alto,U.S.A,2000,91-98
[20]J.Torresen,“A Divide-and-Conquer Approach to Evolvalbe Hardware”,Proceedings of the Second International Conference on Evolvable Systems:From Biology to Hardware(ICES'98),1998,57-65
[21]T.Kalganova,“Bidirectional Incremental Evoiution in Extrinsic Evolvable Hardware”,Proceedings of the Second NASA/DOD Workshop on Evolvable Hardware,CA:Palo Alto,U.S.A,2000,65-74
[22]V Vassilev,J.Miller,“Scalability Problems of Digital Circuit Evolution:Evolvablility and Efficient Designs”,Proceedings of the Second NASA/DOD Workshop on Evolvable Hardware,CA:Palo Alto,U.S.A,2000,55-64
[23]陈毓屏等一个新的研究领域—演化硬件．航空计算技术，1998，28(1)：1-8
[24]康立山，何巍，陈毓屏．“用函数型可编程逻辑器件实现演化硬件．计算机学报，1999，22(7)：781-784
[25]曾三友，颜雪松，康立山．“演化硬件及其在深空探测应用可行性研究”．中国宇航
[26]赵曙光等．“基于函数级FPGA原型的演化硬件内部进化”，计算机学报，2002 25(5)，666-669
[27]赵曙光等，“基于进化的电子电路自动设计方法”，电路与系统学报，2002，7p72-78
[28]赵曙光等，“一种基于演化硬件的染色体编码新方法”，西安电子科技大学学报，2000，27(6)：778-780
[29]赵曙光等，“可进化硬件的基本原理与关键技术”，系统工程与电子技术，2002p70-73
[30]J.He,X.Wang,M.Zhang,and Q.Fang,“New Research on Scalability of Lossless Image Compression by GP Engine,”in 2005 NASA/DoD Conference on Evolvable Hardware,2005,pp.160-164.
[31]方潜生，王煦法，何劲松，“硬件进化的快速算法模型研究”，中国科学技术大学学报，vol．33(5)，pp．612-618，2003．
[32]林勇，罗文坚，王煦法，“硬件电路的选择性进化冗余”，中国科学技术大学学报，vol．36(5)，pp．523-529，2006．
[33]林勇，罗文坚，钱海，王煦法，“n×n阵列胚胎电子系统应用中的优化设计问题分析”，中国科学技术大学学报，vol．37(2)，pp．171-176，2007．
[34]Andrew J.Greensted,“RISA:A Hardware Platform for Evolutionary Design”,Proceedings of the 2007 IEEE Workshop on Evolvable and Adaptive Hardware
[35]Yann Thoma,Eduardo Sanchez,“A Reconfigurable Chip for Evolvable Hardware Genetic and Evolutionary Computation”-GECCO 2004
[36]X.Yao and T.Higuchi,“Promises and Challenges of Evolvable Hardware”,IEEE Transactions on Systems,Man,and Cybernetics,Part C,vol.29,pp.87-97,February 1998.
[37]M.lwata,I.Kajitani,H.Yamada,and T.Higuchi,“A pattern recognition system using evolvable hardware,”Parallel Problem Solving from Nature Ⅳ,Berlin,Germany,1996,pp.761-770
[38]Xilinx Corporation,“XC6200 Field Promable Gate Arrays Product Specification”,1997
[39]Xilinx Corporation,“Virtex-E Field Promable Gate Arrays Product Specification”,DS022,2002
[40]Xilinx Corporation,“Virtex-Ⅱ Platform FPGAs:Complete Data Sheet”DS031,2005
[41]Xilinx Corporation,“Virtex-Ⅱ Pro and Virtex-Ⅱ Pro Ⅹ Platform FPGAs:Complete Data Sheet”DS083,2005
[42]Hollingworth,G.Smith,S.Tyrrell,A“Safe Intrinsic Evolution of Virtex Devices”,Evolvable Hardware,2000.Proceedings
[43]Glette,K.Torresen,J.Yasunaga,M.Yamaguchi,Y.“On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition”,Adaptive Hardware and Systems,2006
[44]“An evolvable hardware system in Xilinx Virtex Ⅱ Pro FPGA”,International Journal of Innovative Computing and Applications,Volume 1,Issue 1(April 2007)
[45]Kyrre Glette and Jim Torresen,“A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-Ⅱ Pro Device”Evolvable Systems:From Biology to Hardware pp.66-75
[46]Lukas Sekanina,Tomas Martinek and Zbysek Gajda“Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules”,IEEE Congress on Evolutionary Computation,2006
[47]Higuichi T.“Evolvable Hardware at Function Level”.In Proc.1997 IEEE Int.Conf Evolutionary Computation,(ICES'97),1997:187-192
[48]Z.Vasicek and L.Sekanina.“An evolvable hardware system in Xilinx Virtex Ⅱ Pro FPGA”.Int.J.Innovative Computing and Applications,1(1):63-73,2007.
[49]Stomeo,E.Kalganova,T.Lambert,C.Lipnitsakya,N.Yatskevich,Y.“On evolution of relatively large combinational logic circuits Evolvable Hardware”,2005.Proceedings.2005 NASA/DoD Conference
[50]Keum-Sung Hwang,Sung-Bae Cho,“Evolving diverse hardware's using speculated genetic algorithm”,Proceedings of the 2002 Congress on Evolutionary Computation,Volume 1,Issue,12-17 May 2002 Page(s):437-442
[51]Sin Man Cheang;Kin Hong Lee;Kwong Sak Leung,“applying genetic parallel programming to synthesize combinational logic circuits”,Evolutionary Computation,IEEE Transactions on Volume 11,Issue 4,Aug.2007 Page(s):503-520
[52]Sekanina,L.Friedl,“On Routine Implementation of Virtual Evolvable Devices Using COMBO6,”In Proc.of the 2004 NASA/DoD Conference on Evolvable Hardware,Seattle,USA,IEEE Computer Society Press,2004,pp.63-70
[53]潘光华，来金梅，陈利光等，“FPGA可编程逻辑单元时序功能的设计实现”电子学报，2008．(08)
[54]Zdenek Vasicek,Lukas Sekanina“An Area-Efficient Alternative to Adaptive Median Filtering in FPGAs”,International Conference on Field Programmable Logic and Applications,2007.
[55]Zdenek Vasicek and Lukas Sekanina,“Evaluation of a New Platform For Image Filter Evolution”,Conference on Adaptive Hardware and Systems(AHS 2007)Computation,3(3):167-196,1999.
[56]R Nirmal Kumar,S.Suresh and Prof.J.Raja Paul Perinbam,“Digital Image Filter Design using Evolvable Hardware”,International Conference on Computer and Information Science(ICIS'05)
[57]Mirfakhraei,N.;Yongqun Tang;“Performance analysis of Benes networks under nonuniform traffic”Communications,1996.ICC 96,Conference Record,Converging Technologies for Tomorrow's Applications.1996 IEEE International Conference on Volume 3,23-27 June 1996 Page(s):1669-1673 vol.3
[58]Gonzalez R.C,Woods R.E.“Digital hnage Processing,3~(rd)”.ed.,Addison-Wseley,1992
[59]John C.Gallagher,Saranyan Vigraham,and Gregory Kramer,“A Family of Compact Genetic Algorithms for Intrinsic Evolvable Hardware”,IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION,VOL.8,NO.2,APRIL 2004
[60]Lukas Sekanina“Novel 3x3 image filters implemented in hardware“http://www.fit.vutbr.cz/～sekanina”
[61]侯慧、马晓骏、来金梅、童家榕、孙劫、陈利光，“适用于数据通路的可编程逻辑器件FDP100K”，电子学报，2005
[62]来金梅，陈利光，童家榕“一种现场可编程逻辑阵列布线资源结构及其建模方法”专利申请号：2007100380994
[63]Li-Guang Chen,Kan-Wen Wang,Jin-Mei Lai,Jia-Rong Tong“A Novel Hybrid FPGA Architecture”ICSICT 2006,23～26 Oct 2006,ShangHai
[64]Li-Guang Chen,Jin-Mei Lai,Jia-Rong Tong“An AND-LUT Based Hybrid FPGA Architecture”半导体学报,P19,VOL.28,NO.3,Mar 2007
[65]LiGuang Chen,YaBin Wang,JinMei Lai,Jiarong Tong,Rui Tu,“Design and Implementation of FDP Chip”半导体学报,P713,VOL.29,NO.4,Apr 2008。
[66]LiGuang Chen,YaBin Wang,JinMei Lai,Jiarong Tong,Rui Tu,Fang Wu,GuanHua Pan,QiuShi Shen,Huowen Zhang,Jian wang,Yuan wang“Architecture and implementation of FDP250K FPGA”SPL2008,26～29 Mar 2008, Argentina
[67]Fang Wu, Huowen Zhang, JinMei Lai, Liguang Chen, Lei Duan, Jiarong Tong "Design and Implementation of a Delay-Optimized Universal Programmable Routing Circuit for FPGA " ASPDAC2009
[68] V. Betz and J. Rose, "VPR: A New Packing, Placement and Routing Tool for FPGA Research," [C] Int. Workshop on Field-Programmable Logic and Applications, pp. 213 - 222, Sept. 1997.
[69]Xilinx Corporation .Application Note Xapp151.Virtex series configuration architecture user guide v1.7.
[70] Yann Thoma, Eduardo Sanchez, A Reconfigurable Chip for Evolvable Hardware Genetic and Evolutionary Computation - GECCO 2004
[71]Xilinx Corporation, "Virtex-II Pro and Virtex-II Pro X Platform FPGAs:Complete Data Sheet" DS083, 2005
[72] Atmel, "AT94KAL Series Field Programmable System Level Integrated Circuit"FPSLI datasheet.
[73]Triscend, "A7V Field-Configurable System-on-Chip Family" datasheet.
[74]Xilinx Corporation, "PLB IPIF datasheet", DS458.
[2]王正志，薄涛，“进化计算”，长沙：国防科技大学出版社，2000
[3]Stoica A.“Evolvable hardware:from on-chip circuit synthesis to evolvable space systems”Proceedings."IEEE International Symposium on Multiple-Valued Logic,2000.(ISMVL 2000)
[4]Stoica A.,Zebulum R.,Keymeulen D..“Progress and challenges in building evolvable device”,Proceedings.“The Third NASA/DoD Workshop on,Evolvable Hardware”,2001
[5]A.Thompson,“Evolving Electronic Robot Controllers that Exploit Hardware Resources,”in Advances in Artificial Lrfe:Proc.3rd European Conference on Artificial life,1995,pp.640-656
[6]S.Thorsten and X.Yao,“Using Negative Correlation to Evolve Fault-Tolerant Circuits,”in the 5th International Conference on Evolvable Systems,Trondheim,Norway,2003,pp.35-46.
[7]Garis H D.“Evolvable Hardware Genetic Programming of a Darwin Machine in:Branko Soucek and the IRIS Group(Eds.)”,Dynamic,Genetic and Chaotic Programming.John Willey&Sons,Inc.,373-393,1992
[8]Hugo de Garis,“Exploring GenNet Behaviors:Using Genetic Programming to Explore Qualitatively New Behaviors in Recurrent Neural Networks”,Int.Joint Conference on Neural Networks”,Baltimore,USA,June 1992
[9]http://www.smi.stanford.edu/people/koza
[10]http://www.cogs.susx.ac.uldusers/adrianth
[11]http://www.etl.go.jp:8080/etl/kikou/ehw.html
[12]A.Thompson,“Explorations in Design Space:Unconventional Electronics Design Through Artificial Evolution”,IEEE Transation on Evolutionary Computation,1999,3(3),167-196
[13]T.Higuchi,M.Iwata,l.Kajitani,H.Yamada,B.Manderick,Y Hirao,M.Murakawa,S.Yoshizawa,T.Fumya,“Evolvable Hardware with Genetic Learning”,Proceedings of the IEEE International Symposium on Circuits and Systems,1996,Vol.4,29-32
[14]T.Higuchi,M.Iwata,I.Kajitani,H.Iba,T.Furuya,Mandeik,“Evolvable Hardware and its Applications to Pattern Recognition and Fault-tolerant System”,Towards Evolvable Hardware:The Evolutionary Engineering Approach(Lecture Notes in Computer Science),Springer-Verlag,1996,Vol.1062,118-135
[15]T.Higuchi,“Real-World Applications of Analog and Digital Evolvable Hardware”,IEEE Transaction on Evolutionary Computation,1999,3(3),220-235
[16]G Tufte et al.,“Evolving an Adaptive Digital Filter”,Proceedings of the Second NASA/DOD Workshop on Evolvable Hardware,CA:Palo Alto,U.S.A,2000,143-15
[17]J.R.Koza et al.,“Automated Synthesis of Analog Electrical Circuits by Means of Genetic Programming”,IEEE Transaction on Evolutionary Computation,1997,1(2),109-128
[18]A.Stoica et al.,“Evolution of Analog Circuits on Field Programmable Transistor Arrays”,Proceedings of the Second NASA/DOD Workshop on Evolvable Hardware,CA:Palo Alto,U.S.A,2000,99-108
[19]R Zebulum et al.,“A Reconfigurable Platform for the Automatic Synthesis of Analog Circuits”,Proceedings of the Second NASA/DOD Workshop on Evolvable Hardware,CA:Palo Alto,U.S.A,2000,91-98
[20]J.Torresen,“A Divide-and-Conquer Approach to Evolvalbe Hardware”,Proceedings of the Second International Conference on Evolvable Systems:From Biology to Hardware(ICES'98),1998,57-65
[21]T.Kalganova,“Bidirectional Incremental Evoiution in Extrinsic Evolvable Hardware”,Proceedings of the Second NASA/DOD Workshop on Evolvable Hardware,CA:Palo Alto,U.S.A,2000,65-74
[22]V Vassilev,J.Miller,“Scalability Problems of Digital Circuit Evolution:Evolvablility and Efficient Designs”,Proceedings of the Second NASA/DOD Workshop on Evolvable Hardware,CA:Palo Alto,U.S.A,2000,55-64
[23]陈毓屏等一个新的研究领域—演化硬件．航空计算技术，1998，28(1)：1-8
[24]康立山，何巍，陈毓屏．“用函数型可编程逻辑器件实现演化硬件．计算机学报，1999，22(7)：781-784
[25]曾三友，颜雪松，康立山．“演化硬件及其在深空探测应用可行性研究”．中国宇航
[26]赵曙光等．“基于函数级FPGA原型的演化硬件内部进化”，计算机学报，2002 25(5)，666-669
[27]赵曙光等，“基于进化的电子电路自动设计方法”，电路与系统学报，2002，7p72-78
[28]赵曙光等，“一种基于演化硬件的染色体编码新方法”，西安电子科技大学学报，2000，27(6)：778-780
[29]赵曙光等，“可进化硬件的基本原理与关键技术”，系统工程与电子技术，2002p70-73
[30]J.He,X.Wang,M.Zhang,and Q.Fang,“New Research on Scalability of Lossless Image Compression by GP Engine,”in 2005 NASA/DoD Conference on Evolvable Hardware,2005,pp.160-164.
[31]方潜生，王煦法，何劲松，“硬件进化的快速算法模型研究”，中国科学技术大学学报，vol．33(5)，pp．612-618，2003．
[32]林勇，罗文坚，王煦法，“硬件电路的选择性进化冗余”，中国科学技术大学学报，vol．36(5)，pp．523-529，2006．
[33]林勇，罗文坚，钱海，王煦法，“n×n阵列胚胎电子系统应用中的优化设计问题分析”，中国科学技术大学学报，vol．37(2)，pp．171-176，2007．
[34]Andrew J.Greensted,“RISA:A Hardware Platform for Evolutionary Design”,Proceedings of the 2007 IEEE Workshop on Evolvable and Adaptive Hardware
[35]Yann Thoma,Eduardo Sanchez,“A Reconfigurable Chip for Evolvable Hardware Genetic and Evolutionary Computation”-GECCO 2004
[36]X.Yao and T.Higuchi,“Promises and Challenges of Evolvable Hardware”,IEEE Transactions on Systems,Man,and Cybernetics,Part C,vol.29,pp.87-97,February 1998.
[37]M.lwata,I.Kajitani,H.Yamada,and T.Higuchi,“A pattern recognition system using evolvable hardware,”Parallel Problem Solving from Nature Ⅳ,Berlin,Germany,1996,pp.761-770
[38]Xilinx Corporation,“XC6200 Field Promable Gate Arrays Product Specification”,1997
[39]Xilinx Corporation,“Virtex-E Field Promable Gate Arrays Product Specification”,DS022,2002
[40]Xilinx Corporation,“Virtex-Ⅱ Platform FPGAs:Complete Data Sheet”DS031,2005
[41]Xilinx Corporation,“Virtex-Ⅱ Pro and Virtex-Ⅱ Pro Ⅹ Platform FPGAs:Complete Data Sheet”DS083,2005
[42]Hollingworth,G.Smith,S.Tyrrell,A“Safe Intrinsic Evolution of Virtex Devices”,Evolvable Hardware,2000.Proceedings
[43]Glette,K.Torresen,J.Yasunaga,M.Yamaguchi,Y.“On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition”,Adaptive Hardware and Systems,2006
[44]“An evolvable hardware system in Xilinx Virtex Ⅱ Pro FPGA”,International Journal of Innovative Computing and Applications,Volume 1,Issue 1(April 2007)
[45]Kyrre Glette and Jim Torresen,“A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-Ⅱ Pro Device”Evolvable Systems:From Biology to Hardware pp.66-75
[46]Lukas Sekanina,Tomas Martinek and Zbysek Gajda“Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules”,IEEE Congress on Evolutionary Computation,2006
[47]Higuichi T.“Evolvable Hardware at Function Level”.In Proc.1997 IEEE Int.Conf Evolutionary Computation,(ICES'97),1997:187-192
[48]Z.Vasicek and L.Sekanina.“An evolvable hardware system in Xilinx Virtex Ⅱ Pro FPGA”.Int.J.Innovative Computing and Applications,1(1):63-73,2007.
[49]Stomeo,E.Kalganova,T.Lambert,C.Lipnitsakya,N.Yatskevich,Y.“On evolution of relatively large combinational logic circuits Evolvable Hardware”,2005.Proceedings.2005 NASA/DoD Conference
[50]Keum-Sung Hwang,Sung-Bae Cho,“Evolving diverse hardware's using speculated genetic algorithm”,Proceedings of the 2002 Congress on Evolutionary Computation,Volume 1,Issue,12-17 May 2002 Page(s):437-442
[51]Sin Man Cheang;Kin Hong Lee;Kwong Sak Leung,“applying genetic parallel programming to synthesize combinational logic circuits”,Evolutionary Computation,IEEE Transactions on Volume 11,Issue 4,Aug.2007 Page(s):503-520
[52]Sekanina,L.Friedl,“On Routine Implementation of Virtual Evolvable Devices Using COMBO6,”In Proc.of the 2004 NASA/DoD Conference on Evolvable Hardware,Seattle,USA,IEEE Computer Society Press,2004,pp.63-70
[53]潘光华，来金梅，陈利光等，“FPGA可编程逻辑单元时序功能的设计实现”电子学报，2008．(08)
[54]Zdenek Vasicek,Lukas Sekanina“An Area-Efficient Alternative to Adaptive Median Filtering in FPGAs”,International Conference on Field Programmable Logic and Applications,2007.
[55]Zdenek Vasicek and Lukas Sekanina,“Evaluation of a New Platform For Image Filter Evolution”,Conference on Adaptive Hardware and Systems(AHS 2007)Computation,3(3):167-196,1999.
[56]R Nirmal Kumar,S.Suresh and Prof.J.Raja Paul Perinbam,“Digital Image Filter Design using Evolvable Hardware”,International Conference on Computer and Information Science(ICIS'05)
[57]Mirfakhraei,N.;Yongqun Tang;“Performance analysis of Benes networks under nonuniform traffic”Communications,1996.ICC 96,Conference Record,Converging Technologies for Tomorrow's Applications.1996 IEEE International Conference on Volume 3,23-27 June 1996 Page(s):1669-1673 vol.3
[58]Gonzalez R.C,Woods R.E.“Digital hnage Processing,3~(rd)”.ed.,Addison-Wseley,1992
[59]John C.Gallagher,Saranyan Vigraham,and Gregory Kramer,“A Family of Compact Genetic Algorithms for Intrinsic Evolvable Hardware”,IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION,VOL.8,NO.2,APRIL 2004
[60]Lukas Sekanina“Novel 3x3 image filters implemented in hardware“http://www.fit.vutbr.cz/～sekanina”
[61]侯慧、马晓骏、来金梅、童家榕、孙劫、陈利光，“适用于数据通路的可编程逻辑器件FDP100K”，电子学报，2005
[62]来金梅，陈利光，童家榕“一种现场可编程逻辑阵列布线资源结构及其建模方法”专利申请号：2007100380994
[63]Li-Guang Chen,Kan-Wen Wang,Jin-Mei Lai,Jia-Rong Tong“A Novel Hybrid FPGA Architecture”ICSICT 2006,23～26 Oct 2006,ShangHai
[64]Li-Guang Chen,Jin-Mei Lai,Jia-Rong Tong“An AND-LUT Based Hybrid FPGA Architecture”半导体学报,P19,VOL.28,NO.3,Mar 2007
[65]LiGuang Chen,YaBin Wang,JinMei Lai,Jiarong Tong,Rui Tu,“Design and Implementation of FDP Chip”半导体学报,P713,VOL.29,NO.4,Apr 2008。
[66]LiGuang Chen,YaBin Wang,JinMei Lai,Jiarong Tong,Rui Tu,Fang Wu,GuanHua Pan,QiuShi Shen,Huowen Zhang,Jian wang,Yuan wang“Architecture and implementation of FDP250K FPGA”SPL2008,26～29 Mar 2008, Argentina
[67]Fang Wu, Huowen Zhang, JinMei Lai, Liguang Chen, Lei Duan, Jiarong Tong "Design and Implementation of a Delay-Optimized Universal Programmable Routing Circuit for FPGA " ASPDAC2009
[68] V. Betz and J. Rose, "VPR: A New Packing, Placement and Routing Tool for FPGA Research," [C] Int. Workshop on Field-Programmable Logic and Applications, pp. 213 - 222, Sept. 1997.
[69]Xilinx Corporation .Application Note Xapp151.Virtex series configuration architecture user guide v1.7.
[70] Yann Thoma, Eduardo Sanchez, A Reconfigurable Chip for Evolvable Hardware Genetic and Evolutionary Computation - GECCO 2004
[71]Xilinx Corporation, "Virtex-II Pro and Virtex-II Pro X Platform FPGAs:Complete Data Sheet" DS083, 2005
[72] Atmel, "AT94KAL Series Field Programmable System Level Integrated Circuit"FPSLI datasheet.
[73]Triscend, "A7V Field-Configurable System-on-Chip Family" datasheet.
[74]Xilinx Corporation, "PLB IPIF datasheet", DS458.